論文 - 石黒　仁揮

High-frequency characterization of intrinsic FinFET channel

Sakai H., O'Uchi S., Matsukawa T., Endo K., Liu Y.X., Tsukada T., Ishikawa Y., Nakagawa T., Sekigawa T., Koike H., Sakamoto K., Masahara M., Ishikuro H.

Proceedings - IEEE International SOI Conference 2010年12月

ISSN  1078621X

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0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit

Johari A., Kumaki S., Matsubara T., Hayashi I., Ishikuro H.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS    232 - 235 2010年12月

　概要を見る

In this paper we have shown the design of a 0.5 V multi-phase digital controlled oscillator (DCO) in 65-nm CMOS. The DCO generates 32 phases and achieved output frequency range from 0.1MHz to 128MHz with maximum power consumption of 0.28μW/MHz in Cadence spectre circuit simulations. To prevent glitch during phase switching, the circuit for smooth phase transition is proposed and successfully demonstrated in circuit simulation. © 2010 IEEE.

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A 0.5V 6-bit scalable phase interpolator

Kumaki S., Johari A., Matsubara T., Hayashi I., Ishikuro H.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS    1019 - 1022 2010年12月

　概要を見る

This paper proposes a scalable phase interpolator (PI) with dual-input inverter. A pseudo-pipelined architecture is proposed to realize resolution scalability and to reduce the circuit size and power consumption. By using a simple architecture, the proposed circuit operates at 0.5V at which conventional analog PI cannot operate. Slew rate of inverter chain is controlled by current starving technique to support phase interpolation at wide input frequency range. The PI was designed in 65nm-CMOS technology. The circuit simulation confirms 6-bit phase resolution, DNL of 0.41 LSB, and INL of 1.25 LSB. The power consumption is 0.12 μW/MHz. © 2010 IEEE.

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A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator

Shikata A., Sekimoto R., Ishikuro H.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS    1015 - 1018 2010年12月

　概要を見る

This paper presents a twice the supply voltage bootstrapped switch with the proposed rise time accelerator that has high linearity and fast rising with single phase clock input at low voltage. The proposed rise time accelerator improves rising time and ensures circuit operation at extremely low supply voltage without any complex timing generation circuit. The prototype switch is designed in 65nm CMOS process and the simulation results show that the power consumption of quasi differential bootstrapped switch is less than 11nW/MHz at a supply voltage of 0.5V with 10MS/sec. The third order harmonic distortion (HD3) is 104dB with sampling capacitor of 1.28pF. © 2010 IEEE.

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A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

Hayashi I., Matsubara T., Kumaki S., Johari A., Ishikuro H., Kuroda T.

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010    225 - 228 2010年12月

　概要を見る

A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL). ©2010 IEEE.

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Simultaneous 6Gb/s data and 10mW power transmission using nested clover coils for non-contact memory card

Yuan Y., Radecki A., Miura N., Aikawa I., Take Y., Ishikuro H., Kuroda T.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers    199 - 200 2010年10月

　概要を見る

This paper presents a non-contact memory card and a host employing simultaneous data and power transmission through inductive coupling. Nested clover-shaped data coils are proposed for reducing interference from a power link. The host wirelessly tracks current consumption of the card and adjusts transmit power to improve power transfer efficiency. The prototype is implemented in 65nm CMOS. It achieves 6Gb/s data rate and almost 10% power transfer efficiency over a 100-2kΩ range of the load. © 2010 IEEE.

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Wireless proximity interfaces with a pulse-based inductive coupling technique

Ishikuro H., Kuroda T.

IEEE Communications Magazine （IEEE）  48 （ 10 ） 192-199 - 199 2010年10月

研究論文（学術雑誌）, 単著, 査読有り,  ISSN  01636804

　概要を見る

The rapid performance progress in processors and memory cores by technology scaling requires further improvement in interface bandwidth. However, interface bandwidth is not keeping up with the processing speed of the core and is becoming a bottleneck in system performance. To fill the performance gap, wideband lowpower low-cost interfaces are strongly demanded. A wireless proximity interface that uses inductive coupling is one such interface expected to be used for interchip links in high-performance 3D system integration. Inductive coupling interfaces use the magnetic near-field induced by micro-coils. The coils (channels) can be arranged in a dense array because magnetic near-field localizes in the proximity of each coil, and crosstalk between the channels is small. Therefore, inductive coupling interfaces are suitable for wideband low-cost proximity communication. An inductive coupling interface can also realize highly reliable communication with low power consumption. Evaluation systems developed to study the performance of inductive coupling interfaces have demonstrated the feasibility of the interfaces in a wide range of applications. © 2010 IEEE.

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47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Saito M., Yoshida Y., Miura N., Ishikuro H., Kuroda T.

IEEE Transactions on Circuits and Systems I: Regular Papers （IEEE）  48 （ 10 ） 192-199 - 2278 2010年10月

研究論文（学術雑誌）, 単著, 査読有り,  ISSN  15498328

　概要を見る

This paper presents a power reduction scheme and an area reduction scheme in inductive-coupling programmable bus for NAND flash memory stacking. A channel arrangement scheme using three coils enables random access for memory read and memory write. Transmit power is reduced by 47% compared to a previous design with shields. A coil layout style, herein noted as XY coil, allows for the coils to interleave with logic interconnections, resulting in area reduction of 91% relative to at the expense of only 17% transmit power increase. Relayed data transmission at 1.6 Gb/s and BER < 10-12 is achieved. © 2010 IEEE.

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Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip link for low-power 3-D system integration

Niitsu K., Kohama Y., Sugimori Y., Kasuga K., Osada K., Irie N., Ishikuro H., Kuroda T.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems （IEEE）  18 （ 8 ） 1238-1243 - 1243 2010年08月

研究論文（学術雑誌）, 単著, 査読有り,  ISSN  10638210

　概要を見る

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions. © 2006 IEEE.

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A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card

Kawai S., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 53   264 - 265 2010年05月

ISSN  01936530

　概要を見る

An inductive-coupling link has been studied for inter-chip communications in System-in-a-Package [1]. Its communication distance extends millimeter ranges [2,3] and it can be used as a wireless interface for non-contact memory cards. High speed and low power communication can be performed in the inductive-coupling link because of the removal of highly capacitive ESD protection devices [1]. The wireless interface eliminates mechanical contacts resulting in high reliability. Target data rate is 2.5Gb/s/ch which is 12.5x higher than that of a commercial memory card and target communication range is 0.5mm to 1mm, considering the allowance of card insertion. The maximum data rate of the inductive-coupling link demonstrated in [3] at 1mm distance was 160Mb/s/ch. A theoretical limit is 1Gb/s/ch since self resonant frequency of an on-chip inductor of 3GHz. To increase the self resonant frequency, the inductor is moved off chip to a flexible circuit board to reduce parasitic capacitance. The self resonant frequency of 1mm diameter inductor is increased to 4GHz corresponding to a signal data rate of 1.25Gb/s/ch. Additionally, the number of bit per symbol is increased to 2 by 4 pulse amplitude modulation (4PAM) and a data rate of 2.5Gb/s/ch is achieved. But to communicate by using 4PAM in the inductive-coupling link, issues listed below must be solved. First, the communication range is limited to 0.95mm to 1mm. The amplitude of the received signal is inversely proportional to the communication distance, and therefore, received signal cannot be converted to a correct data without adjusting the input threshold voltages of a receiver. Second, the pulse width is narrower in 4PAM and thus synchronization on the receiver side is difficult. ©2010 IEEE.

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2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking

Saito M., Sugimori Y., Kohama Y., Yoshida Y., Miura N., Ishikuro H., Sakurai T., Kuroda T.

IEEE Journal of Solid-State Circuits （IEEE）  45 （ 1 ） 134-141 - 141 2010年01月

研究論文（学術雑誌）, 単著, 査読有り,  ISSN  00189200

　概要を見る

An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuitlayout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8. © 2009 IEEE.

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A High-Speed Inductive-Coupling Link With Burst Transmission

N. Miura, Y. Kohama, Y. Sugimori, H. Ishikuro, T. Sakurai, T. Kuroda

IEEE Journal of Solid-State Circuits （IEEE）  44 （ 3 ） 945-955 2009年03月

研究論文（学術雑誌）, 単著, 査読有り

A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna

V.V.Kulkarni, M. Muqsith, K. Niitsu, H. Ishikuro, T. Kuroda

IEEE Journal of Solid-State Circuits （IEEE）  44 （ 2 ） 394-403 2009年02月

研究論文（学術雑誌）, 単著, 査読有り

A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping

N. Miura, H. Ishikuro, K. Niitsu, T. Sakurai, H. Kuroda

IEEE Journal of Solid-State Circuits （IEEE）  43 （ 1 ） 285-291 2008年01月

研究論文（学術雑誌）, 単著, 査読有り

60% Power Reduction in Inductive-Coupling Inter-Chip Link by Current-Sensing Technique

K. Niitsu, N. Miura, M. Inoue, Y. Nakagawa, M. Tago, M. Mizuno, H. Ishikuro, and T. Kuroda

Japanese Journal of Applied Physics （JSAP）  46 （ 4B ） 2215-2219 2007年04月

研究論文（学術雑誌）, 共著, 査読有り

An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors

K.Ishida, A.Tamtrakarn, H.Ishikuro, M.Takamiya, and T. Sakurai,

IEICE Trans. Electron. （IEICE）  E90-C （ 4 ） 786-792 2007年04月

研究論文（学術雑誌）, 単著, 査読有り

A 2.4-GHz Temperature compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitter

T. Tanzawa, H. Shibayama, R. Terauchi, K. Hisano, H. Ishikuro, S. Kousai, H.Majima, H. Kobayashi, T. Takayama, K. Agawa, M. Koizumi, and F. Hatori

IEICE Trans. Electron （電子情報通信学会）  E88-C4 （ 4 ）  2005年04月

研究論文（研究会，シンポジウム資料等）, 共著, 査読有り

A Full-CMOS Single Chip Bluetooth LSI with 1.5MHz-IF Receiver and Direct Modulation Transmitter

F. Hatori, H. Ishikuro, M. Hamada, K. Agawa, S. Kousai, H. Kobayashi, and D.M.Nguyen

IEICE Trans. Electron. （電子情報通信学会）  E87-C （ 4 ）  2004年04月

研究論文（学術雑誌）, 共著, 査読有り

Large Electron Addition Energy above 250 meV in the Silicon Quantum Dot in a Single Electron Transistor

M. Saitoh, N. Takahashi, H. Ishikuro, and T. Hiramoto

Japanese Journal of Applied Physics 40 （ 3B ） 2010 - 2012 2001年03月

研究論文（学術雑誌）, 共著, 査読有り

Effects of interface traps in silicon-quantum-dots-based memory structures

X. L. Yuan, Y. Shi, S. L. Gu, J. M. Zhu, Y. D. Zheng, K. Saito, H. Ishikuro, and T. Hiramoto

Physica E 8 （ 2 ） 189-193 2000年08月

研究論文（学術雑誌）, 共著, 査読有り