論文 - 石黒　仁揮

A Discrete-Time Model for Frequency Modulated Charge Pumps with Synchronized Controller

Tan Y., Ishikuro H.

Midwest Symposium on Circuits and Systems （Midwest Symposium on Circuits and Systems）  2020-August   929 - 932 2020年08月

ISSN  9781538629161

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© 2020 IEEE. This paper presents a discrete-time based approach for frequency modulated charge pumps with synchronized controller. In order to handle the varying frequency, this paper first introduced a method to calculate the output voltage of an open-loop charge pump with predefined frequencies, which is improved from a fixed frequency open-loop model verified in previous research. Then a closed-loop model is proposed for synchronized frequency controllers. An algorithm is hence created from the closed-loop model to simulate the output of charge pumps. The simulation result shows a competitive accuracy and much faster speed when comparing it with transistor level simulations. Overall, this paper demonstrated its value in terms of modeling the frequency modulated charge pumps and hence assisted the top-down design flow.

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A Wide Input-Range, Low-Power and Highly Flexible 18 Bit Time-to-Digital Converter with Compact Differential Circuit Topology

Toth P., Ishikuro H.

Midwest Symposium on Circuits and Systems （Midwest Symposium on Circuits and Systems）  2020-August   937 - 940 2020年08月

ISSN  9781538629161

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© 2020 IEEE. This paper presents a wide-dynamic-range high-resolution time-domain converter concept tailored for low-power sensor interfaces. The unique system structure applies different techniques to reduce circuit complexity, power consumption, and noise sensitivity. A multi-cycle concept, which allows a virtual delay line extension, is applied to achieve high resolution down to 1 ns. At the same time, it expands the dynamic range drastically up to 2.35 ms. Moreover, individually tunable delay elements in the range of 1 ns to 12 ns allow on the one hand on-demand flexible operation in a low- or high-resolution mode for smart sensing applications and flexible power control. On the other hand, delay stage mismatch calibration. The concept of this paper is evaluated through both simulation and hardware by a custom-designed PCB using commercially available components. An HDL state machine operates as control logic on a generic FPGA. The presented concept is highly suitable for on-chip integration.

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A digital-to-resistance converter with an automatic offset calibration method for evaluating dynamic performance of resistive sensor readout circuits

Nakagawa S., Miyazaki T., Ishikuro H.

I2MTC 2020 - International Instrumentation and Measurement Technology Conference, Proceedings （I2MTC 2020 - International Instrumentation and Measurement Technology Conference, Proceedings）  2020年05月

ISSN  9781728144603

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© 2020 IEEE. In this paper, a digital-to-resistance converter (DRC) with automatic offset calibration circuits is proposed. This circuit is used to evaluate the dynamic performance of resistive sensor readout circuits. The proposed DRC consists of a digital-to-analog converter, an analog multiplier, a fixed-value reference resistor, and current sources. A wide-range resistance changing at high frequency is achieved with the proposed DRC. In order to minimize the resistance error caused by the offset voltage of op-amps, an automatic offset calibration method is proposed. This developed prototype DRC achieved 96.3 dB dynamic range, 56.1 dB SNDR at 10kHz, and a maximum operating frequency is 100kHz.

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A linearity testing of cascaded analog mixed-signal blocks using SEIR method

Ishikawa T., Pai C.W., Ishikuro H.

I2MTC 2020 - International Instrumentation and Measurement Technology Conference, Proceedings （I2MTC 2020 - International Instrumentation and Measurement Technology Conference, Proceedings）  2020年05月

ISSN  9781728144603

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© 2020 IEEE. This paper proposes a method to separate distortions of the input signal, amplifier, and analog-to-digital converter (ADC), which are cascaded blocks in the testing of an analog front-end system. The proposed technique extends the stimulus error identification and removal (SEIR) method to separate the low-quality input test signal, the nonlinearity of amplifier and ADC. The system model was built by using MATLAB/Simulink, and the nonlinearity of the input signal with distortion, amplifier, and ADC were successfully separated. With a 12-bit ADC, the estimation error of each block is less than 1 LSB in the simulation, and the proposed method was verified by measurement. The relations between the estimation error, calculation cost and each parameter in the proposed method are systematically studied.

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Low-Power and ppm-Level Multimolecule Detection by Integration of Self-Heated Metal Nanosheet Sensors

Tanaka T., Yanagida T., Uchida K., Tabuchi K., Tatehora K., Shiiki Y., Nakagawa S., Takahashi T., Shimizu R., Ishikuro H., Kuroda T.

IEEE Transactions on Electron Devices （IEEE Transactions on Electron Devices）  66 （ 12 ） 5393 - 5398 2019年12月

ISSN  00189383

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© 1963-2012 IEEE. H2 and NH3 detection with low power consumption was demonstrated by integrated chemiresistive Pt and PtRh nanosheet sensors on glass substrates. The self-heating effects realized low power and local heating of metal nanosheet sensors, enabling the integration of sensors with different operating temperatures. Based on different resistance changes in Pt and PtRh nanosheets toward H2 and NH3, the concentration of each gas was detected from a gas mixture by consuming around 1-mW power. For decreasing the power consumption and further integration of sensors, sensor scaling and pulsed operations were numerically and experimentally studied. In addition to good connectivity of metal nanosheet sensors to large-scale integration (LSI) circuits, improvements of the power consumption by sensor scaling were proven. The pulsed operations required for integrated sensor arrays maintained a sensor response, or a resistance change, of approximately 60%, even when the power consumption was reduced by 20%.

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High-resolution auto-balancing wheatstone-bridge with successive approximation of Δ Σ-Modulated digitally controlled variable resistor

Miyazaki T., Nakagawa S., Ishikuro H.

2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 （2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019）     474 - 477 2019年11月

ISSN  9781728109961

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© 2019 IEEE. This paper describes a high-resolution, highly linear, low power amp-less sensor interface. A Wheatstone-bridge with ΔΣ-modulated digitally controlled variable resistor is proposed. The proposed bridge is automatically balanced by successive approximation (SA) of the digitally controlled resistor, which can eliminate power consuming amplifiers and ADCs. To overcome conversion speed limitation caused by settling time of each SA step, the output differential voltage of the bridge is shorted in advance to the comparison phase of each SA step. A developed prototype system achieved 9.68 bit resolution in target resistance range of three orders of magnitude and conversion speed improvement by 66%.

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Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits

Yoshioka K., Sugimoto T., Waki N., Kim S., Kurose D., Ishii H., Furuta M., Sai A., Ishikuro H., Itakura T.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems （IEEE Transactions on Very Large Scale Integration (VLSI) Systems）  27 （ 11 ） 2575 - 2586 2019年11月

ISSN  10638210

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© 1993-2012 IEEE. To realize high-resolution pipelined and pipelined-SAR analog-to-digital-converters (ADCs), an accurate residue amplifier is necessary. However, realizing such an amplifier in scaled CMOS is challenging due to the worsened transistor characteristics. Prior works focused on gain calibration techniques to mitigate the use of low-gain amplifiers, in return of system complexity and prolonged startups. In this paper, we introduce a digital amplifier (DA) technique to realize power-efficient and accurate amplification in scaled CMOS. DA cancels out all errors (i.e., gain error, nonlinearity, incomplete settling, power supply noise, and thermal noise) of the low-gain amplifier by feedback based on successive approximation. The DA accuracy can be arbitrary set by configuring the number of bits in the DA capacitor digital-to-analog-converter; the amplifier gain is decoupled from the transistor intrinsic gain which is suitable for scaled CMOS integration. We also show that the power efficiency can be enhanced over conventional opamp-based designs with relaxed settling error requirements of DA-based multiplying digital-to-analog-converters (MDACs). Moreover, the circuit design of DA-based MDACs is further discussed. Measurement results of the calibration-free 0.7-V 12-bit 160-MS/s pipelined-SAR ADC implemented in 28-nm CMOS are reported. Without calibration, the ADC achieves signal-to-noise-and-distortion-ratio = 61.1 dB, figure-of-merit = 12.8 fJ/conv., which is over 3× improvement compared with conventional calibration-free high-speed pipelined ADCs. In addition, we evaluate the DA's process scalability by comparing the measured results of the DA-based MDAC prototyped in 65-and 28-nm CMOS. We observe 2×-3× improvement in speed, power, and area mainly resulting from the DA's process scalability.

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A High Accuracy Opamp-less Interface Circuit for 2-D Cross-Point Resistive Sensor Array with Switch Resistance Calibration

Shiiki Y., Ishikuro H.

Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption （Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption）     105 - 108 2019年11月

ISSN  9781728129402

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© 2019 IEEE. In this paper, a new readout method for a 2-D cross-point resistive sensor array with an opamp-less interface circuit is proposed. To avoid the readout inaccuracy caused by nonidealities of an opamp in the conventional readout circuit, our proposed circuit does not use any opamps. A switch resistance calibration technique is also proposed to remove effectively the negative effects of switch nonidealities, which bring high readout accuracy and wide scalability of a target resistive array. To evaluate the readout accuracy in the proposed method, simulation is carried out and the readout error less than 0.06% with 16-bit ADCs in 32×32 resistive array is achieved.

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A differential-ring-oscillator with up to 35 dBc/Hz phase noise improving amplitude feedback loop for ultra low power systems

Toth P., Ishikuro H.

2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 （2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019）     350 - 353 2019年11月

ISSN  9781728109961

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© 2019 IEEE. This work presents a novel idea to dynamically control a differential ring oscillators biasing in order to improve the phase noise performance in the ultra low power domain. This proposed feedback system can be flexibly applied on any type of fully-differential ring oscillator with a tail current source. The following paper covers theoretical and simulative considerations to prove the feasibility of this idea. Finally measurements of a 180 nm standard CMOS integrated prototype system depict the implementability of this idea. A phase noise improvement of up to 35 dBc/Hz can be observed with an active control loop. Moreover, the tuning range of the implemented ring oscillator is extended by 434% in contrast to fixed bias operation. These values are measured at a minimum oscillation power consumption of 55 pW/Hz.

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Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets

Tanaka T., Tabuchi K., Tatehora K., Shiiki Y., Nakagawa S., Takahashi T., Shimizu R., Ishikuro H., Kuroda T., Yanagida T., Uchida K.

Digest of Technical Papers - Symposium on VLSI Technology （Digest of Technical Papers - Symposium on VLSI Technology）  2019-June   T158 - T159 2019年06月

ISSN  9784863487178

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© 2019 The Japan Society of Applied Physics. Ppm-level hydrogen and ammonia in air were recognized by low-power, integrated sensors consisting of catalytic metal nanosheets. Thermal energy necessary for catalytic reactions were given by Joule heating not by external heaters. The ther-mal-aware design of sensors reduces the power consumption to 0.14 mW. The low-power and small-area properties enable large-scale, on-chip integration of molecular sensors, which will be useful in IoT era. A sensor array was successfully connected to a platform with wireless connectivity.

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Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets

Tanaka T., Tabuchi K., Tatehora K., Shiiki Y., Nakagawa S., Takahashi T., Shimizu R., Ishikuro H., Kuroda T., Yanagida T., Uchida K.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers （IEEE Symposium on VLSI Circuits, Digest of Technical Papers）  2019-June   T158 - T159 2019年06月

ISSN  9784863487185

　概要を見る

© 2019 JSAP. Ppm-level hydrogen and ammonia in air were recognized by low-power, integrated sensors consisting of catalytic metal nanosheets. Thermal energy necessary for catalytic reactions were given by Joule heating not by external heaters. The thermal-aware design of sensors reduces the power consumption to 0.14 mW. The low-power and small-area properties enable large-scale, on-chip integration of molecular sensors, which will be useful in IoT era. A sensor array was successfully connected to a platform with wireless connectivity.

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A high-resolution time-based resistance-to-digital converter with TDC and counter

Nakagawa S., Horikoshi K., Ishikuro H.

Midwest Symposium on Circuits and Systems （Midwest Symposium on Circuits and Systems）  2018-August   242 - 245 2019年01月

ISSN  9781538673928

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© 2018 IEEE This paper presents a high resolution time-based resistance-to-digital converter for amp-less high-precision sensor application. In order to solve the trade-off between resolution and bandwidth, a time-to-digital converter (TDC) is combined with a resistance-controlled-oscillator. The TDC is used to measure the fractional part of oscillation period, which realize a high resolution and conversion rate with moderate oscillation frequency. Proposed fractional period estimation technique reduce the required number of TDC and save power consumption. A prototype system was developed and 23 ppm resolution of resistance change at conversion rate of 5kSps was experimentally demonstrated.

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Interface with Opamp output-impedance calibration technique for a large integrated 2-D resistive sensor array

Shiiki Y., Ishikuro H.

Proceedings - IEEE International Symposium on Circuits and Systems （Proceedings - IEEE International Symposium on Circuits and Systems）  2019-May 2019年

ISSN  9781728103976

　概要を見る

© 2019 IEEE In this paper, a noble gas sensing system using a large scale integrated resistive sensor array and its interface system is introduced. Accuracy improvement, compared to conventional techniques, was achieved using our proposed opamp output impedance calibration technique. This technique makes it possible to use a low power, weak drivability opamp in the interface circuit. This paper shows the calibration method which reduces the sneak path current error from 83.6% to 1.2% through MATLAB simulations. A prototype system with 1,024 gas sensors integrated in one chip, discrete ICs of opamp, ADCs, and an FPGA was developed, and the effectiveness of the system is demonstrated.

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Arbitrary Magnetic Field Control Technique by Multi-Coil Transmitter Voltage Phase Shifting for Omni-Directional Free-Positioning Magnetic Resonance Wireless Power Delivery

Inada Y., Kawajiri T., Takeda U., Ishikuro H.

2018 48th European Microwave Conference, EuMC 2018 （2018 48th European Microwave Conference, EuMC 2018）     186 - 189 2018年11月

ISSN  9782874870514

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© 2018 European Microwave Association. This paper presents a technique to efficiently transfer power to devices regardless of their angle and position by using multi-coil transmitter with magnetic resonance coupling. The magnetic field at receiver coil can be arbitrary controlled by changing the phase of transmitter switching signal. The optimum phase can be determined by reversely transmitting signal from receiver to transmitter and detecting the phase of induced voltage of each transmitter coil. The effectiveness of proposed technique is demonstrated by electro-magnetic field simulation and measurements.

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Dual Transmitter Free-Positioning wireless Power Transfer System with Optimum Switching Phase Detection Technique

Takeda U., Inada Y., Kimoto Y., Kawajiri T., Ishikuro H.

IEEE MTT-S International Microwave Symposium Digest （IEEE MTT-S International Microwave Symposium Digest）  2018-June   1261 - 1264 2018年08月

ISSN  9781538650677

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© 2018 IEEE. A multi-transmitter wireless power transfer system with magnetic resonance coupling at 6.78MHz is presented. The switching phase of transmitter is controlled by a reverse signal transfer and optimum phase decision technique. The experimental results demonstrate the tracking ability of receiver coil angle change.

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Measurement time reduction technique for input referred noise of dynamic comparator

Ishijima Y., Nakagawa S., Ishikuro H.

IEEE International Conference on Microelectronic Test Structures （IEEE International Conference on Microelectronic Test Structures）  2018-March   202 - 205 2018年06月

ISSN  9781538650691

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© 2018 IEEE. Time reduction technique for the measurement of input referred noise of dynamic comparator is presented. By using binary search technique, the proposed method can reduce the measurement time of comparator input referred noise to (log2n)/n, where n is a required resolution. Experimental results obtained by the developed measurement system shows good correspondence with the simulated input referred noise.

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Design of resource sharing reconfigurable ΔΣ SAR-ADC

Ishizuka M., Yamada K., Ishikuro H.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC （Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC）  2018-January   317 - 318 2018年02月

ISSN  9781509006021

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© 2018 IEEE. This paper presents an ADC with re-configurability between SAR-only mode and delta-sigma (ΔΣ assisted mode). The ΔΣ assisted mode brings resolution enhancement. Proposed ADC shares a capacitor array for SAR, feedback DAC, and integrator capacitor in ΔΣ loop, which can reduce the circuit size. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at 32 MS/s and power consumption of 0.55 mW. The SNDR is improved to 62.9 dB by ΔΣ assisted mode.

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A 13.56-MHz Wireless Power Transfer System With Enhanced Load-Transient Response and Efficiency by Fully Integrated Wireless Constant-Idle-Time Control for Biomedical Implants

Huang C., Kawajiri T., Ishikuro H.

IEEE Journal of Solid-State Circuits （IEEE Journal of Solid-State Circuits）  53 （ 2 ） 538 - 551 2018年02月

ISSN  00189200

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© 2017 IEEE. In this paper, a complete wireless power transfer system with transmitter (TX) and receiver (RX) chips is presented. Both RX local and TX wireless output voltage regulations are achieved by the proposed constant-idle-time control without using any wires or additional discrete components, such as MCU, DAC, various kinds of controllers, and decoders, which were required in previous works. The system and circuitry design complexity is significantly reduced. Both TX and RX chips are fabricated in the TSMC 65-nm process with standard 2.5-V I/O devices, and the RX coil is fabricated using flexible printed circuits to demonstrate the performance for implantable applications. Up to 17.5% end-to-end total efficiency improvement is observed when enabling the wireless constant-idle-time controlled TX voltage regulation, and an instant load-transient response is also achieved. As a result, compared to previous works, this design achieves a higher total efficiency, a faster load-transient response, and a higher level of integration with a much lower system and circuitry design complexity.

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Open loop dynamic transmitter voltage scaling for fast response and wide load range power efficient WPT system

Kawajiri T., Ishikuro H.

IEEE MTT-S International Microwave Symposium Digest    315 - 317 2017年10月

ISSN  0149645X

　概要を見る

This paper presents a fast response wireless power delivery system with open loop dynamic transmitter voltage scaling technique to keep power efficiency in wide load range. In this technique, according to change of receiver side power consumption, the driving voltage of the transmitter (TX) coil is properly adjusted to control transmission power. The transmitting power and switching loss can be reduced in proportion to the square of the driving voltage. Therefore, it can improve power efficiency. To enhance power control speed, the driving voltage is not locally regulated but automatically determined by the feedback loop of the total WPT system. Fabricated test chips in 180-nm LDMOS process achieved maximum power efficiency of 50.9% when the output power is 0.5W. The output power ranges from 0.03W to 0.5W. The output voltage ripple is kept within 3.5% even when the output power is abruptly changed by one order of magnitude.

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Distortion and its suppression in low-power delta-sigma modulator

Ishikuro H.

Midwest Symposium on Circuits and Systems 2017-August   452 - 455 2017年09月

ISSN  15483746

　概要を見る

In this paper, effects of amplifier distortion in DT sigma-delta modulator are discussed. A second order modulator with single-bit quantizer is modeled and dead-zone effect of ring amplifiers in integrators is simulated by using MATLAB. For the evaluation of dead-zone effect on modulator distortion, test chip was fabricated in 65nm CMOS. SNDR of 62dB and 1MHz signal bandwidth was experimentally demonstrated at sampling frequency of 102.4MHz and power consumption of 1mW.

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A simplified path interference model in 2D multi-hop wireless power transfer system

Shibuya R., Kawajiri T., Ishikuro H.

ISAP 2016 - International Symposium on Antennas and Propagation    54 - 55 2017年01月

　概要を見る

This paper studies the multipath interference in a 2D multi-hop wireless power transfer system which uses magnetic resonance in two dimensional repeater array. By focusing on the current amplitude and phase in each repeaters, power combination from different path is discussed and simplified path interference model is proposed. The accuracy of the proposed simplified path interference model is compared with electromagnetic field simulation.

A Programmable δΣSAR-ADC with charge shuttling technique

Yamada K., Toyama Y., Ishikuro H.

ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things    51 - 52 2016年12月

　概要を見る

This paper presents an ADC with programmability between SAR-only mode and delta-sigma (δΣassisted mode. The ?assisted mode brings 1st order noise shaping for resolution enhancement. Proposed charge shuttling technique makes it possible to share a charge re-distribution capacitor array for DAC in SAR, feedback DAC, and integrator capacitor in δΣloop and improve the accuracy. The prototype ADC fabricated in 65- nm CMOS achieved SNDR of 44.35 dB at sampling rate of 32 MHz and power consumption of 0.55mW. The SNDR is improved to 62.9dB by δΣassisted mode when the signal bandwidth is 60 kHz.

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A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique

Gryta A., Suguro T., Ishikuro H.

2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016    275 - 278 2016年12月

　概要を見る

This paper presents a ΔΣ modulator with ring amplifiers to decrease the power consumption. The proposed ΔΣ modulator employs a technique of cutting-off the current of ring amplifiers after they are settled in each clock cycle. The optimum cutting-off timing can be determined by monitoring the output SNDR. The proposed 1-bit third-order ΔΣ modulator was designed in 65-nm CMOS process. From schematic-level circuit simulation, 76-dB SNDR was obtained at signal bandwidth of 1 MHz and clock frequency of 128 MHz. More than 40% percent of the power is saved at clock frequency of 128 MHz and power scalability is obtained.

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A 24 mW 5.7 Gbps dual frequency conversion demodulator for impulse radio with the first sidelobe

Kohira K., Kitazawa N., Ishikuro H.

IEICE Transactions on Electronics E99C （ 10 ） 1164 - 1173 2016年10月

ISSN  09168524

　概要を見る

This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.

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A wireless power transfer system with enhanced response and efficiency by fully-integrated fast-tracking wireless constant-idle-time control for implants

Huang C., Kawajiri T., Ishikuro H.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2016-September 2016年09月

　概要を見る

In this paper, a 13.56 MHz fully-integrated wireless power transfer system with wireless constant-idle-time control is proposed. The massive off-chip components or wire required for transmitter (TX) voltage regulation in previous works are eliminated. Both wireless and local regulations are achieved with enhanced transient performance and total efficiency, and reduced circuitry and system design complexity. Thanks to the proposed wireless constant-idle-time control technique, an instant load-transient response, and a peak total efficiency of 67.6% with up to 13.7% improvement are observed in measurements with meat between coils at a distance of 6mm.

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A Near-Optimum 13.56 MHz CMOS Active Rectifier with Circuit-Delay Real-Time Calibrations for High-Current Biomedical Implants

Huang C., Kawajiri T., Ishikuro H.

IEEE Journal of Solid-State Circuits 51 （ 8 ） 1797 - 1809 2016年08月

ISSN  00189200

　概要を見る

In this paper, a near-optimum active rectifier is proposed to achieve well-optimized power conversion efficiency (PCE) and voltage conversion ratio (VCR) under various process, voltage, temperature (PVT) and loading conditions. The near-optimum operation includes: eliminated reverse current loss and maximized conduction time achieved by the proposed sampling-based real-time calibrations with automatic circuit-delay compensation for both on- and off-time of active diodes considering PVT variations; and power stage optimizations with adaptive sizing over a wide loading range. The design is fabricated in TSMC 65 nm process with standard I/O devices. Measurement results show more than 36% and 17% improvement in PCE and VCR, respectively, by the proposed techniques. A peak PCE of 94.8% with an 80Ω loading, a peak VCR of 98.7% with 1 kΩ loading, and a maximum output power of 248.1 mW are achieved with 2.5 V input amplitude.

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Low power DT delta-sigma modulator with ring amplifier SC-integrator

Suguro T., Ishikuro H.

Proceedings - IEEE International Symposium on Circuits and Systems 2016-July   2006 - 2009 2016年07月

ISSN  02714310

　概要を見る

This paper presents a low power DT sigma-delta modulator for wide variety of sensor application using a ring amplifier for SC-integrator. The topology is a second order modulator with single-bit quantizer. Dead-zone effect of the ring amplifier in oversampling ADC is discussed. The fabricated test chip in 65nm CMOS process achieved SNDR of 62dB and 1MHz signal band at sampling frequency of 102.4MHz. The power consumption is 1mW and FoM is 483fJ/conv.step.

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Dynamic period switching of PRS-PWM with run-length limiting technique for spurious and ripple reduction in fast response wireless power transmission

Moroto T., Kawajiri T., Ishikuro H.

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC 2016-May   1802 - 1806 2016年05月

　概要を見る

In this paper, we propose a control method in a wireless power transmission that targets small battery-less devices. Dynamic period switching of PRS-PWM (Pseudo Random Sequence - Pulse Width Modulation) with run length limiting technique has been developed to break through the tradeoff between transient response speed, rectified voltage ripple, and spurious emission. Developed wireless power transmission system has achieved ripple reduction by 44%, response speed of 70μs, and spurious reduction by 15.6dB.

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A 12.5 Gbps CDR with differential to common converting edge detector for the wired and wireless serial link

Kohira K., Ishikuro H.

IEICE Transactions on Electronics E99C （ 4 ） 458 - 465 2016年04月

ISSN  09168524

　概要を見る

This paper introduces low-power and small area injectionlocking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2-V supply at 12.5 Gbps. The fabricated CDR achieved a BER lower than 10-12 and the recovered clock had an rms jitter of 0.87 ps. The CDR area is 0.165 mm2.

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An Inductively Powered Wireless Solid-State Drive System with Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories

Kosuge A., Hashiba J., Kawajiri T., Hasegawa S., Shidei T., Ishikuro H., Kuroda T., Takeuchi K.

IEEE Journal of Solid-State Circuits 51 （ 4 ） 1041 - 1050 2016年04月

ISSN  00189200

　概要を見る

A highly reliable wireless solid-state drive (SSD) system for future applications of large volume storage is presented. The wireless interface in the system consists of an inductively coupled power link with fast transmission power control and high-speed data links using transmission line couplers (TLCs). The wireless power link can deliver 1 W from the host to the SSD. The full duplex wireless data interface achieves raw data rate of 1.6 Gb/s. The reliability of the wireless interface is studied though simulation analysis and experiments. The error correction block for the NAND flash memory system can also correct errors in the wireless data links, allowing the requirements for the PHY layer to be relaxed. The error correction code is discussed, including optimization by analyzing the error bits on the wireless data links. The experimental results confirmed strong tolerance to the interference from the power link on the wireless data link, and the water proof property of both the data and power links.

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A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe

Kohira K., Kitazawa N., Ishikuro H.

IEEE Radio and Wireless Symposium, RWS 2016-March   10 - 12 2016年03月

ISSN  21642958

　概要を見る

This paper presents a modulation scheme of impulse radio which uses 1st sidelobe of transmitting NRZ baseband signal and implementation of dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that of BPSK modulation and does not require up-converter in the transmitter. The dual frequency conversion demodulator compensates the spectrum distortion caused by frequency response of circuits and channel. The fabricated demodulator test chip in 65nm CMOS achieved clock and data recovery at 5.5Gbps with power consumption of 24mW.

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A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver

Kosuge A., Okada A., Taguchi M., Ishikuro H., Kuroda T.

IEEE Transactions on Circuits and Systems I: Regular Papers 63 （ 2 ） 265 - 275 2016年02月

ISSN  15498328

　概要を見る

A 280 Mb/s non-contact in-vehicle LAN system using electromagnetic clip connectors is presented. The bidirectional transmission line coupler based electromagnetic clip connector, which can be used to make local area network connections similar to clips, suppresses the signal reflections on the bus enabling 280 Mb/s data rate which is 7 times faster than the state-of-the-art in-vehicle LAN transceiver. Since all modules are connected with the shortest distance, this connection system can reduce wire harness weight by 30%. Forward error correction is done by N-x Manchester encoding on the transmitter side and majority voting on the receiver side. High noise immunity is achieved through synchronous receiving by the digital clock recovery circuit which is robust against noise. Communication tests were conducted at 280 Mb/s with 10 transceivers fabricated in 65 nm CMOS technology connected by a 10 m unshielded twisted pair cable. Evaluation of the bit error rate and radiation spectrum confirmed that the ISO specifications concerning electromagnetic susceptibility and the CISPR ones concerning electromagnetic interference are satisfied.

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Shield effects of metal plate and mesh in wireless power delivery system

Hashiba J., Kawajiri T., Shibuya R., Ishikuro H.

2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings    235 - 237 2016年01月

　概要を見る

This paper presents the influence of metal sheet near the coils of inductively coupled wireless power delivery system. Experiments and electro-magnetic field simulation shows the influence of various kind of metal sheets and sheet positions on the power efficiency and peak frequency shift. The tradeoff between the power efficiency and shielding ability is also discussed.

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Wave monitor for glitch detection and skew adjusting in high-speed DAC

Tokonami K., Kohira K., Ishikuro H.

2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings    175 - 177 2016年01月

　概要を見る

In this paper, a high-speed current steering DAC with wave monitor circuit is proposed. Comparatorbased wave monitor circuit makes it possible to detect a glitch and adjust the skew of each bit digital signal. Fabricated test chip in 40nm-CMOS demonstrates the performance improvement by glitch detection and skew adjusting. At 1GS/sec, the fabricated DAC achieved ENOB of 5.17 bit and power consumption of 2.38mW.

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A Prototype SAW-Less LTE Transmitter with a High-Linearity Modulator Using BPF-Based I/Q Summing and a Triple-Layer Marchand Balun

Nakamura T., Kitazawa N., Kohira K., Ishikuro H.

IEEE Transactions on Microwave Theory and Techniques 63 （ 12 ） 4090 - 4097 2015年12月

ISSN  00189480

　概要を見る

A 65-nm CMOS-technology-based surface-acoustic-wave filterless transmitter (TX) for a long-term evolution (LTE) system was developed and performance tested. The TX incorporates both a passive quadrature modulator (QMOD) using bandpass filter (BPF)-based in-phase/quadrature (I/Q) signal summing and a small triple-layer Marchand balun. The passive operation and BPF-based I/Q summing, respectively, contribute to low noise performance and high input impedance (seen from the baseband signal), resulting in low receiver (RX) band noise and high linearity of the TX. The triple-layer Marchand balun contributes to the small area of the TX. A prototype LTE TX using the QMOD and the balun exhibits in-specification RX-band noise (<-161.6 dBc/Hz), a high output third-order intercept point (OIP3=20.5 dBm), and a small chip area (0.224 mm2).

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A near-optimum 13.56 MHz active rectifier with circuit-delay real-time calibrations for high-current biomedical implants

Huang C., Kawajiri T., Ishikuro H.

Proceedings of the Custom Integrated Circuits Conference 2015-November 2015年11月

ISSN  08865930

　概要を見る

This paper presents a 13.56MHz active rectifier with enhanced power conversion efficiency (PCE) and voltage conversion ratio (VCR) for high-current biomedical implants. Near-optimum operation with compensated circuit delays is achieved by the proposed real-time NMOS on/off calibrations, which minimize the reverse current and maximize the transistor conduction time under various process, voltage, temperature and loading conditions. Adaptive sizing (AS) is also introduced to optimize the PCE over a wide loading range. Measurements in TSMC 65nm show more than 36% and 17% improvement in PCE and VCR, respectively, by the proposed techniques. With 2.5V input amplitude, the rectifier achieves a peak PCE of 94.8% with an 80Ω loading, a peak VCR of 98.7% with a 1kΩ loading, and a maximum output power of 248.1mW.

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A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration

Tanaka K., Saito R., Ishikuro H.

European Solid-State Circuits Conference 2015-October   327 - 330 2015年10月

ISSN  19308833

　概要を見る

A 6-bit high-speed and low-power pipelined binary-search ADC is presented. Over GHz conversion rate is achieved by passive pipeline operation without amplifier. 'Memory effect' caused by charge sharing in the passive pipeline operation is cancelled by charge reset and flatness of frequency response of the converter is improved. Memory effect canceller also makes it easy to calibrate reference voltage to each comparator and to enhance SNDR. The prototype ADC fabricated in 40nm-CMOS achieved 29.21 dB SNDR with 1.6 GS/s at supply voltage of 0.9 V. The ADC achieved a FoM of 84.1 fJ/conv.step.

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A low EMI SIDO wireless power transfer system with 10μsec response time

Kawajiri T., Moroto T., Ishikuro H.

European Solid-State Circuits Conference 2015-October   253 - 256 2015年10月

ISSN  19308833

　概要を見る

This paper describes a system of single-inductor-dual-output (SIDO) wireless power delivery for mobile applications. By updating control signal in the feedback loop by every switching clock cycle, fast tracking to the load change is realized while spurious emission is suppressed by using pseudorandom-sequence PWM (PRS-PWM). Transmitter and receiver chips were fabricated in 0.18μm CMOS process and mounted on the wireless power transfer test board. The system achieved response time shorter than 10μsec. Two output voltages are regulated at 8V and 16V, and maximum efficiency of 41% was achieved when the total output power is 500mW.

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I/Q mismatch compensation ΔΣ modulator using ternary capacitor rotation technique

Yonekura M., Ishikuro H.

European Solid-State Circuits Conference 2015-October   229 - 232 2015年10月

ISSN  19308833

　概要を見る

This paper presents a new technique to suppress I/Q mismatch and decrease power consumption and chip area. The proposed technique uses two methods for all integrators and DAC in the modulator which are main sources of the mismatch and power. One is proposed ternary capacitor rotation technique to compensate the I/Q mismatch and achieve high image-rejection. The other is amplifier-sharing technique to reduce the number of amplifier and power consumption. The third-order 1bit delta-sigma modulator was designed in 65nm CMOS process, and fabricated test chip achieved an image-rejection ratio (IRR) of higher than 70dB throughout a 1MHz bandwidth. The overall power consumption is 12.7mW including I/Q channels.

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Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory

Kosuge A., Hashiba J., Kawajiri T., Hasegawa S., Shidei T., Ishikuro H., Kuroda T., Takeuchi K.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2015-August   C128 - C129 2015年08月

　概要を見る

This paper presents a wireless solid-state drive (SSD) system for future applications of large volume storage in mobile devices or data centers. The wireless interface in the developed system consists of an inductive-coupling power link with a fast transmitting power control and high-speed data links with transmission line couplers (TLCs). The wireless power link can deliver 1W from the host side to the SSD side. The full duplex wireless data interface achieved raw data rate of 1.6Gbps/link. The error correction block for NAND flash memory system can also correct the error in wireless data links. The data link has tolerance to the interference from the power link, and both the data and power links show the waterproof property of the system.

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Analysis and design of an 8.5-Gb/s/Link multi-drop bus using energy-equipartitioned transmission line couplers

Kosuge A., Ishizuka S., Taguchi M., Ishikuro H., Kuroda T.

IEEE Transactions on Circuits and Systems I: Regular Papers 62 （ 8 ） 2122 - 2131 2015年08月

ISSN  15498328

　概要を見る

An 8.5-Gb/s/link non-contact multi-drop bus is presented. The signal reflections that limit the data rates of conventional multi-drop bus interfaces are dramatically reduced by using transmission line couplers at each signal branching point. As an energy-equipartitioned technique provides the same signal level to every port, wider receiver margin is achieved. The data rate is improved by 1.8 times compared to the most advanced multi-drop bus interface. The theoretical analysis and design techniques of energy-equipartitioned transmission line couplers are discussed in this paper. The design methodologies were verified through simulations performed by using a full-3D EM-simulator and experiments with FR4 test boards. Due to the low-cut characteristics of the couplers, the low-frequency components are cut off so that differentiated pulses arrive at the receiver input point. A receiver detects and recovers the received pulses by integrating them using hysteresis characteristics. The design techniques of the transceiver for the transmission line couplers are also discussed in this paper. The proposed methods were verified by using a test chip fabricated with a 90-nm CMOS process. Experiments with a prototype of an eight-drop multi-drop bus system confirmed BER < 10-14 at a data rate of 8.5-Gb/s/link. The measured timing margin at the far-end module was 0.49-UI at a BER of 10-12. The power consumption of the transceiver was 75.6-mW at a supply voltage of 1.2-V.

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Fence loaded antenna coupler for high-band UWB with steep cutoff characteristics

Saito I., Kohira K., Ishikuro H.

IEEE Radio and Wireless Symposium, RWS 2015-June （ June ） 56 - 58 2015年06月

ISSN  21642958

　概要を見る

This paper presents a fence-type virtual short stub loaded UWB antenna coupler which has broadband and steep cutoff characteristics at both the lower and upper cutoff frequency. The fence-type short stub consists of a top and bottom metal layers of FR4 substrate and Through Holes (THs) connecting layers. Thanks to this geometry, resonance and anti-resonance occur at various frequencies in several signal paths. The size of the antenna is 1cm × 1cm. The simulation result of coupling coefficient parameter (S21) is higher than -20dB from 6.2GHz to 10.4GHz (4.2GHz bandwidth) when the distance between two couplers is 1cm.

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Intermittently operating RF frontend with 5ns startup time for 10Gbps proximity wireless communication

Kitazawa N., Kohira K., Ishikuro H.

2015 IEEE 15th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2015    24 - 26 2015年06月

　概要を見る

This paper presents intermittently operating RF frontend for proximity wireless communication with wireless power supply. To realize power scalability of the RF frontend, intermittent operation is performed by switching the bias of the amplifier. Quick startup circuit is proposed to accelerate the charging time to a decoupling capacitor. The fabricated test chip in 65nm CMOS occupies 0.075mm2. The 3dB bandwidth of amplifier ranges from 1.8GHz to 7.2GHz and current consumption is 8mA. The startup time of the circuit is 5ns.

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Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC

Yoshioka K., Saito R., Danjo T., Tsukamoto S., Ishikuro H.

IEEE Journal of Solid-State Circuits 50 （ 4 ） 932 - 945 2015年04月

ISSN  00189200

　概要を見る

Dynamic Architecture and Frequency Scaling (DAFS) is shown to realize superlinear power scaling in high-speed analog-to-digital converters (ADCs). To achieve both high-speed operation and low power consumption, the ADC architecture is reconfigured between binary search and flash every clock cycle, relying on the conversion delay. The proposed binary search/flash architecture reconfigurable ADC can be implemented with only a small modification to conventional binary search ADCs. By live configuring, the flash operation is adaptively performed when an excess delay is detected. DAFS not only significantly improves the power scaling but also compensates for transistor speed shifts due to process, voltage and temperature (PVT) variations. Therefore, DAFS can be used to improve the design margin of high-speed ADCs. A prototype subranging ADC fabricated in 65 nm CMOS technology operates up to 1220 MS/s and achieves an SNDR of 36.2 dB with a Nyquist input frequency. DAFS is active between 820-1220 MS/s and achieves peak power reduction of 30%, when compared with the power scaling when DAFS is disabled. A peak FoM of 85 fJ/conv. was obtained at 820 MS/s, which is nearly a twofold improvement over that of previously reported subranging ADCs.

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Dual-output wireless power delivery system for small size large volume wireless memory card

Hashiba J., Kawajiri T., Hasegawa Y., Ishikuro H.

20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015    32 - 33 2015年03月

　概要を見る

A single-inductor dual-output wireless power delivery system for small size battery-less NAND flash memory card is presented. The power delivery system uses two rectifiers connected to a single inductor which is synchronously switched by pseudo-random-sequence PWM signal with induced AC voltage. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 % and maximum total transmitting power of 0.5 W. The test chips were designed and fabricated using 0.18um-CMOS with high-voltage LDMOS option.

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An 8 bit 0.3-0.8 v 0.2-40 MS/s 2-bit/Step SAR ADC with successively activated threshold configuring comparators in 40 nm CMOS

Yoshioka K., Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 （ 2 ） 356 - 368 2015年02月

ISSN  10638210

　概要を見る

A 0.3-0.8 V low-power 2-bit/step asynchronous successive approximation register analog-to-digital converter (ADC) is presented. A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. Simple digital calibration is enabled by generating the reference internally. The prototype ADC fabricated in a 40 nm CMOS achieved a 44.3 dB signal-to-noise-plus-distortion ratio (SNDR) with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 4.8 fJ/conv-step at 0.4 V and operates down to 0.3 V.

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A 13b SAR ADC with eye-opening VCO based comparator

Yoshioka K., Ishikuro H.

European Solid-State Circuits Conference    411 - 414 2014年10月

ISSN  19308833

　概要を見る

A low-power and high accuracy comparator based on voltage controlled ring-oscillator (VCO) is presented. By using the dead zone of phase detector effectively, the VCO comparator automatically changes its noise level depending on the input voltage level (Δvin). When Δvin is large, the comparator operates as a low-power delay-line based comparator. On the other hand, when Δvin is small, the VCO is enabled and eye is opened during the oscillation. This suppress input referred noise and enables accurate conversion. The number of oscillation cycle for one comparison is inversely proportional to Δvin and adaptive noise reduction is realized. The VCO comparator does not require any sort of tuning. A 13b SAR ADC with proposed VCO based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves SNDR 66 dB at 1 MS/s with FoM of 29fJ/conv.-step.

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A SAW-less LTE transmitter with high-linearity modulator using BPF-based I/Q summing

Nakamura T., Kitazawa N., Kohira K., Ishikuro H.

European Solid-State Circuits Conference    387 - 390 2014年10月

ISSN  19308833

　概要を見る

A SAW-filter-less LTE transmitter based on 65-nm CMOS technology, incorporating a passive quadrature modulator (QMOD) with band-pass-filter (BPF) I/Q summing technique, was developed. The passive operation and the BPF I/Q summing technique, respectively, contribute to low noise performance and high input impedance seen from baseband signal, resulting in low receiver-band noise and high linearity of the transmitter. A transmitter using the QMOD exhibits both inspecification receiver-band noise (<-156 dBc/Hz) and high output 3rd intercept point (OIP3 = 20.6 dBm).

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An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique

Yoshioka K., Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC    31 - 32 2014年03月

　概要を見る

An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC. © 2014 IEEE.

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A 0.15-mm-thick noncontact connector for mipi using a vertical directional coupler

Kosuge A., Mizuhara W., Shidei T., Takeya T., Miura N., Taguchi M., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 49 （ 1 ） 223 - 231 2014年01月

ISSN  00189200

　概要を見る

A noncontact and housing-less thin-thick connecting method was developed for mobile industry processor interface (MIPI) applications. This paper describes the world's first 0.15-mm-thick connector using a vertical directional coupler (VDC) which enables simultaneous two-link communication with one coupler without fatal performance degradation. We have analyzed the conditions for isolating two links in a coupler, and the design method is discussed. A fully balanced pulse transmitter implemented in 90-nm CMOS technology significantly suppressed electromagnetic interference (EMI), which agrees well with MIPI requirements. An experimental liquid crystal display interface system reached a maximum data rate of 2.3 Gb/s/link at a bit error rate of less than 10-12 and a power consumption of 1.47~pJ/b. The timing margin of single link was 320 ps (=64% U.I.) and of two links was 305 ps (= 61% U.I.) at 2.0 Gb/s. © 2013 IEEE.

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7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Yoshioka K., Saito R., Danjo T., Tsukamoto S., Ishikuro H.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2014年

　概要を見る

Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs. © 2014 IEEE.

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An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%

Kosuge A., Ishizuka S., Liu L., Okada A., Taguchi M., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 57   496 - 497 2014年

ISSN  01936530

　概要を見る

Heavier wire harnesses decrease the fuel efficiency of vehicles. The number of wires has increased sharply with presently over one hundred electronic control units (ECUs). Connectors also add to the weight (Fig. 30.6.1(a)). The connectors used in vehicles occupy a considerable space because heavy protection is required against transmission interruption caused by vibration. In addition, a significant number of wires are used together in a junction box to increase total wire length (e.g. 55L when 10 ECUs are connected) and thus weight increases accordingly. © 2014 IEEE.

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A low power, area efficient frequency acquisition circuit with array oscillator for pulse-based inductive-coupling transceiver

Jyo T., Kuroda T., Ishikuro H.

Asia-Pacific Microwave Conference Proceedings, APMC    95 - 97 2013年12月

　概要を見る

This paper presents a low power, small area Frequency Acquisition Circuit (FAC) for a pulse-based inductive coupling transceiver. A multiphase clock which is generated in array oscillator is used to control the pulse width. To solve the problem of oscillation frequency change by PVT variation, FAC is proposed to control the oscillation frequency. FAC uses the multiphase clock generated in array oscillator. By sharing the multiphase clock for both the pulse generation and the frequency control, low power and small area can be achieved. The fabricated test chip in 65nm CMOS occupies 0.045mm2. The array oscillator generates 1GHz, 20 phase clocks at the supply voltage of 0.8V. The RMS of cycle-to-cycle jitter is 3.3ps and the power consumption is 1.1mW. © 2013 IEEE.

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Single-inductor-dual-output wireless power receiver with synchronous pseudo-random-sequence PWM switched rectifiers

Hasegawa Y., Tomita K., Ishihara S., Honma R., Ishikuro H.

Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013    261 - 264 2013年12月

　概要を見る

A single-inductor dual-output wireless power delivery receiver for small size battery-less applications is presented. The power delivery system uses two rectifiers connected to a receiving inductor switched by pseudo-random-sequence PWM (PRS-PWM) signal synchronized with induced AC voltage in the receiving inductor. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 %. The maximum total transmitting power is 0.5 W. The test chip was designed and fabricated using 0.18um-CMOS with high-voltage (32V) LDMOS option. © 2013 IEEE.

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0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Nomura M., Muramatsu A., Takeno H., Hattori S., Ogawa D., Nasu M., Hirairi K., Kumashiro S., Moriwaki S., Yamamoto Y., Miyano S., Hiraku Y., Hayashi I., Yoshioka K., Shikata A., Ishikuro H., Ahn M., Okuma Y., Zhang X., Ryu Y., Ishida K., Takamiya M., Kuroda T., Shinohara H., Sakurai T.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2013年09月

　概要を見る

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%. © 2013 JSAP.

A 0.0058mm² 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique

Yoshioka K., Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2013年09月

　概要を見る

An extremely low power and area efficient threshold configuring ADC (TC-ADC) is proposed. The threshold configuring comparator (TCC) performs a binary search and only 1b-DAC is required. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC. © 2013 JSAP.

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Nomura M., Muramatsu A., Takeno H., Hattori S., Ogawa D., Nasu M., Hirairi K., Kumashiro S., Moriwaki S., Yamamoto Y., Miyano S., Hiraku Y., Hayashi I., Yoshioka K., Shikata A., Ishikuro H., Ahn M., Okuma Y., Zhang X., Ryu Y., Ishida K., Takamiya M., Kuroda T., Shinohara H., Sakurai T.

Digest of Technical Papers - Symposium on VLSI Technology 2013年09月

ISSN  07431562

　概要を見る

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%. © 2013 JSAP.

A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL

Urano Y., Yun W., Kuroda T., Ishikuro H.

Proceedings - IEEE International Symposium on Circuits and Systems    1576 - 1579 2013年09月

ISSN  02714310

　概要を見る

This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2. © 2013 IEEE.

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A 0.7V intermittently operating LNA with optimal on-time controller for pulse-based inductive-coupling transceiver

Jyo T., Kuroda T., Ishikuro H.

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium    21 - 24 2013年09月

ISSN  15292517

　概要を見る

This paper presents a low-power LNA for a inductive-coupling tranceiver. Intermittently operating technique to turn on LNA only at the moment when the pulse signal appears is used to reduce power consumption. To optimally control the On-time of LNA, pulse width detector based on self-oversampling TDC is used and compensate the PVT variations of On-time witdh and of pulse signal width. The fabricated test chip in 65nm CMOS occupies 0.06mm2 and achieved the intermittently operating frequency at the range from 60 to 400Mbps. The power consumption is 0.42mW at 400Mbps and the supply voltage of 0.7V which corresponds to 37% power reduction from the power consumption without optimal On-Time Controller. © 2013 IEEE.

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A voltage scaling 0.25-1.8 v delta-sigma modulator with inverter-opamp self-configuring amplifier

Yoshioka K., Toyama Y., Jyo T., Ishikuro H.

Proceedings - IEEE International Symposium on Circuits and Systems    809 - 812 2013年09月

ISSN  02714310

　概要を見る

A 2nd order discrete time (DT) ΔΣ modulator with very wide supply voltage range of 0.25-1.8 V is presented. An inverter-opamp self-configuring amplifier (IOSA) is proposed with sufficient gain through sub-threshold to strong inversion region. The amplifier senses the supply voltage and automatically configures either to operate as an inverter or an opamp. The prototype ADC fabricated in 180nm CMOS achieved SNDR of 53dB at a supply voltage of 0.3V and a best FoM of 0.09 pJ/step. At 1.8 V supply the modulator achieves SNDR 61dB and operates down to 0.25V. © 2013 IEEE.

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A 0.5-v 5.2-fj/conversion-step full asynchronous sar adc with leakage power reduction down to 650 pw by boosted self-power gating in 40-nm CMOS

Sekimoto R., Shikata A., Yoshioka K., Kuroda T., Ishikuro H.

IEEE Journal of Solid-State Circuits 48 （ 11 ） 2628 - 2636 2013年08月

ISSN  00189200

　概要を見る

This paper presents an ultralow-power and ultralow-voltage SAR ADC. Full asynchronous operation and boosted self-power gating are proposed to improve conversion accuracy and reduce static leakage power. By designing with MOSFET of high threshold voltage (rm HVt) and low threshold voltage (rm LVt), the leakage power is reduced without decrease of maximum sampling frequency. The test chip in 40-nm CMOS process has successfully reduced leakage power by 98%, and it achieves 8.2-bit ENOB and while consuming only 650 pW at 0.1 kS/s from 0.5-V power supply. The power consumption is scalable up to 4 MS/s and power supply range from 0.4 to 0.7 V. The best figure of merit at 0.5 V is 5.2 fJ/conversion-step at 20 kS/s. © 2013 IEEE.

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An adaptive DAC settling waiting time optimized ultra low voltage asynchronous SAR ADC in 40 nm CMOS

Sekimoto R., Shikata A., Yoshioka K., Kuroda T., Ishikuro H.

IEICE Transactions on Electronics E96-C （ 6 ） 820 - 827 2013年06月

ISSN  09168524

　概要を見る

An ultra low power and low voltage successive-approximation-register (SAR) analog-to-digital converter (ADC) with timing optimized asynchronous clock generator is presented. By calibrating the delay amount of the clock generator, the DAC settling waiting time is adaptively optimized to counter the device mismatch. This technique improved the maximum sampling frequency by 40% keeping ENOB around 7-bit at 0.4 V analog and 0.7 V digital power supply voltage. The delay time dependency on power supply has small effect to the accuracy of conversion. Decreasing of supply voltage by 9% degrades ENOB only by 0.1-bit, and the proposed calibration can give delay margins for high voltage swing. The prototype ADC fabricated in 40 nm CMOS process achieved figure of merit (FoM) of 8.75-fJ/conversion-step with 2.048 MS/s at 0.6 V analog and 0.7 V digital power supply voltage. The ADC can operates from 50 S/s to 8 MS/s keeping ENOB over 7.5-bit. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

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A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC

Yoshioka K., Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC    111 - 112 2013年05月

　概要を見る

An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V. © 2013 IEEE.

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A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and dicode partial-response channel transceivers

Kosuge A., Mizuhara W., Miura N., Taguchi M., Ishikuro H., Kuroda T.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC    91 - 92 2013年05月

　概要を見る

A reduced-reflection multi-drop bus system using Dicode (1-D) partial response signaling transceiver is presented for the first time in the world. Directional couplers on transmission lines arranged with equi-energy distributing and exact impedance matched conditions allow the bus to reach to 12.5Gbps/link speed, which is the world's fastest data link speed with multi-drop bus architecture. Dicode partial-response signaling method with a half-rate architecture was used where a precoder is placed in the transmitter to make the signal best fit for the channel to eliminate inter symbol interference (ISI). © 2013 IEEE.

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A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA

Jyo T., Kuroda T., Ishikuro H.

IEEE Radio and Wireless Symposium, RWS    217 - 219 2013年05月

ISSN  21642958

　概要を見る

This paper presents a small size, low-power inductive-coupling receiver for wireless proximity communication. Area efficient active inductor peaking is used to expand the bandwidth of low voltage LNA. Proposed LNA can operate intermittently, synchronized with received pulse timing and reduces the power consumption at low data rate. Clock is extracted from the received pulse signal by simple combination of imbalanced inverters. The fabricated test chip in 65nm-CMOS occupies 0.035mm2 and achieved 1.6Gbps with power consumption of 1.76mW at 0.8V power supply. © 2013 IEEE.

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A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler

Mizuhara W., Shidei T., Kosuge A., Takeya T., Miura N., Taguchi M., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 56   200 - 201 2013年04月

ISSN  01936530

　概要を見る

As silicon chip performance continues to increase, the interconnection capabilities should also be improved to achieve higher overall system performance. This paper proposes a new, small-size and high-speed non-contact interconnect between printed circuit boards (PCBs) using a vertical directional coupler (VDC), which has actually been applied to a liquid crystal display (LCD) driver board. The feasibility of a millimeter-range non-contact interface using a directional coupler was studied previously [1]. In this paper, two signal ports have been implemented in one coupler by best utilizing the characteristics of VDC. The coupler size is 5mm × 2.25mm, and the gap between the couplers is about 75μm, which corresponds to the twofold thickness of a soldering resist on PCB and the adhesive material in between. The transmitter transforms the data sequence from Non-Return-to-Zero (NRZ) into pulses in order to reduce the level of DC components. This achieves a power saving of 1.47pJ/b, and the pulses are sent to the coupler in differential mode to prevent electromagnetic interference (EMI). The measured speed was 4.6Gb/s per coupler to achieve the MIPI's maximum speed of 6Gb/s with two couplers. Conventional connectors have housings to protect contact elements or to provide mechanical support for plug-in and out. However, these housings make it difficult to achieve the smallest possible systems because they require extra space. In addition, they sometimes make the PCB trace longer, which deteriorates the maximum data rate. The method we have developed involves delineating VDC on PCB or a flexible printed circuit (FPC) to connect boards without housings and with the minimum distance. As a result, this interconnect scheme is advantageous not only because it saves space but also because it makes it easier to build systems, even those that contain a large number of built-in connectors. Thus, the proposed non-contact interconnect is suitable for future small-size systems. © 2013 IEEE.

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3D clock distribution using vertically/horizontally-coupled resonators

Take Y., Miura N., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 56   258 - 259 2013年04月

ISSN  01936530

　概要を見る

Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages. © 2013 IEEE.

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1=f noise characteristics of fin-type field-effect transistors in saturation region

Sakai H., O'uchi S.I., Endo K., Matsukawa T., Liu Y., Ishikawa Y., Tsukada J., Nakagawa T., Sekigawa T., Koike H., Masahara M., Ishikuro H.

Japanese Journal of Applied Physics 52 （ 4 PART 2 ）  2013年04月

ISSN  00214922

　概要を見る

In this work, we measured 1=f noise of independent-double-gate-(IDG-) fin-type FET (FinFET) which has two independent gates. Flicker noise of common-double-gate-(CDG-) mode which both gates are applied with the same voltage and IDG-mode that has one gate voltage grounded and the other gate voltage applied with arbitrary voltage, and both result were compared with the same drain current (Id). First, we measured relationship between characteristic of the normalized 1=f noise by Id (SId =I2 d ) and characteristic of Id. Both the SId =I2 d of IDG-and CDG-modes show nearly equal values and tendency. Next, this work also shows the relationship between 1=f noise and vertical electric field (Ei) of surface of gate oxide film. As a result we could not definitely see a large margin of 1=f noise between CDG-and IDG-modes from Ei. This work also discovered that 1=f noise was greatly influenced by Id density. © 2013 The Japan Society of Applied Physics.

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A 12-Gb/s non-contact interface with coupled transmission lines

Takeya T., Nan L., Nakano S., Miura N., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 48 （ 3 ） 790 - 800 2013年03月

ISSN  00189200

　概要を見る

This paper presents a high data rate, non-contact interface using a coupled transmission line (CTL) composed of two differential transmission lines. The proposed CTL can achieve a measured loss of-13.4 dB and a 3-db bandwidth of 3.4-9.0 GHz as a non-contact channel for a 1-mm communication distance. This wideband characteristic makes it possible to achieve high-speed communication using a single channel. The hysteresis buffer-based receiver recovers the transmitted data from the distorted waveforms derived from the AC coupling characteristics of the channel. The interference from the power delivery coil to the CTL is also evaluated. The simulated results showed that the interference was less than-57.8 dB at 13.56 MHz. The system could achieve a communication speed of 12 Gb/s with a BER < 10-12 at a communication distance of 1 mm both with and without a wireless power supply of 75 mArms. The timing margin with the wireless power supply was 41 ps (=0.49 UI). © 1966-2012 IEEE.

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A 4-10 bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS withWide Supply Voltage Range SAR Controller

Shikata A., Sekimoto R., Yoshioka K., Kuroda T., Ishikuro H.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96-A （ 2 ） 443 - 452 2013年02月

ISSN  09168508

　概要を見る

This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flipflop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4V single power supply voltage. At 10 bit mode and 1V operation, up to 10MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

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An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator

Yoshioka K., Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

European Solid-State Circuits Conference    381 - 384 2012年12月

ISSN  19308833

　概要を見る

An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V. © 2012 IEEE.

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0.6-3.6 GHz wideband operation with high phase resolution on-chip network analyzer

Johari A.H., Ishikuro H.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS    539 - 542 2012年12月

　概要を見る

In this paper, we have shown the design of a wideband operation On-chip Network Analyzer (OCNA) in 45nm CMOS. Its maximum operation ranges from 0.6 ∼ 3.6 GHz with maximum phase resolution of 0.3 degree, and maximum power consumption of 3.2 mW/GHz in Cadence Spectre circuit simulation. The OCNA effective area is 0.072 mm2 which is the smallest compared to previous research group. The OCNA performance is assess by monitoring the Circuit-under-Test (CUT) frequency characteristics. The proposed OCNA successfully captures the waveform and also the CUT frequency characteristic. © 2012 IEEE.

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A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

Hiraku Y., Hayashi I., Chung H., Kuroda T., Ishikuro H.

Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC    33 - 36 2012年12月

　概要を見る

This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm2. © 2012 IEEE.

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A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating

Sekimoto R., Shikata A., Yoshioka K., Kuroda T., Ishikuro H.

Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC    161 - 164 2012年12月

　概要を見る

This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous operation and boosted self power gating are proposed to improve conversion accuracy and reduce static leakage power. Test chip fabricated in 40nm CMOS process has successfully reduced leakage power by 98% and it performs ENOB of 8.2bit and consumes only 0.65nW with 0.1kS/s at 0.5V. The power consumption is scalable up to 4MS/s and power supply range from 0.4 to 0.7V. The best figure of merit (FoM) of 5.2fJ/conversion-step was obtained with 20kS/s at 0.5V. © 2012 IEEE.

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A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with Costas-loop based synchronization scheme in 65nm CMOS

Liu L., Ishikuro H., Kuroda T.

Proceedings of the Custom Integrated Circuits Conference 2012年11月

ISSN  08865930

　概要を見る

A 100Mb/s 1.37mW impulse-radio ultra-wideband (IR-UWB) receiver with Costas-loop based frequency and phase synchronization scheme is developed in 65nm CMOS. This is the first analog-domain plesiochronous solution for IR-UWB communication in DC-960MHz band without the necessity of traditional analog-to-digital converter (ADC) and digital baseband for signal processing, thereby the receiver achieves the lowest energy of 13.7pJ/bit in state-of-the-art plesiochronous IR-UWB communication. © 2012 IEEE.

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A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and dicode partial-response channel transceivers

Kosuge A., Mizuhara W., Miura N., Taguchi M., Ishikuro H., Kuroda T.

Proceedings of the Custom Integrated Circuits Conference 2012年11月

ISSN  08865930

　概要を見る

A reduced-reflection multi-drop bus system using Dicode (1-D) partial response signaling transceiver is presented for the first time in the world. Directional couplers on transmission lines arranged with equi-energy distributing and exact impedance matched conditions allow the bus to reach to 12.5Gbps/link speed. The transmission line has 5-convex portions to form one side of a coupler where the transmission line width is adjusted to control the characteristic impedance of the coupling section, minimizing signal reflection from each section. Dicode partial-response signaling method with a half-rate architecture was used where a precoder is placed in the transmitter to make the signal best fit for the channel to eliminate inter symbol interference (ISI) where the test chip transmitter occupies 3,750 μm2 and the receiver occupies 750 μm2 with 90nm CMOS technology, consuming 40mA and 23mA respectively at the supply voltage of 1.2V. © 2012 IEEE.

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1-W 3.3-16.3-V boosting wireless power transfer circuits with vector summing power controller

Tomita K., Shinoda R., Kuroda T., Ishikuro H.

IEEE Journal of Solid-State Circuits 47 （ 11 ） 2576 - 2585 2012年09月

ISSN  00189200

　概要を見る

This paper presents SD-card-size wireless power transfer system for large-volume contactless memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the dc-dc converter or charge-pump circuit for data write operation into the flash memory chip. The proposed approach reduces the number of components and BOM cost and improves the total power efficiency. A vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18-μ m-CMOS with high voltage option. Voltage boost from 3.3 to 16.3 V and 1-W power transfer with 50% total efficiency have been successfully demonstrated, and the response time for the power control loop is shorter than 35 μs. © 2012 IEEE.

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Rotary coding for power reduction and S/N improvement in inductive-coupling data communication

Radecki A., Miura N., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 47 （ 11 ） 2643 - 2653 2012年09月

ISSN  00189200

　概要を見る

In this paper, we describe a noncontact inductive-coupling data transmission link employing rotary data encoding. A system using this data-transmission link is inherently insensitive to jitter introduced in the channel and consumes approximately 50% less power than previously reported solutions. The system is targeted for applications benefiting from simultaneous noncontact power and data transmission, such as wafer-level testing, memory card interfaces, and inter-strata data communication in 3-D integrated circuits. Functionality of the proposed link is verified experimentally with a test chip developed in an 0.18-μm CMOS process. In the second part of this paper, we introduce a design of a high-speed data transceiver using rotary coding. We demonstrate that, because of properties of the rotary coding, a simple transceiver without a PLL-based CDR circuit can operate at data rates limited only by characteristics of the physical channel. For performance optimization, we have developed a new family of ternary logic gates including latches, D-flip-flops, and multiplexers. © 2012 IEEE.

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A 0.025-0.45 W 60%-efficiency inductive-coupling power transceiver with 5-bit dual-frequency feedforward control for non-contact memory cards

Chung H., Radecki A., Miura N., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 47 （ 10 ） 2496 - 2504 2012年09月

ISSN  00189200

　概要を見る

A 0.025-0.45 W inductive-coupling power transceiver for non-contact memory applications is presented. To deal with sudden and large load variations and achieve high-efficiency, we propose a power transceiver with 5-bit feedforward control. Knowing that load patterns of a memory card have strong correlation with commands issued by a host, feedforward control is applied to minimize response times. To achieve 5-bit power levels, the proposed transceiver utilizes pulse-density modulation (PDM) and a multi-channel structure. Different operation frequencies are chosen for each channel to maximize power transfer efficiency. To further improve transceiver efficiency and enable high-speed operation, an active rectifier with a fast positive feedback is proposed. The test prototype demonstrates 40%-70% efficiency across all load conditions and 60% efficiency in average, which are over an order of magnitude improvements compared to prior arts. © 1966-2012 IEEE.

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Simultaneous 6-Gb/s data and 10-mW power transmission using nested clover coils for noncontact memory card

Radecki A., Yuan Y., Miura N., Aikawa I., Take Y., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 47 （ 10 ） 2484 - 2495 2012年08月

ISSN  00189200

　概要を見る

An inductive power and data transmission link for a noncontact memory card interface is reported. Nested clover coils improve signal-to-interference ratio and enable simultaneous power and data transmission. This capability is then used in the design of a closed-loop feedback system for improving power transfer efficiency. Interference cancellation mechanism is analyzed with both 3-D EM simulations and a newly developed compact model of coupled inductors. Performance of the proposed solutions was confirmed experimentally using a scaled-down stacked-chip prototype fabricated in a 65-nm CMOS process. Maximum data transmission rate is 6 Gb/s and the total power transfer efficiency is 5.2%-10.2% over a load resistance range of 0.1-2 k$\Omega$. © 1966-2012 IEEE.

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A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS

Matsubara T., Hayashi I., Johari A., Kuroda T., Ishikuro H.

RWW 2012 - Proceedings: IEEE Radio and Wireless Symposium, RWS 2012    71 - 74 2012年05月

　概要を見る

This paper presents a pulse-based inductive-coupling transceiver with adaptive pulse width controller for high-speed wireless proximity communication. Adaptive pulse width controller uses 20 phase clocks generated by a multi-phase digitally-controlled-array-oscillator and prevents the pulse width fluctuation under PVT variation at ultra-low power supply voltage. Pulse generation and its width detection are carried out by the identical multi-phase oscillator, which reduces the circuit area. The test chip implemented in 65nm-CMOS has achieved data rate of 850Mb/s/ch at 0.7V supply voltage and power consumption of 4.1mW. © 2012 IEEE.

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A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme

Abe T., Yuan Y., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 55   442 - 443 2012年05月

ISSN  01936530

　概要を見る

Short-distance (<10cm) wireless communications applications are rapidly expanding. For instance, a fast file transfer by "touch-and-proceed data communication" provides a user-friendly interface for electronic products [1,2]. Wireless I/O's may replace conventional connectors on a PCB to overcome performance limitations [3,4]. High-speed (>Gb/s), low energy dissipation (<100pJ/b), low bit-error-rate (BER<10 -3), and low cost (small layout area in matured CMOS processes) are required as well as compliance with spectral regulation and EMI/EMS. None of the previous research achievements has satisfied all these requirements (Fig. 26.2.6). Non-coherent UWB transceivers are typically low speed and energy hungry; i.e. 15Mb/s with 2680pJ/b in a heterodyne transceiver [1] and 1Mb/s with 373pJ/b in a direct-conversion transceiver [3]. Millimeter-Wave radio is often used to raise the data rate at the cost of increase in energy dissipation. A heterodyne non-coherent 60GHz transceiver performed 2.5Gb/s with 114pJ/b [2]. To further reduce the energy dissipation a direct-conversion coherent 56GHz transceiver was developed in 40nm CMOS and 11Gb/s was achieved with 6.4pJ/b [4]. Unfortunately, as a free-running TX LO and injection-lock carrier synchronization were employed, the injection locking range was very narrow. For an RF input power of -30dBm, the locking range was 60MHz, only 0.1% of the center frequency. Tight control of frequency under variation and noise is not easy for manufacturing. Raising the RF input power is also limited by the FCC spectral mask regulation. In this paper, we present a UWB direct-conversion coherent transceiver in 90nm CMOS. 2Gb/s with 75pJ/b is achieved while meeting the FCC regulation for indoor communications. An IQ-switching carrier recovery scheme is proposed to save layout area and energy dissipation by 43% and 20%, respectively, compared with those in the conventional Costas loop. The transceiver with the proposed carrier recovery scheme uses binary phase shift keying (BPSK) modulation. © 2012 IEEE.

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Voltage-boosting wireless power delivery system with fast load tracker by ΔΣ-modulated sub-harmonic resonant switching

Shinoda R., Tomita K., Hasegawa Y., Ishikuro H.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 55   288 - 289 2012年05月

ISSN  01936530

　概要を見る

Recently, many applications have emerged that use wireless power delivery technology. A new standard "Qi" [1] has been established for battery operated portable devices. The rechargeable battery acts as a power buffer and shields the rapid load variation. Therefore, the requirement of the response to load variation is not so stringent and time constant of the power control loop is longer than several tens of milliseconds. Several hundred kHz band is chosen for switching frequency to reduce the power loss and frequency modulation (FM) [2] or pulse-width modulation (PWM) [3] are used for power control because of their relaxed in-band spurious emission regulation. © 2012 IEEE.

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A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line

Yun W., Nakano S., Mizuhara W., Kosuge A., Miura N., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 55   52 - 53 2012年05月

ISSN  01936530

　概要を見る

As computing power and speed increases, the demand for higher memory bandwidth increases as well. Recently, the memory interface has been improved up to 20Gb/s/link [1]. Considering PCB routing area, a multi-drop bus architecture is still preferable for large memory capacity to the point-to-point connection. However, the multi-drop approach suffers from performance degradations due to reflections at each stub. To mitigate this problem, reference [2] proposes an impedance-matched bidirectional multi-drop DQ bus architecture that is difficult to realize due to smaller series resistor if more than 4 modules are used. To avoid multi-reflections from each stub, other approaches have used coupled transmission lines (CTL) [3, 4]. While a horizontal directional coupler buried in the PCB was used [3], coupled traces on the bent loop of flex fixed to a module were used for signal delivery in vertical direction [4]. In [3], a long coupler with long main bus line was used so that the signal integrity degrades at the far-end coupler. In [4], the coupling traces on the motherboard and the flex have zigzag geometries for better misalignment tolerance, which result in large area of routing due to the minimum required pitch between traces. In [5], the CTL needs to be placed close to a Tx/Rx chip, as there are no extended transmission lines for signal lead. Therefore, it cannot be used for memory modules. DRAM multi-drop bus interface technology mapping is described in Fig. 2.8.1. © 2012 IEEE.

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A 10-bit 80-MS/s decision-select successive approximation TDC in 65-nm CMOS

Chung H., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 47 （ 5 ） 1232 - 1241 2012年05月

ISSN  00189200

　概要を見る

This paper presents a 10-bit 80-MS/s successive approximation time-to-digital converter (TDC) with a decision-select structure for on-chip timing measurement applications. Time-domain successive approximation is realized utilizing a relative timing difference between input and reference timings. While the successive approximation scheme allows high bit resolutions and low power consumptions, the decision-select structure enables fast bit conversions that lead to high sampling rates. The decision-select structure unrolls the successive approximation iteration loop and removes time-consuming timing estimation and adjustment procedures to minimize bit conversion times. As the successive approximation scheme relies on a binary search, exponential delay lines are adopted to achieve good power and noise performances by reducing the total number of delay stages. The proposed TDC uses only 0.048 delay stages per bit conversion. A test-chip prototype fabricated in a 65-nm CMOS technology consumes 9.6 mW at 80-MS/s and demonstrates 0.23-pJ/conversion-step figure-of merit (FOM) and 0.5-LSB single-shot precision. © 2012 IEEE.

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A 0.5 v 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS

Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

IEEE Journal of Solid-State Circuits 47 （ 4 ） 1022 - 1030 2012年04月

ISSN  00189200

　概要を見る

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40 nm CMOS process achieves 46.8 dB SNDR and 58.2 dB SFDR with 1.1 MS/sec at 0.5 V power supply. The FoM is 6.3-fJ/conversion step and the chip die area is only 160 μm × 70 μm. © 2012 IEEE.

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6 W/25 mm² wireless power transmission for non-contact wafer-level testing

Radecki A., Chung H., Yoshida Y., Miura N., Shidei T., Ishikuro H., Kuroda T.

IEICE Transactions on Electronics E95-C （ 4 ） 668 - 676 2012年04月

ISSN  09168524

　概要を見る

Wafer-level testing is a well established solution for detecting manufacturing errors and removing non-functional devices early in the fabrication process. Recently this technique has been facing a number of challenges, resulting from increased complexity of devices under test, larger number and higher density of pads or bumps, application of mechanically fragile materials, such as low-k dielectrics, and ever developing packaging technologies. Most of these difficulties originate from the use of mechanical probes, as they limit testing speed, impose performance limitations and add reliability issues. Earlier work focused on relaxing these constraints by removing mechanical probes for data transmission and DC signal measurement and replacing them with non-contact interfaces. In this paper we extend this concept by adding a capability of transferring power wirelessly, enabling non-contact wafer-level testing. In addition to further improvements in the performance and reliability, this solution enables new testing scenarios such as probing wafers from their backside. The proposed system achieves 6 W/25 mm2 power transfer density over a distance of up to 0.32 mm, making it suitable for non-contact wafer-level testing of medium performance CMOS integrated circuits. © 2012 The Institute of Electronics, Information and Communication Engineers.

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High-frequency precise characterization of intrinsic FinFET channel

Sakai H., O'uchi S., Matsukawa T., Endo K., Liu Y., Tsukada J., Ishikawa Y., Nakagawa T., Sekigawa T., Koike H., Sakamoto K., Masahara M., Ishikuro H.

IEICE Transactions on Electronics E95-C （ 4 ） 752 - 760 2012年04月

ISSN  09168524

　概要を見る

This paper presents a precise characterization of high-frequency characteristics of intrinsic channel of FinFET. For the de-embedding of the parasitics attached to the source, drain and gate terminals, it proposes special calibration patterns which can place the reference surface just beside the intrinsic part of the FinFET. It compares the measured S parameter data up to 40 GHz with the device simulation and shows good matching. The experimental data of the through pattern also confirms the accuracy of the de-embedded parasitics and extracted intrinsic part of FinFET. © 2012 The Institute of Electronics, Information and Communication Engineers.

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A 65fJ/b inter-chip inductive-coupling data transceivers using charge-recycling technique for low-power inter-chip communication in 3-D system integration

Niitsu K., Kawai S., Miura N., Ishikuro H., Kuroda T.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 （ 7 ） 1285 - 1294 2012年

ISSN  10638210

　概要を見る

This paper presents a low-power inductive-coupling link in 90-nm CMOS. Our newly proposed transmitter circuit uses a charge-recycling technique for power-aware 3-D system integration. The cross-type daisy chain enables charge recycling and achieves power reduction without sacrificing communication performance such as a high timing margin, low bit error rate and high bandwidth. There are two design issues in the cross-type daisy chain: pulse amplitude reduction and another is inter-channel skew. To compensate for these issues, an inductor design and a replica circuit are proposed and investigated. Test chips were designed and fabricated in 90-nm CMOS to verify the validity of the proposed transmitter. Measurements revealed that the proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading the timing margin, data rate, or bit error rate. In order to investigate the compatibility of the transmitter with technology scaling, a simulation of each technology node was performed. The simulation results indicate that the energy dissipation can be potentially reduced to less than 10 fJ/bit in 22 nm CMOS with proposed cross-type daisy chain. © 2011 IEEE.

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A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

Sekimoto R., Shikata A., Kuroda T., Ishikuro H.

European Solid-State Circuits Conference    471 - 474 2011年12月

ISSN  19308833

　概要を見る

This paper presents an ultra low power and low voltage successive- approximation-register (SAR) analog-to-digital converter (ADC) that uses an adaptive timing optimized asynchronous clock generator. Compared to asynchronous converters that use the conventional clock generator, the frequency range is expanded by 50% at 0.4V analog and 0.7V digital power supply voltage. By calibrating the delay time of the clock generator, the DAC settling time is optimized to counter the device mismatch. Test chip has been fabricated in 40nm standard CMOS process and achieved figure of merit (FoM) of 8.75-fJ/conversion- step with 2.048MS/s at 0.6V analog and 0.7V digital power supply voltage. The ADC operates from 50S/s to 8MS/s performing over 7.5-ENOB. © 2011 IEEE.

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1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller

Tomita K., Shinoda R., Kuroda T., Ishikuro H.

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011    177 - 180 2011年12月

　概要を見る

This paper presents SD card size wireless power transfer system for large volume contactless memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the DC-DC converter or charge-pump circuit for data write operation into the flash memory chip. The proposed approach reduces the number of components and BOM cost and improve the total power efficiency. Vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18um-CMOS with high voltage option. Voltage boost from 3.3V to 16.3V and 1W power transfer with 50% total efficiency have been successfully demonstrated. © 2011 IEEE.

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A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface

Yun W., Ishikuro H., Kuroda T.

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011    145 - 148 2011年12月

　概要を見る

An all-digital CDR for a pulse-based inductive-coupling interface is presented, which uses a TDC with free running oscillator for seamless oversampling and an all-digital DLL. The TDC utilizes an error correction scheme to reject noise pulses and the DLL recovers the phase information based on a 32-bit digital comparator. Peak-to-peak jitter is 12.2ps with 1.2Gb/s at 1.2V, whereas energy consumption is 4.7pJ/b with 1.2Gb/s at 0.6V. © 2011 IEEE.

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Rotary coding for power reduction and S/N improvement in inductive-coupling data communication

Radecki A., Miura N., Ishikuro H., Kuroda T.

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011    205 - 208 2011年12月

　概要を見る

We present a non-contact inductive-coupling data communication link employing a rotary data encoding scheme. The circuit consumes 50% less power and is inherently more robust to jitter than previously reported solutions. Applications include wafer-level testing, non-contact memory card interfaces and inter-strata data communication in 3D-integrated circuits. © 2011 IEEE.

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A 14-GHz AC-coupled clock distribution scheme with phase averaging technique using single LC-VCO and distributed phase interpolators

Niitsu K., Kulkarni V.V., Kang S., Ishikuro H., Kuroda T.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 （ 11 ） 2058 - 2066 2011年11月

ISSN  10638210

　概要を見る

In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18-μm mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450 μ m, with 6.9 mW of power. The phase noise was measured to be -79.06 dBc/Hz at a 100 kHz offset, - 101.66 dBc/Hz at a 1 MHz offset, and -107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated. © 2011 IEEE.

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Analysis and techniques for mitigating interference from power/signal lines and to SRAM circuits in CMOS inductive-coupling link for low-power 3-D system integration

Niitsu K., Sugimori Y., Kohama Y., Osada K., Irie N., Ishikuro H., Kuroda T.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems （IEEE）  19 （ 10 ） 1902-1907 - 1907 2011年10月

研究論文（学術雑誌）, 単著, 査読有り,  ISSN  10638210

　概要を見る

This paper discusses analysis and techniques for mitigating interference of an inductive-coupling inter-chip link. Electromagnetic interference from power/signal lines and to SRAM circuits was simulated and measured. In order to verify the interference, test chips were designed and fabricated using 65-nm CMOS technology. The measurement results revealed that: 1) interference from power lines depends on the shape of the power lines; 2) interference from signal lines can be canceled by increasing transmitter power by only 9%; and 3) interference with SRAM circuits is less important than other issues under ordinary conditions. Based on the measurement results, interference mitigation techniques are proposed and investigated. © 2010 IEEE.

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A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers    262 - 263 2011年09月

　概要を見る

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step. © 2011 JSAP (Japan Society of Applied Physi.

A power scalable SAR-ADC in 0.18μm-CMOS with 0.5V nano-watt operation

Sekimoto R., Shikata A., Ishikuro H.

Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011    89 - 94 2011年08月

　概要を見る

This paper presents an extremely low-power and low-voltage Analog-to-Digital Converter (ADC) for wireless sensor networks or medical implantable devices. Top plate sampling and bootstrap switch are used to realize ultra low-voltage (0.5V) operation. Configuration of capacitor array which can decrease the number of control bus lines are proposed to reduce the circuit area and power consumption. To further reduce the power consumption, optimal power supply voltages are determined independently for analog blocks and digital blocks considering the tradeoff between the speed and power. Test ADC chip fabricated in 0.18μm-CMOS process has achieved 0.5V, 6nW operation at sampling frequency of 0.4kS/s. The achieved effective number of bit (ENOB) is 7.19-bit. When the supply voltage is increased to 1V, the ADC operates at 820kS/s with power consumption of 30.9μW and ENOB of 7.41-bit. © 2011 IEEE.

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An 0.5V, 0.91pJ/bit, 1.1Gb/s/ch transceiver in 65nm CMOS for high-speed wireless proximity interface

Matsubara T., Hayashi I., Johari A., Kumaki S., Kohira K., Kuroda T., Ishikuro H.

2011 IEEE Radio and Wireless Week, RWW 2011 - 2011 IEEE Radio and Wireless Symposium, RWS 2011    74 - 77 2011年03月

　概要を見る

This paper presents a pulse-based inductivecoupling transceiver in 65nm CMOS for high-speed wireless proximity communication. The transceiver operates at 0.5V supply voltage. A pulse bootstrap circuit and a common drain output stage enables transmitter to operate at ultralow voltage. In the receiver, a gain boosted common-gate amplifier is used to reduce the input impedance and suppress the ringing of received pulse signal. The data rate and energy efficiency are 1.1Gb/s/ch and 0.91pJ/bit, respectively at 0.5V supply voltage. The data rate can be increased to 1.7Gb/s/ch at 0.75V. © 2011 IEEE.

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6W/25mm² inductive power transfer for non-contact wafer-level testing

Radecki A., Chung H., Yoshida Y., Miura N., Shidei T., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference    230 - 231 2011年

ISSN  01936530

　概要を見る

Wafer-level testing allows detection of manufacturing errors and removes nonfunctional devices early in the fabrication process. It is commonly performed by placing a probe card directly above a device under test (DUT) and establishing a mechanical contact between them by means of an array of probes. This is an invasive technique that may damage fragile low-k dielectric layers and deform pads or bumps. More importantly, it is very difficult to flip thinned wafers face up for probing if they were earlier positioned face down for back grinding. Additional difficulty in handling of thinned wafers arises if dies have to be flipped again for bumping. One solution to above problems is wireless probing. With a number of proposed techniques for establishing high-speed inductive-coupling data links [3] and measuring DC analog signal wirelessly [4], the largest remaining obstacle to non-contact wafer-level testing is supplying power to the DUT. This is because wireless power transfer solutions reported earlier [1,5] do not provide an output power that is sufficient for testing modern high performance devices. © 2011 IEEE.

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A 12Gb/s non-contact interface with coupled transmission lines

Takeya T., Nan L., Nakano S., Miura N., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference    492 - 493 2011年

ISSN  01936530

　概要を見る

The expanding capacity of today's memory cards and increasing speed of processors have created demands for high data rate interfaces between memory cards and processors. Compared to conventional contact pins, wireless interfaces have received tremendous interest for reasons of more convenience, higher reliability, and higher data rate. Two major types of near-field wireless communication techniques using capacitive coupling and inductive coupling channels have been investigated. Tens of Gb/s/ch is achieved using both methods with a communication distance of tens of microns in TCI (thru-chip-interface) applications [1-2]. However, when the communication distance denters the mm range in such applications as non-contact memory cards, the sizes of capacitors or inductors must be up scaled to detect enough electrical flux or magnetic flux, whose magnitude decay as 1/dn (n>1). As a result, the self-resonance frequency fSR is reduced significantly, which becomes the dominant limiting factor for the achievable data rate, since the maximum data rate is usually chosen as 1/2 or 1/3 of fSR in order to avoid signal peaking [3]. Although multi-channel solutions are viable to increase the total data rate, complex systems are required to address the skew issues in synchronization, and low area efficiency is resulted to reduce crosstalk interferences as shown in Fig. 28.3.1. © 2011 IEEE.

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High-frequency characterization of intrinsic FinFET channel

Sakai H., O'Uchi S., Matsukawa T., Endo K., Liu Y.X., Tsukada T., Ishikawa Y., Nakagawa T., Sekigawa T., Koike H., Sakamoto K., Masahara M., Ishikuro H.

Proceedings - IEEE International SOI Conference 2010年12月

ISSN  1078621X

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0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit

Johari A., Kumaki S., Matsubara T., Hayashi I., Ishikuro H.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS    232 - 235 2010年12月

　概要を見る

In this paper we have shown the design of a 0.5 V multi-phase digital controlled oscillator (DCO) in 65-nm CMOS. The DCO generates 32 phases and achieved output frequency range from 0.1MHz to 128MHz with maximum power consumption of 0.28μW/MHz in Cadence spectre circuit simulations. To prevent glitch during phase switching, the circuit for smooth phase transition is proposed and successfully demonstrated in circuit simulation. © 2010 IEEE.

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A 0.5V 6-bit scalable phase interpolator

Kumaki S., Johari A., Matsubara T., Hayashi I., Ishikuro H.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS    1019 - 1022 2010年12月

　概要を見る

This paper proposes a scalable phase interpolator (PI) with dual-input inverter. A pseudo-pipelined architecture is proposed to realize resolution scalability and to reduce the circuit size and power consumption. By using a simple architecture, the proposed circuit operates at 0.5V at which conventional analog PI cannot operate. Slew rate of inverter chain is controlled by current starving technique to support phase interpolation at wide input frequency range. The PI was designed in 65nm-CMOS technology. The circuit simulation confirms 6-bit phase resolution, DNL of 0.41 LSB, and INL of 1.25 LSB. The power consumption is 0.12 μW/MHz. © 2010 IEEE.

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A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator

Shikata A., Sekimoto R., Ishikuro H.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS    1015 - 1018 2010年12月

　概要を見る

This paper presents a twice the supply voltage bootstrapped switch with the proposed rise time accelerator that has high linearity and fast rising with single phase clock input at low voltage. The proposed rise time accelerator improves rising time and ensures circuit operation at extremely low supply voltage without any complex timing generation circuit. The prototype switch is designed in 65nm CMOS process and the simulation results show that the power consumption of quasi differential bootstrapped switch is less than 11nW/MHz at a supply voltage of 0.5V with 10MS/sec. The third order harmonic distortion (HD3) is 104dB with sampling capacitor of 1.28pF. © 2010 IEEE.

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A phase-to-digital converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3V

Hayashi I., Matsubara T., Kumaki S., Johari A., Ishikuro H., Kuroda T.

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010    225 - 228 2010年12月

　概要を見る

A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL). ©2010 IEEE.

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Simultaneous 6Gb/s data and 10mW power transmission using nested clover coils for non-contact memory card

Yuan Y., Radecki A., Miura N., Aikawa I., Take Y., Ishikuro H., Kuroda T.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers    199 - 200 2010年10月

　概要を見る

This paper presents a non-contact memory card and a host employing simultaneous data and power transmission through inductive coupling. Nested clover-shaped data coils are proposed for reducing interference from a power link. The host wirelessly tracks current consumption of the card and adjusts transmit power to improve power transfer efficiency. The prototype is implemented in 65nm CMOS. It achieves 6Gb/s data rate and almost 10% power transfer efficiency over a 100-2kΩ range of the load. © 2010 IEEE.

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Wireless proximity interfaces with a pulse-based inductive coupling technique

Ishikuro H., Kuroda T.

IEEE Communications Magazine （IEEE）  48 （ 10 ） 192-199 - 199 2010年10月

研究論文（学術雑誌）, 単著, 査読有り,  ISSN  01636804

　概要を見る

The rapid performance progress in processors and memory cores by technology scaling requires further improvement in interface bandwidth. However, interface bandwidth is not keeping up with the processing speed of the core and is becoming a bottleneck in system performance. To fill the performance gap, wideband lowpower low-cost interfaces are strongly demanded. A wireless proximity interface that uses inductive coupling is one such interface expected to be used for interchip links in high-performance 3D system integration. Inductive coupling interfaces use the magnetic near-field induced by micro-coils. The coils (channels) can be arranged in a dense array because magnetic near-field localizes in the proximity of each coil, and crosstalk between the channels is small. Therefore, inductive coupling interfaces are suitable for wideband low-cost proximity communication. An inductive coupling interface can also realize highly reliable communication with low power consumption. Evaluation systems developed to study the performance of inductive coupling interfaces have demonstrated the feasibility of the interfaces in a wide range of applications. © 2010 IEEE.

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47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Saito M., Yoshida Y., Miura N., Ishikuro H., Kuroda T.

IEEE Transactions on Circuits and Systems I: Regular Papers （IEEE）  48 （ 10 ） 192-199 - 2278 2010年10月

研究論文（学術雑誌）, 単著, 査読有り,  ISSN  15498328

　概要を見る

This paper presents a power reduction scheme and an area reduction scheme in inductive-coupling programmable bus for NAND flash memory stacking. A channel arrangement scheme using three coils enables random access for memory read and memory write. Transmit power is reduced by 47% compared to a previous design with shields. A coil layout style, herein noted as XY coil, allows for the coils to interleave with logic interconnections, resulting in area reduction of 91% relative to at the expense of only 17% transmit power increase. Relayed data transmission at 1.6 Gb/s and BER < 10-12 is achieved. © 2010 IEEE.

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Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip link for low-power 3-D system integration

Niitsu K., Kohama Y., Sugimori Y., Kasuga K., Osada K., Irie N., Ishikuro H., Kuroda T.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems （IEEE）  18 （ 8 ） 1238-1243 - 1243 2010年08月

研究論文（学術雑誌）, 単著, 査読有り,  ISSN  10638210

　概要を見る

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions. © 2006 IEEE.

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A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card

Kawai S., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 53   264 - 265 2010年05月

ISSN  01936530

　概要を見る

An inductive-coupling link has been studied for inter-chip communications in System-in-a-Package [1]. Its communication distance extends millimeter ranges [2,3] and it can be used as a wireless interface for non-contact memory cards. High speed and low power communication can be performed in the inductive-coupling link because of the removal of highly capacitive ESD protection devices [1]. The wireless interface eliminates mechanical contacts resulting in high reliability. Target data rate is 2.5Gb/s/ch which is 12.5x higher than that of a commercial memory card and target communication range is 0.5mm to 1mm, considering the allowance of card insertion. The maximum data rate of the inductive-coupling link demonstrated in [3] at 1mm distance was 160Mb/s/ch. A theoretical limit is 1Gb/s/ch since self resonant frequency of an on-chip inductor of 3GHz. To increase the self resonant frequency, the inductor is moved off chip to a flexible circuit board to reduce parasitic capacitance. The self resonant frequency of 1mm diameter inductor is increased to 4GHz corresponding to a signal data rate of 1.25Gb/s/ch. Additionally, the number of bit per symbol is increased to 2 by 4 pulse amplitude modulation (4PAM) and a data rate of 2.5Gb/s/ch is achieved. But to communicate by using 4PAM in the inductive-coupling link, issues listed below must be solved. First, the communication range is limited to 0.95mm to 1mm. The amplitude of the received signal is inversely proportional to the communication distance, and therefore, received signal cannot be converted to a correct data without adjusting the input threshold voltages of a receiver. Second, the pulse width is narrower in 4PAM and thus synchronization on the receiver side is difficult. ©2010 IEEE.

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2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking

Saito M., Sugimori Y., Kohama Y., Yoshida Y., Miura N., Ishikuro H., Sakurai T., Kuroda T.

IEEE Journal of Solid-State Circuits （IEEE）  45 （ 1 ） 134-141 - 141 2010年01月

研究論文（学術雑誌）, 単著, 査読有り,  ISSN  00189200

　概要を見る

An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuitlayout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8. © 2009 IEEE.

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A High-Speed Inductive-Coupling Link With Burst Transmission

N. Miura, Y. Kohama, Y. Sugimori, H. Ishikuro, T. Sakurai, T. Kuroda

IEEE Journal of Solid-State Circuits （IEEE）  44 （ 3 ） 945-955 2009年03月

研究論文（学術雑誌）, 単著, 査読有り

A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna

V.V.Kulkarni, M. Muqsith, K. Niitsu, H. Ishikuro, T. Kuroda

IEEE Journal of Solid-State Circuits （IEEE）  44 （ 2 ） 394-403 2009年02月

研究論文（学術雑誌）, 単著, 査読有り

A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping

N. Miura, H. Ishikuro, K. Niitsu, T. Sakurai, H. Kuroda

IEEE Journal of Solid-State Circuits （IEEE）  43 （ 1 ） 285-291 2008年01月

研究論文（学術雑誌）, 単著, 査読有り

60% Power Reduction in Inductive-Coupling Inter-Chip Link by Current-Sensing Technique

K. Niitsu, N. Miura, M. Inoue, Y. Nakagawa, M. Tago, M. Mizuno, H. Ishikuro, and T. Kuroda

Japanese Journal of Applied Physics （JSAP）  46 （ 4B ） 2215-2219 2007年04月

研究論文（学術雑誌）, 共著, 査読有り

An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors

K.Ishida, A.Tamtrakarn, H.Ishikuro, M.Takamiya, and T. Sakurai,

IEICE Trans. Electron. （IEICE）  E90-C （ 4 ） 786-792 2007年04月

研究論文（学術雑誌）, 単著, 査読有り

A 2.4-GHz Temperature compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitter

T. Tanzawa, H. Shibayama, R. Terauchi, K. Hisano, H. Ishikuro, S. Kousai, H.Majima, H. Kobayashi, T. Takayama, K. Agawa, M. Koizumi, and F. Hatori

IEICE Trans. Electron （電子情報通信学会）  E88-C4 （ 4 ）  2005年04月

研究論文（研究会，シンポジウム資料等）, 共著, 査読有り

A Full-CMOS Single Chip Bluetooth LSI with 1.5MHz-IF Receiver and Direct Modulation Transmitter

F. Hatori, H. Ishikuro, M. Hamada, K. Agawa, S. Kousai, H. Kobayashi, and D.M.Nguyen

IEICE Trans. Electron. （電子情報通信学会）  E87-C （ 4 ）  2004年04月

研究論文（学術雑誌）, 共著, 査読有り

Large Electron Addition Energy above 250 meV in the Silicon Quantum Dot in a Single Electron Transistor

M. Saitoh, N. Takahashi, H. Ishikuro, and T. Hiramoto

Japanese Journal of Applied Physics 40 （ 3B ） 2010 - 2012 2001年03月

研究論文（学術雑誌）, 共著, 査読有り

Effects of interface traps in silicon-quantum-dots-based memory structures

X. L. Yuan, Y. Shi, S. L. Gu, J. M. Zhu, Y. D. Zheng, K. Saito, H. Ishikuro, and T. Hiramoto

Physica E 8 （ 2 ） 189-193 2000年08月

研究論文（学術雑誌）, 共著, 査読有り

Experimental Evidence for Quantum Mechanical Narrow Channel Effect in Ultra-Narrow MOSFETs

H. Majima, H. Ishikuro, and T. Hiramoto

IEEE Electron Devices Letters 21 （ 8 ） 396 - 398 2000年08月

研究論文（学術雑誌）, 共著, 査読有り

Impact of the Device Scaling on the Low-Frequency Noise in n-MOSFETs

H. M. Bu, Y. Shi, X. L. Yuan, Y. D. Zheng, S. H. Gu, H. Majima, H. Ishikuro, and T. Hiramoto

Applied Physics A A71 （ 2 ） 133 - 136 2000年06月

研究論文（学術雑誌）, 共著, 査読有り

Random telegraph signals and low-frequency noise in n-metal-oxide-semiconductor field-effect transistors with ultranarrow channels

H. M. Bu, Y. Shi, X. L. Yuan, J. Wu, S. L. Gu, and Y. D. Zheng, H. Majima, H. Ishikuro, and T. Hiramoto

Applied Physics Letters 76 （ 22 ） 3259 - 3261 2000年05月

研究論文（学術雑誌）, 共著, 査読有り

Control of Coulomb blockade oscillations in silicon single electron transistor using silicon nano-crystal floating gates

Nobuyoshi Takahashi, Hiroki Ishikuro, and Toshiro Hiramoto

Applied Physics Letters 76 （ 2 ） 209 - 211 2000年01月

研究論文（学術雑誌）, 共著, 査読有り

Characteristic Distributions of Narrow Channel Metal-Oxide-Semiconductor Field-Effect-Transistor Memories with Silicon Nanocrystal Floating Gates

Eiji Nagata, Nobuyoshi Takahashi, Yuri Yasuda, Takashi Inukai, Hiroki Ishikuro, and Toshiro Hiramoto

Japanese Journal of Applied Physics 38 （ 12B ） 7230 - 7232 1999年12月

研究論文（学術雑誌）, 共著, 査読有り

Highly Integrated Single Electron Devices and Giga-bit Lithography

Toshiro Hiramoto, H. Ishikuro, and H. Majima

Journal of Photopolymer Science and Technology 12 （ 3 ） 417 - 422 1999年06月

研究論文（学術雑誌）, 共著, 査読有り

Coulomb Blockade in VLSI-Compatible Multiple-Dot and Single-Dot MOSFETs

Toshiro Hiramoto and Hiroki Ishikuro

International Journal of Electronics 86 （ 5 ） 591 - 603 1999年05月

研究論文（学術雑誌）, 単著, 査読有り

Characteristics of Narrow Channel MOSFET Memory Based on Silicon Nanocrystals

Yi Shi, Kenichi Saito, Hiroki Ishikuro, and Toshiro Hiramoto

Japanese Journal of Applied Physics 38 （ 4B ） 2453 - 2456 1999年04月

研究論文（学術雑誌）, 共著, 査読有り

Measurement of Energetic and Lateral Distribution of Interface State Density in FD SOI MOSFETs

Tran Ngoc Duyet, Hiroki Ishikuro, Yi Shi, Takuya Saraya, Makoto Takamiya, and Toshiro Hiramoto

Japanese Journal of Applied Physics 38 （ 4B ） 2496 - 2500 1999年04月

研究論文（学術雑誌）, 共著, 査読有り

On the origin of tunneling barriers in silicon single electron and single hole transistors

H. Ishikuro and T. Hiramoto

Applied Physics Letters 74 （ 8 ） 1126 - 1128 1999年02月

研究論文（学術雑誌）, 共著, 査読有り

Effects of Interface Traps on Charge Retention Characteristics in Silicon-Quantum-Dot-Based Metal-Oxide-Semiconductor Diodes

Yi Shi, Kenichi Saito, Hiroki Ishikuro, and Toshiro Hiramoto

Japanese Journal of Applied Physics 38 （ 1B ） 425 - 428 1999年01月

研究論文（学術雑誌）, 共著, 査読有り

Fabrication of Nano-Scale Point Contact Metal-Oxide-Semiconductor Field-Effect-Transistors Using Micrometer-Scale Design Rule

Hiroki Ishikuro and Toshiro Hiramoto

Japanese Journal of Applied Physics 38 （ 1B ） 396-398 1999年01月

研究論文（学術雑誌）, 共著, 査読有り

Quantum Energy and Charging Energy in Point Contact MOSFETs acting as Single Electron Transistors

Toshiro Hiramoto and Hiroki Ishikuro

Superlattices and Microstructures 24 （ 1-2 ） 263 - 267 1999年

研究論文（学術雑誌）, 共著, 査読有り

Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals

Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto

Journal of Applied Physics 84 （ 4 ） 2358-2360 1998年08月

研究論文（学術雑誌）, 共著, 査読有り

Hopping Transport in Multiple-Dot Silicon Single Electron MOSFET, Solid State Electronics

H. Ishikuro and T. Hiramoto

Solid State Electronics 42 （ 7-8 ） 1425 - 1428 1998年07月

研究論文（学術雑誌）, 共著, 査読有り

Suppression of Geometric Component of Charge Pumping Current in Thin Film SOI MOSFET

N. Duyet, H. Ishikuro, M. Takamiya, T. Saraya, and T. Hiramoto

Japanese Journal of Applied Physics 37 （ 7B ） L855 - L858 1998年07月

研究論文（学術雑誌）, 共著, 査読有り

Fabrication of Gate-All Around MOSFET by Silicon Anisotropic Etching Technique

T. Mukaiyama, K. Saito, H. Ishikuro, M. Takamiya, T. Saraya, and T. Hiramoto

Solid State Electronics 42 （ 7-8 ） 1623 - 1626 1998年06月

研究論文（学術雑誌）, 共著, 査読有り

Quantum mechanical effects in the silicon quantum dot in a single-electron-transistor

Hiroki Ishikuro and Toshiro Hiramoto

Applied Physics Letters 71 （ 25 ） 3691 - 3693 1997年12月

研究論文（学術雑誌）, 共著, 査読有り

Room Temperature Coulomb Blockade and Low Temperature Hopping Transport in a Multiple-Dot-Channel MOSFET

T. Hiramoto, H. Ishikuro, T. Fujii, G. Hashiguchi, and T. Ikoma

Japanese Journal of Applied Physics 36 （ 6B ） 4139 - 4142 1997年06月

研究論文（学術雑誌）, 共著, 査読有り

Fabirication of Si Nano-Structures for Single Electron Device Applications by Anisotropic Etching

T. Hiramoto, H. Ishikuro, K. Saito, T. Fujii, T. Saraya, G. Hashiguchi, and T. Ikoma

Japanese Journal of Applied Physics 35 （ 12B ） 6664 - 6667 1996年12月

研究論文（学術雑誌）, 共著, 査読有り

Coulomb Blockade Oscillations at Room Temperature in a Si Quantum Wire Metal-Oxide-Semiconductor Field-Effect-Transistor Fabricated by Anisotropic Etching on a Silicon-on-Insulator Substrate

H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, T. Hiramoto, and T. Ikoma

Applied Physics Letters 68 （ 25 ） 3585 - 3587 1996年06月

研究論文（学術雑誌）, 共著

Extremely Large Amplitude Random Telegraph Signals in a Very Narrow Split-Gate MOSFET at Low Temperatures

H. Ishikuro, T. Saraya, T. Hiramoto, and T. Ikoma

Japanese Journal of Applied Physics 35 （ 2B ） 858 - 860 1996年02月

研究論文（学術雑誌）, 共著, 査読有り

Characterization of Precisely Width-Controlled Si Quantum Wires Fabricated on SOI Substrates

T. Hiramoto, H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, and T. Ikoma

Physics B 227   95 - 97 1996年

研究論文（学術雑誌）, 共著, 査読有り