論文 - 石黒　仁揮

A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS

Matsubara T., Hayashi I., Johari A., Kuroda T., Ishikuro H.

RWW 2012 - Proceedings: IEEE Radio and Wireless Symposium, RWS 2012    71 - 74 2012年05月

　概要を見る

This paper presents a pulse-based inductive-coupling transceiver with adaptive pulse width controller for high-speed wireless proximity communication. Adaptive pulse width controller uses 20 phase clocks generated by a multi-phase digitally-controlled-array-oscillator and prevents the pulse width fluctuation under PVT variation at ultra-low power supply voltage. Pulse generation and its width detection are carried out by the identical multi-phase oscillator, which reduces the circuit area. The test chip implemented in 65nm-CMOS has achieved data rate of 850Mb/s/ch at 0.7V supply voltage and power consumption of 4.1mW. © 2012 IEEE.

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A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme

Abe T., Yuan Y., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 55   442 - 443 2012年05月

ISSN  01936530

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Short-distance (<10cm) wireless communications applications are rapidly expanding. For instance, a fast file transfer by "touch-and-proceed data communication" provides a user-friendly interface for electronic products [1,2]. Wireless I/O's may replace conventional connectors on a PCB to overcome performance limitations [3,4]. High-speed (>Gb/s), low energy dissipation (<100pJ/b), low bit-error-rate (BER<10 -3), and low cost (small layout area in matured CMOS processes) are required as well as compliance with spectral regulation and EMI/EMS. None of the previous research achievements has satisfied all these requirements (Fig. 26.2.6). Non-coherent UWB transceivers are typically low speed and energy hungry; i.e. 15Mb/s with 2680pJ/b in a heterodyne transceiver [1] and 1Mb/s with 373pJ/b in a direct-conversion transceiver [3]. Millimeter-Wave radio is often used to raise the data rate at the cost of increase in energy dissipation. A heterodyne non-coherent 60GHz transceiver performed 2.5Gb/s with 114pJ/b [2]. To further reduce the energy dissipation a direct-conversion coherent 56GHz transceiver was developed in 40nm CMOS and 11Gb/s was achieved with 6.4pJ/b [4]. Unfortunately, as a free-running TX LO and injection-lock carrier synchronization were employed, the injection locking range was very narrow. For an RF input power of -30dBm, the locking range was 60MHz, only 0.1% of the center frequency. Tight control of frequency under variation and noise is not easy for manufacturing. Raising the RF input power is also limited by the FCC spectral mask regulation. In this paper, we present a UWB direct-conversion coherent transceiver in 90nm CMOS. 2Gb/s with 75pJ/b is achieved while meeting the FCC regulation for indoor communications. An IQ-switching carrier recovery scheme is proposed to save layout area and energy dissipation by 43% and 20%, respectively, compared with those in the conventional Costas loop. The transceiver with the proposed carrier recovery scheme uses binary phase shift keying (BPSK) modulation. © 2012 IEEE.

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Voltage-boosting wireless power delivery system with fast load tracker by ΔΣ-modulated sub-harmonic resonant switching

Shinoda R., Tomita K., Hasegawa Y., Ishikuro H.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 55   288 - 289 2012年05月

ISSN  01936530

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Recently, many applications have emerged that use wireless power delivery technology. A new standard "Qi" [1] has been established for battery operated portable devices. The rechargeable battery acts as a power buffer and shields the rapid load variation. Therefore, the requirement of the response to load variation is not so stringent and time constant of the power control loop is longer than several tens of milliseconds. Several hundred kHz band is chosen for switching frequency to reduce the power loss and frequency modulation (FM) [2] or pulse-width modulation (PWM) [3] are used for power control because of their relaxed in-band spurious emission regulation. © 2012 IEEE.

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A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line

Yun W., Nakano S., Mizuhara W., Kosuge A., Miura N., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 55   52 - 53 2012年05月

ISSN  01936530

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As computing power and speed increases, the demand for higher memory bandwidth increases as well. Recently, the memory interface has been improved up to 20Gb/s/link [1]. Considering PCB routing area, a multi-drop bus architecture is still preferable for large memory capacity to the point-to-point connection. However, the multi-drop approach suffers from performance degradations due to reflections at each stub. To mitigate this problem, reference [2] proposes an impedance-matched bidirectional multi-drop DQ bus architecture that is difficult to realize due to smaller series resistor if more than 4 modules are used. To avoid multi-reflections from each stub, other approaches have used coupled transmission lines (CTL) [3, 4]. While a horizontal directional coupler buried in the PCB was used [3], coupled traces on the bent loop of flex fixed to a module were used for signal delivery in vertical direction [4]. In [3], a long coupler with long main bus line was used so that the signal integrity degrades at the far-end coupler. In [4], the coupling traces on the motherboard and the flex have zigzag geometries for better misalignment tolerance, which result in large area of routing due to the minimum required pitch between traces. In [5], the CTL needs to be placed close to a Tx/Rx chip, as there are no extended transmission lines for signal lead. Therefore, it cannot be used for memory modules. DRAM multi-drop bus interface technology mapping is described in Fig. 2.8.1. © 2012 IEEE.

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A 10-bit 80-MS/s decision-select successive approximation TDC in 65-nm CMOS

Chung H., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 47 （ 5 ） 1232 - 1241 2012年05月

ISSN  00189200

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This paper presents a 10-bit 80-MS/s successive approximation time-to-digital converter (TDC) with a decision-select structure for on-chip timing measurement applications. Time-domain successive approximation is realized utilizing a relative timing difference between input and reference timings. While the successive approximation scheme allows high bit resolutions and low power consumptions, the decision-select structure enables fast bit conversions that lead to high sampling rates. The decision-select structure unrolls the successive approximation iteration loop and removes time-consuming timing estimation and adjustment procedures to minimize bit conversion times. As the successive approximation scheme relies on a binary search, exponential delay lines are adopted to achieve good power and noise performances by reducing the total number of delay stages. The proposed TDC uses only 0.048 delay stages per bit conversion. A test-chip prototype fabricated in a 65-nm CMOS technology consumes 9.6 mW at 80-MS/s and demonstrates 0.23-pJ/conversion-step figure-of merit (FOM) and 0.5-LSB single-shot precision. © 2012 IEEE.

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A 0.5 v 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS

Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

IEEE Journal of Solid-State Circuits 47 （ 4 ） 1022 - 1030 2012年04月

ISSN  00189200

　概要を見る

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40 nm CMOS process achieves 46.8 dB SNDR and 58.2 dB SFDR with 1.1 MS/sec at 0.5 V power supply. The FoM is 6.3-fJ/conversion step and the chip die area is only 160 μm × 70 μm. © 2012 IEEE.

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6 W/25 mm² wireless power transmission for non-contact wafer-level testing

Radecki A., Chung H., Yoshida Y., Miura N., Shidei T., Ishikuro H., Kuroda T.

IEICE Transactions on Electronics E95-C （ 4 ） 668 - 676 2012年04月

ISSN  09168524

　概要を見る

Wafer-level testing is a well established solution for detecting manufacturing errors and removing non-functional devices early in the fabrication process. Recently this technique has been facing a number of challenges, resulting from increased complexity of devices under test, larger number and higher density of pads or bumps, application of mechanically fragile materials, such as low-k dielectrics, and ever developing packaging technologies. Most of these difficulties originate from the use of mechanical probes, as they limit testing speed, impose performance limitations and add reliability issues. Earlier work focused on relaxing these constraints by removing mechanical probes for data transmission and DC signal measurement and replacing them with non-contact interfaces. In this paper we extend this concept by adding a capability of transferring power wirelessly, enabling non-contact wafer-level testing. In addition to further improvements in the performance and reliability, this solution enables new testing scenarios such as probing wafers from their backside. The proposed system achieves 6 W/25 mm2 power transfer density over a distance of up to 0.32 mm, making it suitable for non-contact wafer-level testing of medium performance CMOS integrated circuits. © 2012 The Institute of Electronics, Information and Communication Engineers.

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High-frequency precise characterization of intrinsic FinFET channel

Sakai H., O'uchi S., Matsukawa T., Endo K., Liu Y., Tsukada J., Ishikawa Y., Nakagawa T., Sekigawa T., Koike H., Sakamoto K., Masahara M., Ishikuro H.

IEICE Transactions on Electronics E95-C （ 4 ） 752 - 760 2012年04月

ISSN  09168524

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This paper presents a precise characterization of high-frequency characteristics of intrinsic channel of FinFET. For the de-embedding of the parasitics attached to the source, drain and gate terminals, it proposes special calibration patterns which can place the reference surface just beside the intrinsic part of the FinFET. It compares the measured S parameter data up to 40 GHz with the device simulation and shows good matching. The experimental data of the through pattern also confirms the accuracy of the de-embedded parasitics and extracted intrinsic part of FinFET. © 2012 The Institute of Electronics, Information and Communication Engineers.

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A 65fJ/b inter-chip inductive-coupling data transceivers using charge-recycling technique for low-power inter-chip communication in 3-D system integration

Niitsu K., Kawai S., Miura N., Ishikuro H., Kuroda T.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 （ 7 ） 1285 - 1294 2012年

ISSN  10638210

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This paper presents a low-power inductive-coupling link in 90-nm CMOS. Our newly proposed transmitter circuit uses a charge-recycling technique for power-aware 3-D system integration. The cross-type daisy chain enables charge recycling and achieves power reduction without sacrificing communication performance such as a high timing margin, low bit error rate and high bandwidth. There are two design issues in the cross-type daisy chain: pulse amplitude reduction and another is inter-channel skew. To compensate for these issues, an inductor design and a replica circuit are proposed and investigated. Test chips were designed and fabricated in 90-nm CMOS to verify the validity of the proposed transmitter. Measurements revealed that the proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading the timing margin, data rate, or bit error rate. In order to investigate the compatibility of the transmitter with technology scaling, a simulation of each technology node was performed. The simulation results indicate that the energy dissipation can be potentially reduced to less than 10 fJ/bit in 22 nm CMOS with proposed cross-type daisy chain. © 2011 IEEE.

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A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

Sekimoto R., Shikata A., Kuroda T., Ishikuro H.

European Solid-State Circuits Conference    471 - 474 2011年12月

ISSN  19308833

　概要を見る

This paper presents an ultra low power and low voltage successive- approximation-register (SAR) analog-to-digital converter (ADC) that uses an adaptive timing optimized asynchronous clock generator. Compared to asynchronous converters that use the conventional clock generator, the frequency range is expanded by 50% at 0.4V analog and 0.7V digital power supply voltage. By calibrating the delay time of the clock generator, the DAC settling time is optimized to counter the device mismatch. Test chip has been fabricated in 40nm standard CMOS process and achieved figure of merit (FoM) of 8.75-fJ/conversion- step with 2.048MS/s at 0.6V analog and 0.7V digital power supply voltage. The ADC operates from 50S/s to 8MS/s performing over 7.5-ENOB. © 2011 IEEE.

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1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller

Tomita K., Shinoda R., Kuroda T., Ishikuro H.

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011    177 - 180 2011年12月

　概要を見る

This paper presents SD card size wireless power transfer system for large volume contactless memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the DC-DC converter or charge-pump circuit for data write operation into the flash memory chip. The proposed approach reduces the number of components and BOM cost and improve the total power efficiency. Vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18um-CMOS with high voltage option. Voltage boost from 3.3V to 16.3V and 1W power transfer with 50% total efficiency have been successfully demonstrated. © 2011 IEEE.

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A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface

Yun W., Ishikuro H., Kuroda T.

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011    145 - 148 2011年12月

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An all-digital CDR for a pulse-based inductive-coupling interface is presented, which uses a TDC with free running oscillator for seamless oversampling and an all-digital DLL. The TDC utilizes an error correction scheme to reject noise pulses and the DLL recovers the phase information based on a 32-bit digital comparator. Peak-to-peak jitter is 12.2ps with 1.2Gb/s at 1.2V, whereas energy consumption is 4.7pJ/b with 1.2Gb/s at 0.6V. © 2011 IEEE.

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Rotary coding for power reduction and S/N improvement in inductive-coupling data communication

Radecki A., Miura N., Ishikuro H., Kuroda T.

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011    205 - 208 2011年12月

　概要を見る

We present a non-contact inductive-coupling data communication link employing a rotary data encoding scheme. The circuit consumes 50% less power and is inherently more robust to jitter than previously reported solutions. Applications include wafer-level testing, non-contact memory card interfaces and inter-strata data communication in 3D-integrated circuits. © 2011 IEEE.

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A 14-GHz AC-coupled clock distribution scheme with phase averaging technique using single LC-VCO and distributed phase interpolators

Niitsu K., Kulkarni V.V., Kang S., Ishikuro H., Kuroda T.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 （ 11 ） 2058 - 2066 2011年11月

ISSN  10638210

　概要を見る

In this paper, we report the world's first ac-coupled clock distribution circuit for low-power and high-frequency clock distribution. By employing the proposed ac-coupled LC-based voltage-controlled oscillator (LC-VCO) and phase interpolators, the use of conventional current-mode-logic (CML) buffers with large power requirements can be prevented, and power consumption for clock distribution can be reduced. With the aim of verifying the effectiveness of the proposed circuit, test chips were designed and fabricated in 0.18-μm mixed-signal CMOS technology. The measured results indicated a 14.007 GHz clock distribution to four points whose pitches are 450 μ m, with 6.9 mW of power. The phase noise was measured to be -79.06 dBc/Hz at a 100 kHz offset, - 101.66 dBc/Hz at a 1 MHz offset, and -107.25 dBc/Hz at a 10 MHz offset, with a clock frequency of 12.96 GHz. Furthermore, a phase averaging technique for reducing phase deviation was proposed and theoretically investigated. © 2011 IEEE.

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Analysis and techniques for mitigating interference from power/signal lines and to SRAM circuits in CMOS inductive-coupling link for low-power 3-D system integration

Niitsu K., Sugimori Y., Kohama Y., Osada K., Irie N., Ishikuro H., Kuroda T.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems （IEEE）  19 （ 10 ） 1902-1907 - 1907 2011年10月

研究論文（学術雑誌）, 単著, 査読有り,  ISSN  10638210

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This paper discusses analysis and techniques for mitigating interference of an inductive-coupling inter-chip link. Electromagnetic interference from power/signal lines and to SRAM circuits was simulated and measured. In order to verify the interference, test chips were designed and fabricated using 65-nm CMOS technology. The measurement results revealed that: 1) interference from power lines depends on the shape of the power lines; 2) interference from signal lines can be canceled by increasing transmitter power by only 9%; and 3) interference with SRAM circuits is less important than other issues under ordinary conditions. Based on the measurement results, interference mitigation techniques are proposed and investigated. © 2010 IEEE.

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A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers    262 - 263 2011年09月

　概要を見る

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step. © 2011 JSAP (Japan Society of Applied Physi.

A power scalable SAR-ADC in 0.18μm-CMOS with 0.5V nano-watt operation

Sekimoto R., Shikata A., Ishikuro H.

Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011    89 - 94 2011年08月

　概要を見る

This paper presents an extremely low-power and low-voltage Analog-to-Digital Converter (ADC) for wireless sensor networks or medical implantable devices. Top plate sampling and bootstrap switch are used to realize ultra low-voltage (0.5V) operation. Configuration of capacitor array which can decrease the number of control bus lines are proposed to reduce the circuit area and power consumption. To further reduce the power consumption, optimal power supply voltages are determined independently for analog blocks and digital blocks considering the tradeoff between the speed and power. Test ADC chip fabricated in 0.18μm-CMOS process has achieved 0.5V, 6nW operation at sampling frequency of 0.4kS/s. The achieved effective number of bit (ENOB) is 7.19-bit. When the supply voltage is increased to 1V, the ADC operates at 820kS/s with power consumption of 30.9μW and ENOB of 7.41-bit. © 2011 IEEE.

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An 0.5V, 0.91pJ/bit, 1.1Gb/s/ch transceiver in 65nm CMOS for high-speed wireless proximity interface

Matsubara T., Hayashi I., Johari A., Kumaki S., Kohira K., Kuroda T., Ishikuro H.

2011 IEEE Radio and Wireless Week, RWW 2011 - 2011 IEEE Radio and Wireless Symposium, RWS 2011    74 - 77 2011年03月

　概要を見る

This paper presents a pulse-based inductivecoupling transceiver in 65nm CMOS for high-speed wireless proximity communication. The transceiver operates at 0.5V supply voltage. A pulse bootstrap circuit and a common drain output stage enables transmitter to operate at ultralow voltage. In the receiver, a gain boosted common-gate amplifier is used to reduce the input impedance and suppress the ringing of received pulse signal. The data rate and energy efficiency are 1.1Gb/s/ch and 0.91pJ/bit, respectively at 0.5V supply voltage. The data rate can be increased to 1.7Gb/s/ch at 0.75V. © 2011 IEEE.

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6W/25mm² inductive power transfer for non-contact wafer-level testing

Radecki A., Chung H., Yoshida Y., Miura N., Shidei T., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference    230 - 231 2011年

ISSN  01936530

　概要を見る

Wafer-level testing allows detection of manufacturing errors and removes nonfunctional devices early in the fabrication process. It is commonly performed by placing a probe card directly above a device under test (DUT) and establishing a mechanical contact between them by means of an array of probes. This is an invasive technique that may damage fragile low-k dielectric layers and deform pads or bumps. More importantly, it is very difficult to flip thinned wafers face up for probing if they were earlier positioned face down for back grinding. Additional difficulty in handling of thinned wafers arises if dies have to be flipped again for bumping. One solution to above problems is wireless probing. With a number of proposed techniques for establishing high-speed inductive-coupling data links [3] and measuring DC analog signal wirelessly [4], the largest remaining obstacle to non-contact wafer-level testing is supplying power to the DUT. This is because wireless power transfer solutions reported earlier [1,5] do not provide an output power that is sufficient for testing modern high performance devices. © 2011 IEEE.

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A 12Gb/s non-contact interface with coupled transmission lines

Takeya T., Nan L., Nakano S., Miura N., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference    492 - 493 2011年

ISSN  01936530

　概要を見る

The expanding capacity of today's memory cards and increasing speed of processors have created demands for high data rate interfaces between memory cards and processors. Compared to conventional contact pins, wireless interfaces have received tremendous interest for reasons of more convenience, higher reliability, and higher data rate. Two major types of near-field wireless communication techniques using capacitive coupling and inductive coupling channels have been investigated. Tens of Gb/s/ch is achieved using both methods with a communication distance of tens of microns in TCI (thru-chip-interface) applications [1-2]. However, when the communication distance denters the mm range in such applications as non-contact memory cards, the sizes of capacitors or inductors must be up scaled to detect enough electrical flux or magnetic flux, whose magnitude decay as 1/dn (n>1). As a result, the self-resonance frequency fSR is reduced significantly, which becomes the dominant limiting factor for the achievable data rate, since the maximum data rate is usually chosen as 1/2 or 1/3 of fSR in order to avoid signal peaking [3]. Although multi-channel solutions are viable to increase the total data rate, complex systems are required to address the skew issues in synchronization, and low area efficiency is resulted to reduce crosstalk interferences as shown in Fig. 28.3.1. © 2011 IEEE.

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