論文 - 石黒　仁揮

A 0.5-v 5.2-fj/conversion-step full asynchronous sar adc with leakage power reduction down to 650 pw by boosted self-power gating in 40-nm CMOS

Sekimoto R., Shikata A., Yoshioka K., Kuroda T., Ishikuro H.

IEEE Journal of Solid-State Circuits 48 （ 11 ） 2628 - 2636 2013年08月

ISSN  00189200

　概要を見る

This paper presents an ultralow-power and ultralow-voltage SAR ADC. Full asynchronous operation and boosted self-power gating are proposed to improve conversion accuracy and reduce static leakage power. By designing with MOSFET of high threshold voltage (rm HVt) and low threshold voltage (rm LVt), the leakage power is reduced without decrease of maximum sampling frequency. The test chip in 40-nm CMOS process has successfully reduced leakage power by 98%, and it achieves 8.2-bit ENOB and while consuming only 650 pW at 0.1 kS/s from 0.5-V power supply. The power consumption is scalable up to 4 MS/s and power supply range from 0.4 to 0.7 V. The best figure of merit at 0.5 V is 5.2 fJ/conversion-step at 20 kS/s. © 2013 IEEE.

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An adaptive DAC settling waiting time optimized ultra low voltage asynchronous SAR ADC in 40 nm CMOS

Sekimoto R., Shikata A., Yoshioka K., Kuroda T., Ishikuro H.

IEICE Transactions on Electronics E96-C （ 6 ） 820 - 827 2013年06月

ISSN  09168524

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An ultra low power and low voltage successive-approximation-register (SAR) analog-to-digital converter (ADC) with timing optimized asynchronous clock generator is presented. By calibrating the delay amount of the clock generator, the DAC settling waiting time is adaptively optimized to counter the device mismatch. This technique improved the maximum sampling frequency by 40% keeping ENOB around 7-bit at 0.4 V analog and 0.7 V digital power supply voltage. The delay time dependency on power supply has small effect to the accuracy of conversion. Decreasing of supply voltage by 9% degrades ENOB only by 0.1-bit, and the proposed calibration can give delay margins for high voltage swing. The prototype ADC fabricated in 40 nm CMOS process achieved figure of merit (FoM) of 8.75-fJ/conversion-step with 2.048 MS/s at 0.6 V analog and 0.7 V digital power supply voltage. The ADC can operates from 50 S/s to 8 MS/s keeping ENOB over 7.5-bit. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

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A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC

Yoshioka K., Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC    111 - 112 2013年05月

　概要を見る

An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V. © 2013 IEEE.

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A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and dicode partial-response channel transceivers

Kosuge A., Mizuhara W., Miura N., Taguchi M., Ishikuro H., Kuroda T.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC    91 - 92 2013年05月

　概要を見る

A reduced-reflection multi-drop bus system using Dicode (1-D) partial response signaling transceiver is presented for the first time in the world. Directional couplers on transmission lines arranged with equi-energy distributing and exact impedance matched conditions allow the bus to reach to 12.5Gbps/link speed, which is the world's fastest data link speed with multi-drop bus architecture. Dicode partial-response signaling method with a half-rate architecture was used where a precoder is placed in the transmitter to make the signal best fit for the channel to eliminate inter symbol interference (ISI). © 2013 IEEE.

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A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA

Jyo T., Kuroda T., Ishikuro H.

IEEE Radio and Wireless Symposium, RWS    217 - 219 2013年05月

ISSN  21642958

　概要を見る

This paper presents a small size, low-power inductive-coupling receiver for wireless proximity communication. Area efficient active inductor peaking is used to expand the bandwidth of low voltage LNA. Proposed LNA can operate intermittently, synchronized with received pulse timing and reduces the power consumption at low data rate. Clock is extracted from the received pulse signal by simple combination of imbalanced inverters. The fabricated test chip in 65nm-CMOS occupies 0.035mm2 and achieved 1.6Gbps with power consumption of 1.76mW at 0.8V power supply. © 2013 IEEE.

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A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler

Mizuhara W., Shidei T., Kosuge A., Takeya T., Miura N., Taguchi M., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 56   200 - 201 2013年04月

ISSN  01936530

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As silicon chip performance continues to increase, the interconnection capabilities should also be improved to achieve higher overall system performance. This paper proposes a new, small-size and high-speed non-contact interconnect between printed circuit boards (PCBs) using a vertical directional coupler (VDC), which has actually been applied to a liquid crystal display (LCD) driver board. The feasibility of a millimeter-range non-contact interface using a directional coupler was studied previously [1]. In this paper, two signal ports have been implemented in one coupler by best utilizing the characteristics of VDC. The coupler size is 5mm × 2.25mm, and the gap between the couplers is about 75μm, which corresponds to the twofold thickness of a soldering resist on PCB and the adhesive material in between. The transmitter transforms the data sequence from Non-Return-to-Zero (NRZ) into pulses in order to reduce the level of DC components. This achieves a power saving of 1.47pJ/b, and the pulses are sent to the coupler in differential mode to prevent electromagnetic interference (EMI). The measured speed was 4.6Gb/s per coupler to achieve the MIPI's maximum speed of 6Gb/s with two couplers. Conventional connectors have housings to protect contact elements or to provide mechanical support for plug-in and out. However, these housings make it difficult to achieve the smallest possible systems because they require extra space. In addition, they sometimes make the PCB trace longer, which deteriorates the maximum data rate. The method we have developed involves delineating VDC on PCB or a flexible printed circuit (FPC) to connect boards without housings and with the minimum distance. As a result, this interconnect scheme is advantageous not only because it saves space but also because it makes it easier to build systems, even those that contain a large number of built-in connectors. Thus, the proposed non-contact interconnect is suitable for future small-size systems. © 2013 IEEE.

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3D clock distribution using vertically/horizontally-coupled resonators

Take Y., Miura N., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 56   258 - 259 2013年04月

ISSN  01936530

　概要を見る

Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages. © 2013 IEEE.

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1=f noise characteristics of fin-type field-effect transistors in saturation region

Sakai H., O'uchi S.I., Endo K., Matsukawa T., Liu Y., Ishikawa Y., Tsukada J., Nakagawa T., Sekigawa T., Koike H., Masahara M., Ishikuro H.

Japanese Journal of Applied Physics 52 （ 4 PART 2 ）  2013年04月

ISSN  00214922

　概要を見る

In this work, we measured 1=f noise of independent-double-gate-(IDG-) fin-type FET (FinFET) which has two independent gates. Flicker noise of common-double-gate-(CDG-) mode which both gates are applied with the same voltage and IDG-mode that has one gate voltage grounded and the other gate voltage applied with arbitrary voltage, and both result were compared with the same drain current (Id). First, we measured relationship between characteristic of the normalized 1=f noise by Id (SId =I2 d ) and characteristic of Id. Both the SId =I2 d of IDG-and CDG-modes show nearly equal values and tendency. Next, this work also shows the relationship between 1=f noise and vertical electric field (Ei) of surface of gate oxide film. As a result we could not definitely see a large margin of 1=f noise between CDG-and IDG-modes from Ei. This work also discovered that 1=f noise was greatly influenced by Id density. © 2013 The Japan Society of Applied Physics.

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A 12-Gb/s non-contact interface with coupled transmission lines

Takeya T., Nan L., Nakano S., Miura N., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 48 （ 3 ） 790 - 800 2013年03月

ISSN  00189200

　概要を見る

This paper presents a high data rate, non-contact interface using a coupled transmission line (CTL) composed of two differential transmission lines. The proposed CTL can achieve a measured loss of-13.4 dB and a 3-db bandwidth of 3.4-9.0 GHz as a non-contact channel for a 1-mm communication distance. This wideband characteristic makes it possible to achieve high-speed communication using a single channel. The hysteresis buffer-based receiver recovers the transmitted data from the distorted waveforms derived from the AC coupling characteristics of the channel. The interference from the power delivery coil to the CTL is also evaluated. The simulated results showed that the interference was less than-57.8 dB at 13.56 MHz. The system could achieve a communication speed of 12 Gb/s with a BER < 10-12 at a communication distance of 1 mm both with and without a wireless power supply of 75 mArms. The timing margin with the wireless power supply was 41 ps (=0.49 UI). © 1966-2012 IEEE.

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A 4-10 bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS withWide Supply Voltage Range SAR Controller

Shikata A., Sekimoto R., Yoshioka K., Kuroda T., Ishikuro H.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96-A （ 2 ） 443 - 452 2013年02月

ISSN  09168508

　概要を見る

This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flipflop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4V single power supply voltage. At 10 bit mode and 1V operation, up to 10MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

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An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator

Yoshioka K., Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

European Solid-State Circuits Conference    381 - 384 2012年12月

ISSN  19308833

　概要を見る

An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V. © 2012 IEEE.

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0.6-3.6 GHz wideband operation with high phase resolution on-chip network analyzer

Johari A.H., Ishikuro H.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS    539 - 542 2012年12月

　概要を見る

In this paper, we have shown the design of a wideband operation On-chip Network Analyzer (OCNA) in 45nm CMOS. Its maximum operation ranges from 0.6 ∼ 3.6 GHz with maximum phase resolution of 0.3 degree, and maximum power consumption of 3.2 mW/GHz in Cadence Spectre circuit simulation. The OCNA effective area is 0.072 mm2 which is the smallest compared to previous research group. The OCNA performance is assess by monitoring the Circuit-under-Test (CUT) frequency characteristics. The proposed OCNA successfully captures the waveform and also the CUT frequency characteristic. © 2012 IEEE.

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A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

Hiraku Y., Hayashi I., Chung H., Kuroda T., Ishikuro H.

Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC    33 - 36 2012年12月

　概要を見る

This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm2. © 2012 IEEE.

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A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating

Sekimoto R., Shikata A., Yoshioka K., Kuroda T., Ishikuro H.

Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC    161 - 164 2012年12月

　概要を見る

This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous operation and boosted self power gating are proposed to improve conversion accuracy and reduce static leakage power. Test chip fabricated in 40nm CMOS process has successfully reduced leakage power by 98% and it performs ENOB of 8.2bit and consumes only 0.65nW with 0.1kS/s at 0.5V. The power consumption is scalable up to 4MS/s and power supply range from 0.4 to 0.7V. The best figure of merit (FoM) of 5.2fJ/conversion-step was obtained with 20kS/s at 0.5V. © 2012 IEEE.

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A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with Costas-loop based synchronization scheme in 65nm CMOS

Liu L., Ishikuro H., Kuroda T.

Proceedings of the Custom Integrated Circuits Conference 2012年11月

ISSN  08865930

　概要を見る

A 100Mb/s 1.37mW impulse-radio ultra-wideband (IR-UWB) receiver with Costas-loop based frequency and phase synchronization scheme is developed in 65nm CMOS. This is the first analog-domain plesiochronous solution for IR-UWB communication in DC-960MHz band without the necessity of traditional analog-to-digital converter (ADC) and digital baseband for signal processing, thereby the receiver achieves the lowest energy of 13.7pJ/bit in state-of-the-art plesiochronous IR-UWB communication. © 2012 IEEE.

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A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and dicode partial-response channel transceivers

Kosuge A., Mizuhara W., Miura N., Taguchi M., Ishikuro H., Kuroda T.

Proceedings of the Custom Integrated Circuits Conference 2012年11月

ISSN  08865930

　概要を見る

A reduced-reflection multi-drop bus system using Dicode (1-D) partial response signaling transceiver is presented for the first time in the world. Directional couplers on transmission lines arranged with equi-energy distributing and exact impedance matched conditions allow the bus to reach to 12.5Gbps/link speed. The transmission line has 5-convex portions to form one side of a coupler where the transmission line width is adjusted to control the characteristic impedance of the coupling section, minimizing signal reflection from each section. Dicode partial-response signaling method with a half-rate architecture was used where a precoder is placed in the transmitter to make the signal best fit for the channel to eliminate inter symbol interference (ISI) where the test chip transmitter occupies 3,750 μm2 and the receiver occupies 750 μm2 with 90nm CMOS technology, consuming 40mA and 23mA respectively at the supply voltage of 1.2V. © 2012 IEEE.

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1-W 3.3-16.3-V boosting wireless power transfer circuits with vector summing power controller

Tomita K., Shinoda R., Kuroda T., Ishikuro H.

IEEE Journal of Solid-State Circuits 47 （ 11 ） 2576 - 2585 2012年09月

ISSN  00189200

　概要を見る

This paper presents SD-card-size wireless power transfer system for large-volume contactless memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the dc-dc converter or charge-pump circuit for data write operation into the flash memory chip. The proposed approach reduces the number of components and BOM cost and improves the total power efficiency. A vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18-μ m-CMOS with high voltage option. Voltage boost from 3.3 to 16.3 V and 1-W power transfer with 50% total efficiency have been successfully demonstrated, and the response time for the power control loop is shorter than 35 μs. © 2012 IEEE.

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Rotary coding for power reduction and S/N improvement in inductive-coupling data communication

Radecki A., Miura N., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 47 （ 11 ） 2643 - 2653 2012年09月

ISSN  00189200

　概要を見る

In this paper, we describe a noncontact inductive-coupling data transmission link employing rotary data encoding. A system using this data-transmission link is inherently insensitive to jitter introduced in the channel and consumes approximately 50% less power than previously reported solutions. The system is targeted for applications benefiting from simultaneous noncontact power and data transmission, such as wafer-level testing, memory card interfaces, and inter-strata data communication in 3-D integrated circuits. Functionality of the proposed link is verified experimentally with a test chip developed in an 0.18-μm CMOS process. In the second part of this paper, we introduce a design of a high-speed data transceiver using rotary coding. We demonstrate that, because of properties of the rotary coding, a simple transceiver without a PLL-based CDR circuit can operate at data rates limited only by characteristics of the physical channel. For performance optimization, we have developed a new family of ternary logic gates including latches, D-flip-flops, and multiplexers. © 2012 IEEE.

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A 0.025-0.45 W 60%-efficiency inductive-coupling power transceiver with 5-bit dual-frequency feedforward control for non-contact memory cards

Chung H., Radecki A., Miura N., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 47 （ 10 ） 2496 - 2504 2012年09月

ISSN  00189200

　概要を見る

A 0.025-0.45 W inductive-coupling power transceiver for non-contact memory applications is presented. To deal with sudden and large load variations and achieve high-efficiency, we propose a power transceiver with 5-bit feedforward control. Knowing that load patterns of a memory card have strong correlation with commands issued by a host, feedforward control is applied to minimize response times. To achieve 5-bit power levels, the proposed transceiver utilizes pulse-density modulation (PDM) and a multi-channel structure. Different operation frequencies are chosen for each channel to maximize power transfer efficiency. To further improve transceiver efficiency and enable high-speed operation, an active rectifier with a fast positive feedback is proposed. The test prototype demonstrates 40%-70% efficiency across all load conditions and 60% efficiency in average, which are over an order of magnitude improvements compared to prior arts. © 1966-2012 IEEE.

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Simultaneous 6-Gb/s data and 10-mW power transmission using nested clover coils for noncontact memory card

Radecki A., Yuan Y., Miura N., Aikawa I., Take Y., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 47 （ 10 ） 2484 - 2495 2012年08月

ISSN  00189200

　概要を見る

An inductive power and data transmission link for a noncontact memory card interface is reported. Nested clover coils improve signal-to-interference ratio and enable simultaneous power and data transmission. This capability is then used in the design of a closed-loop feedback system for improving power transfer efficiency. Interference cancellation mechanism is analyzed with both 3-D EM simulations and a newly developed compact model of coupled inductors. Performance of the proposed solutions was confirmed experimentally using a scaled-down stacked-chip prototype fabricated in a 65-nm CMOS process. Maximum data transmission rate is 6 Gb/s and the total power transfer efficiency is 5.2%-10.2% over a load resistance range of 0.1-2 k$\Omega$. © 1966-2012 IEEE.

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