論文 - 石黒　仁揮

A simplified path interference model in 2D multi-hop wireless power transfer system

Shibuya R., Kawajiri T., Ishikuro H.

ISAP 2016 - International Symposium on Antennas and Propagation    54 - 55 2017年01月

　概要を見る

This paper studies the multipath interference in a 2D multi-hop wireless power transfer system which uses magnetic resonance in two dimensional repeater array. By focusing on the current amplitude and phase in each repeaters, power combination from different path is discussed and simplified path interference model is proposed. The accuracy of the proposed simplified path interference model is compared with electromagnetic field simulation.

A Programmable δΣSAR-ADC with charge shuttling technique

Yamada K., Toyama Y., Ishikuro H.

ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things    51 - 52 2016年12月

　概要を見る

This paper presents an ADC with programmability between SAR-only mode and delta-sigma (δΣassisted mode. The ?assisted mode brings 1st order noise shaping for resolution enhancement. Proposed charge shuttling technique makes it possible to share a charge re-distribution capacitor array for DAC in SAR, feedback DAC, and integrator capacitor in δΣloop and improve the accuracy. The prototype ADC fabricated in 65- nm CMOS achieved SNDR of 44.35 dB at sampling rate of 32 MHz and power consumption of 0.55mW. The SNDR is improved to 62.9dB by δΣassisted mode when the signal bandwidth is 60 kHz.

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A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique

Gryta A., Suguro T., Ishikuro H.

2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016    275 - 278 2016年12月

　概要を見る

This paper presents a ΔΣ modulator with ring amplifiers to decrease the power consumption. The proposed ΔΣ modulator employs a technique of cutting-off the current of ring amplifiers after they are settled in each clock cycle. The optimum cutting-off timing can be determined by monitoring the output SNDR. The proposed 1-bit third-order ΔΣ modulator was designed in 65-nm CMOS process. From schematic-level circuit simulation, 76-dB SNDR was obtained at signal bandwidth of 1 MHz and clock frequency of 128 MHz. More than 40% percent of the power is saved at clock frequency of 128 MHz and power scalability is obtained.

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A 24 mW 5.7 Gbps dual frequency conversion demodulator for impulse radio with the first sidelobe

Kohira K., Kitazawa N., Ishikuro H.

IEICE Transactions on Electronics E99C （ 10 ） 1164 - 1173 2016年10月

ISSN  09168524

　概要を見る

This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.

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A wireless power transfer system with enhanced response and efficiency by fully-integrated fast-tracking wireless constant-idle-time control for implants

Huang C., Kawajiri T., Ishikuro H.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2016-September 2016年09月

　概要を見る

In this paper, a 13.56 MHz fully-integrated wireless power transfer system with wireless constant-idle-time control is proposed. The massive off-chip components or wire required for transmitter (TX) voltage regulation in previous works are eliminated. Both wireless and local regulations are achieved with enhanced transient performance and total efficiency, and reduced circuitry and system design complexity. Thanks to the proposed wireless constant-idle-time control technique, an instant load-transient response, and a peak total efficiency of 67.6% with up to 13.7% improvement are observed in measurements with meat between coils at a distance of 6mm.

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A Near-Optimum 13.56 MHz CMOS Active Rectifier with Circuit-Delay Real-Time Calibrations for High-Current Biomedical Implants

Huang C., Kawajiri T., Ishikuro H.

IEEE Journal of Solid-State Circuits 51 （ 8 ） 1797 - 1809 2016年08月

ISSN  00189200

　概要を見る

In this paper, a near-optimum active rectifier is proposed to achieve well-optimized power conversion efficiency (PCE) and voltage conversion ratio (VCR) under various process, voltage, temperature (PVT) and loading conditions. The near-optimum operation includes: eliminated reverse current loss and maximized conduction time achieved by the proposed sampling-based real-time calibrations with automatic circuit-delay compensation for both on- and off-time of active diodes considering PVT variations; and power stage optimizations with adaptive sizing over a wide loading range. The design is fabricated in TSMC 65 nm process with standard I/O devices. Measurement results show more than 36% and 17% improvement in PCE and VCR, respectively, by the proposed techniques. A peak PCE of 94.8% with an 80Ω loading, a peak VCR of 98.7% with 1 kΩ loading, and a maximum output power of 248.1 mW are achieved with 2.5 V input amplitude.

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Low power DT delta-sigma modulator with ring amplifier SC-integrator

Suguro T., Ishikuro H.

Proceedings - IEEE International Symposium on Circuits and Systems 2016-July   2006 - 2009 2016年07月

ISSN  02714310

　概要を見る

This paper presents a low power DT sigma-delta modulator for wide variety of sensor application using a ring amplifier for SC-integrator. The topology is a second order modulator with single-bit quantizer. Dead-zone effect of the ring amplifier in oversampling ADC is discussed. The fabricated test chip in 65nm CMOS process achieved SNDR of 62dB and 1MHz signal band at sampling frequency of 102.4MHz. The power consumption is 1mW and FoM is 483fJ/conv.step.

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Dynamic period switching of PRS-PWM with run-length limiting technique for spurious and ripple reduction in fast response wireless power transmission

Moroto T., Kawajiri T., Ishikuro H.

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC 2016-May   1802 - 1806 2016年05月

　概要を見る

In this paper, we propose a control method in a wireless power transmission that targets small battery-less devices. Dynamic period switching of PRS-PWM (Pseudo Random Sequence - Pulse Width Modulation) with run length limiting technique has been developed to break through the tradeoff between transient response speed, rectified voltage ripple, and spurious emission. Developed wireless power transmission system has achieved ripple reduction by 44%, response speed of 70μs, and spurious reduction by 15.6dB.

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A 12.5 Gbps CDR with differential to common converting edge detector for the wired and wireless serial link

Kohira K., Ishikuro H.

IEICE Transactions on Electronics E99C （ 4 ） 458 - 465 2016年04月

ISSN  09168524

　概要を見る

This paper introduces low-power and small area injectionlocking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2-V supply at 12.5 Gbps. The fabricated CDR achieved a BER lower than 10-12 and the recovered clock had an rms jitter of 0.87 ps. The CDR area is 0.165 mm2.

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An Inductively Powered Wireless Solid-State Drive System with Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories

Kosuge A., Hashiba J., Kawajiri T., Hasegawa S., Shidei T., Ishikuro H., Kuroda T., Takeuchi K.

IEEE Journal of Solid-State Circuits 51 （ 4 ） 1041 - 1050 2016年04月

ISSN  00189200

　概要を見る

A highly reliable wireless solid-state drive (SSD) system for future applications of large volume storage is presented. The wireless interface in the system consists of an inductively coupled power link with fast transmission power control and high-speed data links using transmission line couplers (TLCs). The wireless power link can deliver 1 W from the host to the SSD. The full duplex wireless data interface achieves raw data rate of 1.6 Gb/s. The reliability of the wireless interface is studied though simulation analysis and experiments. The error correction block for the NAND flash memory system can also correct errors in the wireless data links, allowing the requirements for the PHY layer to be relaxed. The error correction code is discussed, including optimization by analyzing the error bits on the wireless data links. The experimental results confirmed strong tolerance to the interference from the power link on the wireless data link, and the water proof property of both the data and power links.

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A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe

Kohira K., Kitazawa N., Ishikuro H.

IEEE Radio and Wireless Symposium, RWS 2016-March   10 - 12 2016年03月

ISSN  21642958

　概要を見る

This paper presents a modulation scheme of impulse radio which uses 1st sidelobe of transmitting NRZ baseband signal and implementation of dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that of BPSK modulation and does not require up-converter in the transmitter. The dual frequency conversion demodulator compensates the spectrum distortion caused by frequency response of circuits and channel. The fabricated demodulator test chip in 65nm CMOS achieved clock and data recovery at 5.5Gbps with power consumption of 24mW.

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A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver

Kosuge A., Okada A., Taguchi M., Ishikuro H., Kuroda T.

IEEE Transactions on Circuits and Systems I: Regular Papers 63 （ 2 ） 265 - 275 2016年02月

ISSN  15498328

　概要を見る

A 280 Mb/s non-contact in-vehicle LAN system using electromagnetic clip connectors is presented. The bidirectional transmission line coupler based electromagnetic clip connector, which can be used to make local area network connections similar to clips, suppresses the signal reflections on the bus enabling 280 Mb/s data rate which is 7 times faster than the state-of-the-art in-vehicle LAN transceiver. Since all modules are connected with the shortest distance, this connection system can reduce wire harness weight by 30%. Forward error correction is done by N-x Manchester encoding on the transmitter side and majority voting on the receiver side. High noise immunity is achieved through synchronous receiving by the digital clock recovery circuit which is robust against noise. Communication tests were conducted at 280 Mb/s with 10 transceivers fabricated in 65 nm CMOS technology connected by a 10 m unshielded twisted pair cable. Evaluation of the bit error rate and radiation spectrum confirmed that the ISO specifications concerning electromagnetic susceptibility and the CISPR ones concerning electromagnetic interference are satisfied.

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Shield effects of metal plate and mesh in wireless power delivery system

Hashiba J., Kawajiri T., Shibuya R., Ishikuro H.

2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings    235 - 237 2016年01月

　概要を見る

This paper presents the influence of metal sheet near the coils of inductively coupled wireless power delivery system. Experiments and electro-magnetic field simulation shows the influence of various kind of metal sheets and sheet positions on the power efficiency and peak frequency shift. The tradeoff between the power efficiency and shielding ability is also discussed.

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Wave monitor for glitch detection and skew adjusting in high-speed DAC

Tokonami K., Kohira K., Ishikuro H.

2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings    175 - 177 2016年01月

　概要を見る

In this paper, a high-speed current steering DAC with wave monitor circuit is proposed. Comparatorbased wave monitor circuit makes it possible to detect a glitch and adjust the skew of each bit digital signal. Fabricated test chip in 40nm-CMOS demonstrates the performance improvement by glitch detection and skew adjusting. At 1GS/sec, the fabricated DAC achieved ENOB of 5.17 bit and power consumption of 2.38mW.

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A Prototype SAW-Less LTE Transmitter with a High-Linearity Modulator Using BPF-Based I/Q Summing and a Triple-Layer Marchand Balun

Nakamura T., Kitazawa N., Kohira K., Ishikuro H.

IEEE Transactions on Microwave Theory and Techniques 63 （ 12 ） 4090 - 4097 2015年12月

ISSN  00189480

　概要を見る

A 65-nm CMOS-technology-based surface-acoustic-wave filterless transmitter (TX) for a long-term evolution (LTE) system was developed and performance tested. The TX incorporates both a passive quadrature modulator (QMOD) using bandpass filter (BPF)-based in-phase/quadrature (I/Q) signal summing and a small triple-layer Marchand balun. The passive operation and BPF-based I/Q summing, respectively, contribute to low noise performance and high input impedance (seen from the baseband signal), resulting in low receiver (RX) band noise and high linearity of the TX. The triple-layer Marchand balun contributes to the small area of the TX. A prototype LTE TX using the QMOD and the balun exhibits in-specification RX-band noise (<-161.6 dBc/Hz), a high output third-order intercept point (OIP3=20.5 dBm), and a small chip area (0.224 mm2).

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A near-optimum 13.56 MHz active rectifier with circuit-delay real-time calibrations for high-current biomedical implants

Huang C., Kawajiri T., Ishikuro H.

Proceedings of the Custom Integrated Circuits Conference 2015-November 2015年11月

ISSN  08865930

　概要を見る

This paper presents a 13.56MHz active rectifier with enhanced power conversion efficiency (PCE) and voltage conversion ratio (VCR) for high-current biomedical implants. Near-optimum operation with compensated circuit delays is achieved by the proposed real-time NMOS on/off calibrations, which minimize the reverse current and maximize the transistor conduction time under various process, voltage, temperature and loading conditions. Adaptive sizing (AS) is also introduced to optimize the PCE over a wide loading range. Measurements in TSMC 65nm show more than 36% and 17% improvement in PCE and VCR, respectively, by the proposed techniques. With 2.5V input amplitude, the rectifier achieves a peak PCE of 94.8% with an 80Ω loading, a peak VCR of 98.7% with a 1kΩ loading, and a maximum output power of 248.1mW.

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A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration

Tanaka K., Saito R., Ishikuro H.

European Solid-State Circuits Conference 2015-October   327 - 330 2015年10月

ISSN  19308833

　概要を見る

A 6-bit high-speed and low-power pipelined binary-search ADC is presented. Over GHz conversion rate is achieved by passive pipeline operation without amplifier. 'Memory effect' caused by charge sharing in the passive pipeline operation is cancelled by charge reset and flatness of frequency response of the converter is improved. Memory effect canceller also makes it easy to calibrate reference voltage to each comparator and to enhance SNDR. The prototype ADC fabricated in 40nm-CMOS achieved 29.21 dB SNDR with 1.6 GS/s at supply voltage of 0.9 V. The ADC achieved a FoM of 84.1 fJ/conv.step.

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A low EMI SIDO wireless power transfer system with 10μsec response time

Kawajiri T., Moroto T., Ishikuro H.

European Solid-State Circuits Conference 2015-October   253 - 256 2015年10月

ISSN  19308833

　概要を見る

This paper describes a system of single-inductor-dual-output (SIDO) wireless power delivery for mobile applications. By updating control signal in the feedback loop by every switching clock cycle, fast tracking to the load change is realized while spurious emission is suppressed by using pseudorandom-sequence PWM (PRS-PWM). Transmitter and receiver chips were fabricated in 0.18μm CMOS process and mounted on the wireless power transfer test board. The system achieved response time shorter than 10μsec. Two output voltages are regulated at 8V and 16V, and maximum efficiency of 41% was achieved when the total output power is 500mW.

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I/Q mismatch compensation ΔΣ modulator using ternary capacitor rotation technique

Yonekura M., Ishikuro H.

European Solid-State Circuits Conference 2015-October   229 - 232 2015年10月

ISSN  19308833

　概要を見る

This paper presents a new technique to suppress I/Q mismatch and decrease power consumption and chip area. The proposed technique uses two methods for all integrators and DAC in the modulator which are main sources of the mismatch and power. One is proposed ternary capacitor rotation technique to compensate the I/Q mismatch and achieve high image-rejection. The other is amplifier-sharing technique to reduce the number of amplifier and power consumption. The third-order 1bit delta-sigma modulator was designed in 65nm CMOS process, and fabricated test chip achieved an image-rejection ratio (IRR) of higher than 70dB throughout a 1MHz bandwidth. The overall power consumption is 12.7mW including I/Q channels.

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Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory

Kosuge A., Hashiba J., Kawajiri T., Hasegawa S., Shidei T., Ishikuro H., Kuroda T., Takeuchi K.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2015-August   C128 - C129 2015年08月

　概要を見る

This paper presents a wireless solid-state drive (SSD) system for future applications of large volume storage in mobile devices or data centers. The wireless interface in the developed system consists of an inductive-coupling power link with a fast transmitting power control and high-speed data links with transmission line couplers (TLCs). The wireless power link can deliver 1W from the host side to the SSD side. The full duplex wireless data interface achieved raw data rate of 1.6Gbps/link. The error correction block for NAND flash memory system can also correct the error in wireless data links. The data link has tolerance to the interference from the power link, and both the data and power links show the waterproof property of the system.

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