研究者詳細 - 石黒　仁揮

論文 - 石黒　仁揮

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Analysis and design of an 8.5-Gb/s/Link multi-drop bus using energy-equipartitioned transmission line couplers

Kosuge A., Ishizuka S., Taguchi M., Ishikuro H., Kuroda T.

IEEE Transactions on Circuits and Systems I: Regular Papers 62 （ 8 ） 2122 - 2131 2015年08月

ISSN 15498328

An 8.5-Gb/s/link non-contact multi-drop bus is presented. The signal reflections that limit the data rates of conventional multi-drop bus interfaces are dramatically reduced by using transmission line couplers at each signal branching point. As an energy-equipartitioned technique provides the same signal level to every port, wider receiver margin is achieved. The data rate is improved by 1.8 times compared to the most advanced multi-drop bus interface. The theoretical analysis and design techniques of energy-equipartitioned transmission line couplers are discussed in this paper. The design methodologies were verified through simulations performed by using a full-3D EM-simulator and experiments with FR4 test boards. Due to the low-cut characteristics of the couplers, the low-frequency components are cut off so that differentiated pulses arrive at the receiver input point. A receiver detects and recovers the received pulses by integrating them using hysteresis characteristics. The design techniques of the transceiver for the transmission line couplers are also discussed in this paper. The proposed methods were verified by using a test chip fabricated with a 90-nm CMOS process. Experiments with a prototype of an eight-drop multi-drop bus system confirmed BER < 10-14 at a data rate of 8.5-Gb/s/link. The measured timing margin at the far-end module was 0.49-UI at a BER of 10-12. The power consumption of the transceiver was 75.6-mW at a supply voltage of 1.2-V.

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Fence loaded antenna coupler for high-band UWB with steep cutoff characteristics

Saito I., Kohira K., Ishikuro H.

IEEE Radio and Wireless Symposium, RWS 2015-June （ June ） 56 - 58 2015年06月

ISSN 21642958

This paper presents a fence-type virtual short stub loaded UWB antenna coupler which has broadband and steep cutoff characteristics at both the lower and upper cutoff frequency. The fence-type short stub consists of a top and bottom metal layers of FR4 substrate and Through Holes (THs) connecting layers. Thanks to this geometry, resonance and anti-resonance occur at various frequencies in several signal paths. The size of the antenna is 1cm × 1cm. The simulation result of coupling coefficient parameter (S21) is higher than -20dB from 6.2GHz to 10.4GHz (4.2GHz bandwidth) when the distance between two couplers is 1cm.

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Intermittently operating RF frontend with 5ns startup time for 10Gbps proximity wireless communication

Kitazawa N., Kohira K., Ishikuro H.

2015 IEEE 15th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2015 24 - 26 2015年06月

This paper presents intermittently operating RF frontend for proximity wireless communication with wireless power supply. To realize power scalability of the RF frontend, intermittent operation is performed by switching the bias of the amplifier. Quick startup circuit is proposed to accelerate the charging time to a decoupling capacitor. The fabricated test chip in 65nm CMOS occupies 0.075mm2. The 3dB bandwidth of amplifier ranges from 1.8GHz to 7.2GHz and current consumption is 8mA. The startup time of the circuit is 5ns.

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Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC

Yoshioka K., Saito R., Danjo T., Tsukamoto S., Ishikuro H.

IEEE Journal of Solid-State Circuits 50 （ 4 ） 932 - 945 2015年04月

ISSN 00189200

Dynamic Architecture and Frequency Scaling (DAFS) is shown to realize superlinear power scaling in high-speed analog-to-digital converters (ADCs). To achieve both high-speed operation and low power consumption, the ADC architecture is reconfigured between binary search and flash every clock cycle, relying on the conversion delay. The proposed binary search/flash architecture reconfigurable ADC can be implemented with only a small modification to conventional binary search ADCs. By live configuring, the flash operation is adaptively performed when an excess delay is detected. DAFS not only significantly improves the power scaling but also compensates for transistor speed shifts due to process, voltage and temperature (PVT) variations. Therefore, DAFS can be used to improve the design margin of high-speed ADCs. A prototype subranging ADC fabricated in 65 nm CMOS technology operates up to 1220 MS/s and achieves an SNDR of 36.2 dB with a Nyquist input frequency. DAFS is active between 820-1220 MS/s and achieves peak power reduction of 30%, when compared with the power scaling when DAFS is disabled. A peak FoM of 85 fJ/conv. was obtained at 820 MS/s, which is nearly a twofold improvement over that of previously reported subranging ADCs.

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Dual-output wireless power delivery system for small size large volume wireless memory card

Hashiba J., Kawajiri T., Hasegawa Y., Ishikuro H.

20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 32 - 33 2015年03月

A single-inductor dual-output wireless power delivery system for small size battery-less NAND flash memory card is presented. The power delivery system uses two rectifiers connected to a single inductor which is synchronously switched by pseudo-random-sequence PWM signal with induced AC voltage. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 % and maximum total transmitting power of 0.5 W. The test chips were designed and fabricated using 0.18um-CMOS with high-voltage LDMOS option.

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An 8 bit 0.3-0.8 v 0.2-40 MS/s 2-bit/Step SAR ADC with successively activated threshold configuring comparators in 40 nm CMOS

Yoshioka K., Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 （ 2 ） 356 - 368 2015年02月

ISSN 10638210

A 0.3-0.8 V low-power 2-bit/step asynchronous successive approximation register analog-to-digital converter (ADC) is presented. A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. Simple digital calibration is enabled by generating the reference internally. The prototype ADC fabricated in a 40 nm CMOS achieved a 44.3 dB signal-to-noise-plus-distortion ratio (SNDR) with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 4.8 fJ/conv-step at 0.4 V and operates down to 0.3 V.

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A 13b SAR ADC with eye-opening VCO based comparator

Yoshioka K., Ishikuro H.

European Solid-State Circuits Conference 411 - 414 2014年10月

ISSN 19308833

A low-power and high accuracy comparator based on voltage controlled ring-oscillator (VCO) is presented. By using the dead zone of phase detector effectively, the VCO comparator automatically changes its noise level depending on the input voltage level (Δvin). When Δvin is large, the comparator operates as a low-power delay-line based comparator. On the other hand, when Δvin is small, the VCO is enabled and eye is opened during the oscillation. This suppress input referred noise and enables accurate conversion. The number of oscillation cycle for one comparison is inversely proportional to Δvin and adaptive noise reduction is realized. The VCO comparator does not require any sort of tuning. A 13b SAR ADC with proposed VCO based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves SNDR 66 dB at 1 MS/s with FoM of 29fJ/conv.-step.

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A SAW-less LTE transmitter with high-linearity modulator using BPF-based I/Q summing

Nakamura T., Kitazawa N., Kohira K., Ishikuro H.

European Solid-State Circuits Conference 387 - 390 2014年10月

ISSN 19308833

A SAW-filter-less LTE transmitter based on 65-nm CMOS technology, incorporating a passive quadrature modulator (QMOD) with band-pass-filter (BPF) I/Q summing technique, was developed. The passive operation and the BPF I/Q summing technique, respectively, contribute to low noise performance and high input impedance seen from baseband signal, resulting in low receiver-band noise and high linearity of the transmitter. A transmitter using the QMOD exhibits both inspecification receiver-band noise (<-156 dBc/Hz) and high output 3rd intercept point (OIP3 = 20.6 dBm).

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An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique

Yoshioka K., Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 31 - 32 2014年03月

An extremely low power and area efficient threshold configuring ADC (TC-ADC) for time interleaved ADC is proposed. The threshold configuring comparator (TCC) performs a binary search. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC. © 2014 IEEE.

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A 0.15-mm-thick noncontact connector for mipi using a vertical directional coupler

Kosuge A., Mizuhara W., Shidei T., Takeya T., Miura N., Taguchi M., Ishikuro H., Kuroda T.

IEEE Journal of Solid-State Circuits 49 （ 1 ） 223 - 231 2014年01月

ISSN 00189200

A noncontact and housing-less thin-thick connecting method was developed for mobile industry processor interface (MIPI) applications. This paper describes the world's first 0.15-mm-thick connector using a vertical directional coupler (VDC) which enables simultaneous two-link communication with one coupler without fatal performance degradation. We have analyzed the conditions for isolating two links in a coupler, and the design method is discussed. A fully balanced pulse transmitter implemented in 90-nm CMOS technology significantly suppressed electromagnetic interference (EMI), which agrees well with MIPI requirements. An experimental liquid crystal display interface system reached a maximum data rate of 2.3 Gb/s/link at a bit error rate of less than 10-12 and a power consumption of 1.47~pJ/b. The timing margin of single link was 320 ps (=64% U.I.) and of two links was 305 ps (= 61% U.I.) at 2.0 Gb/s. © 2013 IEEE.

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7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Yoshioka K., Saito R., Danjo T., Tsukamoto S., Ishikuro H.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2014年

Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs. © 2014 IEEE.

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An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%

Kosuge A., Ishizuka S., Liu L., Okada A., Taguchi M., Ishikuro H., Kuroda T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference 57 496 - 497 2014年

ISSN 01936530

Heavier wire harnesses decrease the fuel efficiency of vehicles. The number of wires has increased sharply with presently over one hundred electronic control units (ECUs). Connectors also add to the weight (Fig. 30.6.1(a)). The connectors used in vehicles occupy a considerable space because heavy protection is required against transmission interruption caused by vibration. In addition, a significant number of wires are used together in a junction box to increase total wire length (e.g. 55L when 10 ECUs are connected) and thus weight increases accordingly. © 2014 IEEE.

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A low power, area efficient frequency acquisition circuit with array oscillator for pulse-based inductive-coupling transceiver

Jyo T., Kuroda T., Ishikuro H.

Asia-Pacific Microwave Conference Proceedings, APMC 95 - 97 2013年12月

This paper presents a low power, small area Frequency Acquisition Circuit (FAC) for a pulse-based inductive coupling transceiver. A multiphase clock which is generated in array oscillator is used to control the pulse width. To solve the problem of oscillation frequency change by PVT variation, FAC is proposed to control the oscillation frequency. FAC uses the multiphase clock generated in array oscillator. By sharing the multiphase clock for both the pulse generation and the frequency control, low power and small area can be achieved. The fabricated test chip in 65nm CMOS occupies 0.045mm2. The array oscillator generates 1GHz, 20 phase clocks at the supply voltage of 0.8V. The RMS of cycle-to-cycle jitter is 3.3ps and the power consumption is 1.1mW. © 2013 IEEE.

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Single-inductor-dual-output wireless power receiver with synchronous pseudo-random-sequence PWM switched rectifiers

Hasegawa Y., Tomita K., Ishihara S., Honma R., Ishikuro H.

Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 261 - 264 2013年12月

A single-inductor dual-output wireless power delivery receiver for small size battery-less applications is presented. The power delivery system uses two rectifiers connected to a receiving inductor switched by pseudo-random-sequence PWM (PRS-PWM) signal synchronized with induced AC voltage in the receiving inductor. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 %. The maximum total transmitting power is 0.5 W. The test chip was designed and fabricated using 0.18um-CMOS with high-voltage (32V) LDMOS option. © 2013 IEEE.

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0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Nomura M., Muramatsu A., Takeno H., Hattori S., Ogawa D., Nasu M., Hirairi K., Kumashiro S., Moriwaki S., Yamamoto Y., Miyano S., Hiraku Y., Hayashi I., Yoshioka K., Shikata A., Ishikuro H., Ahn M., Okuma Y., Zhang X., Ryu Y., Ishida K., Takamiya M., Kuroda T., Shinohara H., Sakurai T.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2013年09月

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%. © 2013 JSAP.

A 0.0058mm<sup>2</sup> 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique

Yoshioka K., Shikata A., Sekimoto R., Kuroda T., Ishikuro H.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2013年09月

An extremely low power and area efficient threshold configuring ADC (TC-ADC) is proposed. The threshold configuring comparator (TCC) performs a binary search and only 1b-DAC is required. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC. © 2013 JSAP.

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Digest of Technical Papers - Symposium on VLSI Technology 2013年09月

ISSN 07431562

A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL

Urano Y., Yun W., Kuroda T., Ishikuro H.

Proceedings - IEEE International Symposium on Circuits and Systems 1576 - 1579 2013年09月

ISSN 02714310

This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2. © 2013 IEEE.

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A 0.7V intermittently operating LNA with optimal on-time controller for pulse-based inductive-coupling transceiver

Jyo T., Kuroda T., Ishikuro H.

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium 21 - 24 2013年09月

ISSN 15292517

This paper presents a low-power LNA for a inductive-coupling tranceiver. Intermittently operating technique to turn on LNA only at the moment when the pulse signal appears is used to reduce power consumption. To optimally control the On-time of LNA, pulse width detector based on self-oversampling TDC is used and compensate the PVT variations of On-time witdh and of pulse signal width. The fabricated test chip in 65nm CMOS occupies 0.06mm2 and achieved the intermittently operating frequency at the range from 60 to 400Mbps. The power consumption is 0.42mW at 400Mbps and the supply voltage of 0.7V which corresponds to 37% power reduction from the power consumption without optimal On-Time Controller. © 2013 IEEE.

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A voltage scaling 0.25-1.8 v delta-sigma modulator with inverter-opamp self-configuring amplifier

Yoshioka K., Toyama Y., Jyo T., Ishikuro H.

Proceedings - IEEE International Symposium on Circuits and Systems 809 - 812 2013年09月

ISSN 02714310

A 2nd order discrete time (DT) ΔΣ modulator with very wide supply voltage range of 0.25-1.8 V is presented. An inverter-opamp self-configuring amplifier (IOSA) is proposed with sufficient gain through sub-threshold to strong inversion region. The amplifier senses the supply voltage and automatically configures either to operate as an inverter or an opamp. The prototype ADC fabricated in 180nm CMOS achieved SNDR of 53dB at a supply voltage of 0.3V and a best FoM of 0.09 pJ/step. At 1.8 V supply the modulator achieves SNDR 61dB and operates down to 0.25V. © 2013 IEEE.

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