Papers - Amano, Hideharu
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Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units
Zhao Lei and Daisuke Ilebuchi and Kimiyoshi Usami and Mitaro Namiki and Masaaki Kondo and Hiroshi Nakamura and Hideharu Amano
IPSJ Trans. on System LSI Design Methodology (IPSJ) 4 ( 0 ) 182-192 2011.04
Research paper (conference, symposium, etc.), Joint Work
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Performace, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power Gating Routers for CMPs
Hiroki Matsutani and Michihiro Koibuchi and Daisuke Ikebuchi and Kimiyoshi Usami and Hiroshi Nakamura and Hideharu Amano
IEEE Trans. on Computer-Aided Design of Integrated Circuits and systems (IEEE) 30 ( 4 ) 520-534 2011.04
Research paper (conference, symposium, etc.), Joint Work, Accepted
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Design and Implementation of Echo Instructions for an Embedded Processor
Karaduman Arda and Stubdal Iver and Hideharu Amano
IPSJ Trans. on System LSI Design Methodology (IPSJ) 4 ( 0 ) 222-231 2011.04
Research paper (conference, symposium, etc.), Joint Work
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A Switch-Tagged Routing Methodology for PC Clusters with VLAN Etnernet
MICHIHIRO KOIBUCHI, TOMOHIRO OTSUKA, TOMOHIRO KUDOH, AMANO HIDEHARU
IEEE Transactions on Parallel and Distributed Systems 22 ( 2 ) 231-244 2011.02
Research paper (conference, symposium, etc.), Joint Work, Accepted
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An Analytical Network Performance Model for SIMD Processor CSX600 Interconnects
Y.Nishikawa} and {M.Koibuchi} and {M.Yoshimi} and {K.Miura} and {H.Amano}AMANO
Journal of Systems Architecture 57 ( 1 ) 146‐159 2011.01
Research paper (conference, symposium, etc.), Joint Work, Accepted
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Ｄｕａｌ－Ｖｔｈセルの利用による動的リコンフィギャラブルプロセッサのリーク電力削減手法
AMANO HIDEHARU
電子情報通信学会論文誌 Ｊ９４－Ｄ ( 1 ) 301‐311 2011.01
Research paper (conference, symposium, etc.), Joint Work, Accepted
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A Leakage Efficient Data TLB design for Embedded Processors
Zhao Lei and Hui Xu and Daisuke Ikebuchi and Tetsuya Sunata and Mitaro Namiki and Hideharu Amano
IEICE Trans. Inf.& Syst. Ｅ９４－Ｅ ( 1 ) 51‐59 2011.01
Research paper (conference, symposium, etc.), Joint Work, Accepted
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動的リコンフィギャラブルデバイスにおけるデータパスコンフィギュレーションを用いた構成情報時間削減手法の提案
AMANO HIDEHARU
電子情報通信学会論文誌 Ｊ９３－Ｄ ( 12 ) 2579‐2586 2010.12
Research paper (conference, symposium, etc.), Joint Work, Accepted
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ＣＭＰにおけるオンチップルータの細粒度パワーゲーティングの評価
AMANO HIDEHARU
情報処理学会論文誌：コンピューティングシステム 3 ( 3 ) 100‐112 2010.09
Research paper (conference, symposium, etc.), Joint Work, Accepted
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単フリット、単サイクルルータを用いたＮｏＣ向け非最短完全適応型ルーティング
AMANO HIDEHARU
情報処理学会論文誌：コンピューティングシステム 3 ( 3 ) 88‐99 2010.09
Research paper (conference, symposium, etc.), Joint Work, Accepted
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MIPS R3000プロセッサにおける細粒度動的スリープ制御の実装と評価
AMANO HIDEHARU
電子情報通信学会論文誌 Ｊ９３－Ｄ ( 6 ) 920‐930 2010.06
Research paper (conference, symposium, etc.), Joint Work, Accepted
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動的リコンフィギャラブルデバイスにおける構成情報配送のためのマルチキャスト手法の検討
AMANO HIDEHARU
電子情報通信学会論文誌 J92-D ( 12 ) 2185-2194 2009.12
Research paper (conference, symposium, etc.), Joint Work, Accepted
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動的リコンフィギャラブルデバイスにおける電力分析と低電力化手法の検討
AMANO HIDEHARU
電子情報通信学会論文誌 (電子情報通信学会論文誌) J92-D ( 10 ) 1763-1771 2009.10
Research paper (conference, symposium, etc.), Joint Work, Accepted
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パイプラインステージ統合による省電力・可変パイプラインルータに関する研究
AMANO HIDEHARU
情報処理学会論文誌コンピューティングシステム 2 ( 3 ) 71-82 2009.09
Research paper (conference, symposium, etc.), Joint Work, Accepted
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低遅延オンチップネットワークのための予測ルータの評価
AMANO HIDEHARU
情報処理学会論文誌コンピューティングシステム 2 ( 3 ) 26-38 2009.09
Research paper (scientific journal), Joint Work, Accepted
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Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network
HIROKI MATSUTANI, MICHIHIRO KOIBUCHI, YUTAKA YAMADA, D.Frank Hsu, AMANO HIDEHARU
IEEE Transaction on Paralel and Distributed Systems (IEEE) 20 ( 8 ) 1126-1141 2009.08
Research paper (conference, symposium, etc.), Joint Work, Accepted
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A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, AMANO HIDEHARU
IEICE Transaction on Information and Systems (IEICE) E92-D ( 4 ) 575-583 2009.04
Research paper (conference, symposium, etc.), Joint Work, Accepted
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DIMMスロット搭載型ネットワークインタフェースDIMMnet-Iとその高バンド幅通信機構BOTF
田邊、山本、濱田、中條、工藤、天野
情報処理学会論文誌HPS 43 ( 4 ) 866－878 2002.04
Research paper (scientific journal), Single Work
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L-turn routing: An Adaptive Routing in Irregular Networks
M.Koibuchi, A.Funahashi, A.Jouraku, H.Amano,
International Conference on Parallel Processing 374-383 2001.09
Research paper (conference, symposium, etc.), Joint Work, Accepted
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Recursive Diagonal Torus: an interconnection network for massively parallel computers
Y．Yang，A．Funahashi，A．Jouraku，H．Nishi，H．Amano，Ｔ．Sueyoshi
IEEE Trans. on Parallel and Distributed Systems (IEEE.Trans．on Parallel and Distributed Processing) 12 ( 7 ) 701-715 2001.07
Research paper (conference, symposium, etc.), Joint Work