Details of a Researcher - Amano, Hideharu

Papers - Amano, Hideharu

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RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA

Wei K., Kuno Y., Arai M., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 1 - 9 2022.06

Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-programmable gate array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation running on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the original design (libSGM), when working on the Tegra X2 GPU, RT-libSGM runs 2 × faster at a lower energy cost.

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Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning

Kojima T., Ohwada A., Amano H.

IEEE Transactions on Parallel and Distributed Systems (IEEE Transactions on Parallel and Distributed Systems) 33 ( 5 ) 1213 - 1230 2022.05

ISSN 10459219

Coarse-grained reconfigurable architectures (CGRAs) provide high energy efficiency with word-level programmability rather than bit-level ones such as FPGAs. The coarser reconfigurability brings about higher energy efficiency and reduces the complexity of compiler tasks compared to the FPGAs. However, application mapping process for CGRAs is still time-consuming. When the compiler tries to map a large and complicated application data-flow-graph(DFG) onto the reconfigurable fabric, it tends to result in inefficient resource use or to fail in mapping. In case of failure, the compiler must divide it into several sub-DFGs and goes back to the same flow. In this work, we propose a novel partitioning method based on a genetic algorithm to eliminate the unmappable DFGs and improve the mapping quality. In order not to generate unmappable sub-DFGs, we also propose an estimation model which predicts the mappability and resource requirements using a DGCNN (Deep Graph Convolutional Neural Network). The genetic algorithm with this model can seek the most resource-efficient mapping without the back-end mapping process. Our model can predict the mappability with more than 98% accuracy and resource usage with a negligible error for two studied CGRAs. Besides, the proposed partitioning method demonstrates 53-75% of memory saving, 1.28-1.39x higher throughput, and better mapping quality over three comparative approaches.

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A traffic-aware memory-cube network using bypassing

Shikama Y., Kawano R., Matsutani H., Amano H., Nagasaka Y., Fukumoto N., Koibuchi M.

Microprocessors and Microsystems (Microprocessors and Microsystems) 90 2022.04

ISSN 01419331

Three-dimensional stack memory which provides both high-bandwidth access and large capacity is a promising technology for next-generation computer systems. While a large number of memory cubes increase the aggregate memory capacity, the communication latency and power consumption increase significantly owing to its low-radix large-diameter packet network. In this context, we propose a memory-cube network called Diagonal Memory Network (DMN). A diagonal network topology, its floor layout, and its lightweight router were designed for low-latency and low-voltage memory-read communication. DMN routing efficiently avoids deadlocks of packets, although it allows each packet transmitted to a processor to use both bypassing and original datapaths. Our evaluation results show that the DMN router decreases the use of hardware resources by more than 31% compared with a conventional virtual channel router. The DMN router reduces energy consumption by 13% and 67% to transit a packet along with the original datapath and bypassing datapath, respectively. Furthermore, using flit-level discrete event simulation, a DMN topology achieves high throughput and latency that is lower than that of existing network topologies using conventional packet routers.

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Body Bias Control on a CGRA based on Convex Optimization

Kojima T., Okuhara H., Kondo M., Amano H.

25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022 - Proceedings (25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022 - Proceedings) 2022

Body biasing is one of the critical techniques to realize more energy-efficient computing with reconfigurable devices, such as Coarse-Grained Reconfigurable Architectures (CGRAs). Its benefit depends on the control granularity, whereas fine-grained control makes it challenging to find the best body bias voltage for each domain due to the complexity of the optimization problem. This work reformulates the optimization problem and introduces continuous relaxation to solve it faster than previous work. Experimental result shows the proposed method can solve the problem within 0.5 sec for all benchmarks in any conditions and demonstrates up to 5.65x speed-up compared to the previous method with negligible loss of accuracy.

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An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings

Ohwada A., Kojima T., Amano H.

Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022 (Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022) 1 - 9 2022

In recent years, IoT devices have become widespread, and energy-efficient coarse-grained reconfigurable architectures (CGRAs) have attracted attention. CGRAs comprise several processing units called processing elements (PEs) arranged in a two-dimensional array. The operations of PEs and the interconnections between them are adaptively changed depending on a target application, and this contributes to a higher energy efficiency compared to general-purpose processors. The application kernel executed on CGRAs is represented as a data flow graph (DFG), and CGRA compilers are responsible for mapping the DFG onto the PE array. Thus, mapping algorithms significantly influence the performance and power efficiency of CGRAs as well as the compile time. This paper proposes POCOCO, a compiler framework for CGRAs that can use pre-optimized subgraph mappings. This contributes to reducing the compiler optimization task. To leverage the subgraph mappings, we extend an existing mapping method based on a genetic algorithm. Experiments on three architectures demonstrated that the proposed method reduces the optimization time by 48%, on an average, for the best case of the three architectures.

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Power Analysis of Directly-connected FPGA Clusters

Iizuka K., Takagi H., Kamei A., Hironaka K., Amano H.

Although low power consumption is a significant advantage of FPGA clusters, almost no power analyses with real systems have been reported. This study reports the detailed power consumption analyses of two FPGA clusters, namely, M-KUBOS and FiC, with power measurement tools and real applications. In both clusters, the type of logic design shells determines the base power consumption. For building clusters, the power for node communication links is mainly determined by the number of activated links and not influenced by the number of actually used links. Therefore, applying the link aggregation technique does not affect the power consumption. Increasing the clock frequency of the application logic mildly increases the power consumption. The obtained results suggest that the best way to reduce the total power consumption of an FPGA cluster and improve its performance is to use the minimum number of links for the application, apply link aggregation, and aggressively increase the clock frequency.

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Power Consumption Reduction Method and Edge Offload Server for Multiple Robots

Natsuho S., Ohkawa T., Amano H., Sugaya M.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)) 12990 LNCS 1 - 19 2022

ISSN 03029743

There are emerging services for the transports and nursing with multiple robots has become more familiar to our society. Considering the increasing demand for automatic multiple robotic services, it appears the research into automatic multiple robotic services is not satisfactory. Specifically, the issues of power consumption of these robots, and its potential reduction have not been sufficiently discussed. In this research, we propose a method and system to reduce the aggregated power consumption of multiple robots by modelling the characteristics of the hardware and service of each robot. We firstly discuss the prediction model of the robot and improve the formula with consideration of its use in a wide range of situations. Then, we achieve the objective of reducing the aggregate power consumption of multiple robots, using consumption logs and re-allocating tasks of them based on the power consumption prediction model of the individual robot. We propose the design and develop a system using ROS (Robot Operating System) asynchronous server to collect the data from the robots, and make the prediction model for each robot, and reallocate tasks based on the findings of the optimized combination on the server. Through the evaluation of the design and implementation with the proposed system and the actual robot Zoom (GR-PEACH + Rasberry pi), we achieve an average power reduction effect of 14%. In addition, by offloading high-load processing to an edge server configured with FPGA instead the Intel Core i7 performance computer, we achieved and increase in processing speed of up to about 70 times.

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Analytical performance estimation for large-scale reconfigurable dataflow platforms

Yasudo R., Coutinho J.G.F., Varbanescu A.L., Luk W., Amano H., Becker T., Guo C.

ACM Transactions on Reconfigurable Technology and Systems (ACM Transactions on Reconfigurable Technology and Systems) 14 ( 3 ) 2021.09

ISSN 19367406

Next-generation high-performance computing platforms will handle extreme data- and compute-intensive problems that are intractable with today's technology. A promising path in achieving the next leap in high-performance computing is to embrace heterogeneity and specialised computing in the form of reconfigurable accelerators such as FPGAs, which have been shown to speed up compute-intensive tasks with reduced power consumption. However, assessing the feasibility of large-scale heterogeneous systems requires fast and accurate performance prediction. This article proposes Performance Estimation for Reconfigurable Kernels and Systems (PERKS), a novel performance estimation framework for reconfigurable dataflow platforms. PERKS makes use of an analytical model with machine and application parameters for predicting the performance of multi-accelerator systems and detecting their bottlenecks. Model calibration is automatic, making the model flexible and usable for different machine configurations and applications, including hypothetical ones. Our experimental results show that PERKS can predict the performance of current workloads on reconfigurable dataflow platforms with an accuracy above 91%. The results also illustrate how the modelling scales to large workloads, and how performance impact of architectural features can be estimated in seconds.

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A programming environment for multi-FPGA systems based on CyberWorkBench: An integrated design tool

Suzuki H., Takahashi W., Wakabayashi K., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 2021.06

This paper proposes a multi-FPGA programming environment based on NEC's integrated design tool CyberWorkBench (CWB) for a multi-FPGA system FiC (Flow-in-Cloud). Programmers describe their program in SystemC as small modules connected with FIFO channels, then verify the operation with the behavioral simulation considering parallel execution. After the high-level synthesis (HLS) is done with CWB, modules distributed to each board are decided, and the interface module is inserted. The cycle accurate simulation is applied to ensure the operation and estimate the performance. Finally, generated Verilog HDL code for each board is implemented with Xilinx's Vivado just like the traditional design and configuration is obtained. As an example, a simple convolutional neural network LeNet is described and implemented on a real system using the tool. Although the cycle accurate simulation takes 105.34sec, the estimated cycles are only 2.2% difference from the real boards execution result. Since the example CNN LeNet is too small, it can be implemented into a single board with a traditional design tool. However, considering the pipeline execution, parallel execution with two boards can distribute the input and output into different FPGAs, and relax the bottleneck.

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GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph

Kawano R., Matsutani H., Koibuchi M., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 51 - 55 2021.06

The design of the network topology of a large-scale parallel computer system can be represented as an order/degree problem in the graph theory. To solve the order/degree problem, we have to obtain all-pairs-shortest-path (APSP) for the graph. A conventional APSP algorithm for GPUs is based on the adjacency matrix (ADJ-APSP). When focusing on low-degree and unweighted graphs, most of the matrix elements are zero in the first few iterations of the algorithm. We will further speed up the APSP algorithm by treating the adjacency matrix as a sparse matrix in the first iterations of the algorithm. Evaluation results show that our proposed algorithm on a single GPU (NVIDIA GeForce RTX 3080) reduces the execution time by up to 32.7 % compared to the conventional algorithm.

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Implementing VTA, a tensor accelerator on Flow-in-Cloud

Hironaka K., Iizuka K., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 46 - 50 2021.06

A multi-FPGA system Flow-in-Cloud (FiC) consists of nodes with a mid-class cost-efficient FPGA and Raspberry Pi3B connected with high speed serial links. It aims to implement a large scale AI applications which is difficult to be implemented on a single FPGA by dividing the target into a number of boards. On the other hand, overlay domain specific architecture receives attention for implementing complicated application programs easily on the FPGA. Here, we focus on an open-source AI compiler framework Apache TVM, and its implementation for FPGA, VTA(Versatile Tensor Accelerator). In order to use FiC through the TVM, we implemented it on FiC and executed the ResNet-18 inference benchmark. The preliminary evaluation results showed that VTA on FiC-SW achieved up to 10 times performance compared to the execution on ARM Cortex-A54 software.

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Recovering faulty non-volatile flip flops for coarse-grained reconfigurable architectures

IKEZOE T., KOJIMA T., AMANO H.

IEICE Transactions on Electronics (IEICE Transactions on Electronics) 1 ( 6 ) 215 - 225 2021.06

ISSN 09168524

Recent IoT devices require extremely low standby power consumption, while a certain performance is needed during the active time, and Coarse-Grained Reconfigurable Arrays (CGRAs) have received attention because of their high energy efficiency. For further reduction of the standby energy consumption of CGRAs, the leakage power for their configuration memory must be reduced. Although the power gating is a common technique, the lost data in flip-flops and memory must be retrieved after the wake-up. Recovering everything requires numerous state transitions and considerable overhead both on its execution time and energy. To address the problem, Non-volatile Cool Mega Array (NVCMA), a CGRA providing non-volatile flip-flops (NVFFs) with spin transfer torque type non-volatile memory (NVM) technology has been developed. However, in general, non-volatile memory technologies have problems with reliability. Some NVFFs are stacked-at-0/1, and cannot store the data in a certain possibility. To improve the chip yield, we propose a mapping algorithm to avoid faulty processing elements of the CGRA caused by the erroneous configuration data. Next, we also propose a method to add an error-correcting code (ECC) mechanism to NVFFs for the configuration and constant memory. The proposed method was applied to NVCMA to evaluate the availability rate and reduction of write time. By using both methods, the average availability ratio of 94.2% was achieved, while the average availability ratio of the nine applications was 0.056% when the probability of failure of the FF was 0.01. The energy for storing data becomes about 2.3 times because of the hardware overhead of ECC but the proposed method can save 8.6% of the writing power on average.

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Hybrid Network of Packet Switching and STDM in a Multi-FPGA System

Shimizu T., Ito K., Iizuka K., Hironaka K., Amano H.

IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings (IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings) 2021.04

A multi-FPGA system, Flow-in-Cloud (FiC) system is currently being developed as a server for Multi-access Edge Computing (MEC), one of the core technologies of 5G. FiC system is composed of mid-range FPGAs directly connected by highspeed serial links and works virtually as a single FPGA with huge resources. Since the applications of MEC are sometimes timing- critical, a Static Time Division Multiplexing (STDM) network has been built on the FiC system. However, the STDM network suffers from the extended latency and low usage of the network resource especially when the network traffic is light. Here, we propose a hybrid router that allows packet switching to use empty slots of the STDM. The evaluation results from a real system appear that packet switching is 2.42 times faster than STDM with 8 boards FFT. Also, we propose and evaluate a dynamic allocation method that changes the switching mode according to the network load.

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A Case for Low-Latency Network-on-Chip using Compression Routers

Niwa N., Shikama Y., Amano H., Koibuchi M.

Proceedings - 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021 (Proceedings - 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021) 134 - 142 2021.03

The communication latency is a primary concern for designing Network-on-Chips (NoCs) since it significantly affects the parallel application performance on a many-core computer system. To reduce the communication latency, we propose an on-chip router that (de)compresses the contents of an incoming packet before completing switch arbitration. The compression router thus has no latency penalty for the compression operation, whereas it shortens a packet length that decreases the network injection-and-ejection latency. Evaluation results show that the compression router improves 7.7% of the parallel application performance (IS, CG, FT, and TSP) and 49% of the effective network throughput by 1.8 compression ratio on NoC. The drawback is that the router area and its energy consumption per bit increase by 0.12mm2 and 1.4 times compared to the conventional virtual-channel router.

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Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths

Shikama Y., Kawano R., Matsutani H., Amano H., Nagasaka Y., Fukumoto N., Koibuchi M.

Three-dimensional stack memory that provides both high-bandwidth access and large capacity is a promising technology for next-generation computer systems. While a large number of memory cubes increase the aggregate memory capacity, the communication latency and power consumption would become significant due to its low-radix large-diameter packet network. In this context, we propose a memory-cube network called Diagonal Memory Network (DMN). A diagonal network topology, its floor layout, and its lightweight router are designed for low-latency and low-voltage memory-read communication. Our evaluation results show that a DMN router decreases 31% of the hardware resources than a conventional virtual-channel router. The DMN router reduces 13% and 67% energy consumption to transit a packet along with the original datapath and bypassing datapath, respectively.

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TCI Tester: Tester for through Chip Interface

Kayashima H., Amano H.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC) 103 - 104 2021.01

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CLAHE implementation and evaluation on a low-end FPGA board by high-level synthesis

Honda K., Wei K., Arai M., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E104D ( 12 ) 2048 - 2056 2021

ISSN 09168532

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing to improve the quality of the image. Contrast Limited Adaptive Histogram Equalization (CLAHE) is one of such techniques to improve the quality of the image for the side mirror camera, which requires a large computation performance. Here, an implementation method of CLAHE on a low-end FPGA board by high-level synthesis is proposed. CLAHE has two main processing parts: cumulative distribution function (CDF) generation, and bilinear interpolation. During the CDF generation, the effect of increasing loop initiation interval can be greatly reduced by placing multiple Processing Elements (PEs). and during the interpolation, latency and BRAM usage were reduced by revising how to hold CDF and calculation method. Finally, by connecting each module with streaming interfaces, using data flow pragmas, overlapping processing, and hiding data transfer, our HLS implementation achieved a comparable result to that of HDL. We parameterized the components of the algorithm so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga clahe.

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CASE: CNN Acceleration for Speech-Classification in Edge-Computing

Gulzar H., Shakeel M., Nishida K., Itoyama K., Nakadai K., Amano H.

Proceedings - 2021 IEEE Cloud Summit, Cloud Summit 2021 (Proceedings - 2021 IEEE Cloud Summit, Cloud Summit 2021) 63 - 68 2021

High performance of Machine Learning algorithms has enabled numerous applications based upon speech interface in our daily life, but most of the frameworks use computationally expensive algorithms deployed on cloud servers as speech recognition engines. With the recent surge in the number of IoT devices, a robust and scalable solution for enabling AI applications on IoT devices is inevitable in form of edge computing. In this paper, we propose the application of Systemon-Chip (SoC) powered edge computing device as accelerator for speech commands classification using Convolutional Neural Network (CNN). Different aspects affecting the CNN performance are explored and an efficient and light-weight model named as CASENet is proposed which achieves state-of-the-art performance with significantly smaller number of parameters and operations. Efficient extraction of useful features from audio signal helped to maintain high accuracy with a 6X smaller number of parameters, making CASENet the smallest CNN in comparison to similarly performing networks. Light-weight nature of the model has led to achieve 96.45% validation accuracy with a 14X smaller number of operations which makes it ideal for low-power IoT and edge devices. A CNN accelerator is designed and deployed on FPGA part of SoC equipped edge server device. The hardware accelerator helped to improve the inference latency of speech command by a 6.7X factor as compared to standard implementation. Memory, computational cost and latency are the most important metrics for selecting a model to deploy on edge computing devices, and CASENet along with the accelerator surpasses all of these requirements.

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Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface

Kayashima H., Amano H.

Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 (Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021) 292 - 296 2021

The building block computing system can build several systems by stacking small chips with inductive coupling wireless chip-to-chip connection TCI (Through Chip Interface). TCI IP (Intellectual Property) was developed by using the Renesas 65nm SOTB process, and several family chips have been developed with the IP. Although all of the chips worked alone without problems, when they were stacked to construct a system, problems were found on some combinations of chips that TCI did not work as designed. This paper analyzes the resistances of power grid of chips with IPs from their layout to investigate the reason of the problems. Then, the voltage drop is estimated with the model built from the real chip evaluation. The analysis results appeared that in some chips, the resistances of the power grid are more than double of the target value, and because of the voltage drop, the supply voltage given to the IP of the largest chip SMTT is about the half of given to the power pad. Although it comes from the limitation of the I/O pads for chip stacking and fixed location of TCI IPs, we must take special care of the design of the transmitter power grid.

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An FPGA-based optimizer design for distributed deep learning with multiple GPUs

Itsubo T., Koibuchi M., Amano H., Matsutani H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E104D ( 12 ) 2057 - 2067 2021

ISSN 09168532

Since deep learning workloads perform a large number of matrix operations on training data, GPUs (Graphics Processing Units) are efficient especially for the training phase. A cluster of computers each of which equips multiple GPUs can significantly accelerate the deep learning workloads. More specifically, a back-propagation algorithm following a gradient descent approach is used for the training. Although the gradient computation is still a major bottleneck of the training, gradient aggregation and optimization impose both communication and computation overheads, which should also be reduced for further shortening the training time. To address this issue, in this paper, multiple GPUs are interconnected with a PCI Express (PCIe) over 10Gbit Ethernet (10GbE) technology. Since these remote GPUs are interconnected with network switches, gradient aggregation and optimizers (e.g., SGD, AdaGrad, Adam, and SMORMS3) are offloaded to FPGA-based 10GbE switches between remote GPUs; thus, the gradient aggregation and parameter optimization are completed in the network. The proposed FPGA-based 10GbE switches with the four optimizers are implemented on NetFPGA-SUME board. Their resource utilizations are increased by PEs for the optimizers, and they consume up to 56% of the resources. Evaluation results using four remote GPUs connected via the proposed FPGA-based switch demonstrate that these optimizers are accelerated by up to 3.0x and 1.25x compared to CPU and GPU implementations, respectively. Also, the gradient aggregation throughput by the FPGA-based switch achieves up to 98.3% of the 10GbE line rate.

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