Details of a Researcher - Amano, Hideharu

Papers - Amano, Hideharu

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RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA

Wei K., Kuno Y., Arai M., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 1 - 9 2022.06

Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-programmable gate array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation running on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the original design (libSGM), when working on the Tegra X2 GPU, RT-libSGM runs 2 × faster at a lower energy cost.

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Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning

Kojima T., Ohwada A., Amano H.

IEEE Transactions on Parallel and Distributed Systems (IEEE Transactions on Parallel and Distributed Systems) 33 ( 5 ) 1213 - 1230 2022.05

ISSN 10459219

Coarse-grained reconfigurable architectures (CGRAs) provide high energy efficiency with word-level programmability rather than bit-level ones such as FPGAs. The coarser reconfigurability brings about higher energy efficiency and reduces the complexity of compiler tasks compared to the FPGAs. However, application mapping process for CGRAs is still time-consuming. When the compiler tries to map a large and complicated application data-flow-graph(DFG) onto the reconfigurable fabric, it tends to result in inefficient resource use or to fail in mapping. In case of failure, the compiler must divide it into several sub-DFGs and goes back to the same flow. In this work, we propose a novel partitioning method based on a genetic algorithm to eliminate the unmappable DFGs and improve the mapping quality. In order not to generate unmappable sub-DFGs, we also propose an estimation model which predicts the mappability and resource requirements using a DGCNN (Deep Graph Convolutional Neural Network). The genetic algorithm with this model can seek the most resource-efficient mapping without the back-end mapping process. Our model can predict the mappability with more than 98% accuracy and resource usage with a negligible error for two studied CGRAs. Besides, the proposed partitioning method demonstrates 53-75% of memory saving, 1.28-1.39x higher throughput, and better mapping quality over three comparative approaches.

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A traffic-aware memory-cube network using bypassing

Shikama Y., Kawano R., Matsutani H., Amano H., Nagasaka Y., Fukumoto N., Koibuchi M.

Microprocessors and Microsystems (Microprocessors and Microsystems) 90 2022.04

ISSN 01419331

Three-dimensional stack memory which provides both high-bandwidth access and large capacity is a promising technology for next-generation computer systems. While a large number of memory cubes increase the aggregate memory capacity, the communication latency and power consumption increase significantly owing to its low-radix large-diameter packet network. In this context, we propose a memory-cube network called Diagonal Memory Network (DMN). A diagonal network topology, its floor layout, and its lightweight router were designed for low-latency and low-voltage memory-read communication. DMN routing efficiently avoids deadlocks of packets, although it allows each packet transmitted to a processor to use both bypassing and original datapaths. Our evaluation results show that the DMN router decreases the use of hardware resources by more than 31% compared with a conventional virtual channel router. The DMN router reduces energy consumption by 13% and 67% to transit a packet along with the original datapath and bypassing datapath, respectively. Furthermore, using flit-level discrete event simulation, a DMN topology achieves high throughput and latency that is lower than that of existing network topologies using conventional packet routers.

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Body Bias Control on a CGRA based on Convex Optimization

Kojima T., Okuhara H., Kondo M., Amano H.

25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022 - Proceedings (25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022 - Proceedings) 2022

Body biasing is one of the critical techniques to realize more energy-efficient computing with reconfigurable devices, such as Coarse-Grained Reconfigurable Architectures (CGRAs). Its benefit depends on the control granularity, whereas fine-grained control makes it challenging to find the best body bias voltage for each domain due to the complexity of the optimization problem. This work reformulates the optimization problem and introduces continuous relaxation to solve it faster than previous work. Experimental result shows the proposed method can solve the problem within 0.5 sec for all benchmarks in any conditions and demonstrates up to 5.65x speed-up compared to the previous method with negligible loss of accuracy.

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An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings

Ohwada A., Kojima T., Amano H.

Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022 (Proceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022) 1 - 9 2022

In recent years, IoT devices have become widespread, and energy-efficient coarse-grained reconfigurable architectures (CGRAs) have attracted attention. CGRAs comprise several processing units called processing elements (PEs) arranged in a two-dimensional array. The operations of PEs and the interconnections between them are adaptively changed depending on a target application, and this contributes to a higher energy efficiency compared to general-purpose processors. The application kernel executed on CGRAs is represented as a data flow graph (DFG), and CGRA compilers are responsible for mapping the DFG onto the PE array. Thus, mapping algorithms significantly influence the performance and power efficiency of CGRAs as well as the compile time. This paper proposes POCOCO, a compiler framework for CGRAs that can use pre-optimized subgraph mappings. This contributes to reducing the compiler optimization task. To leverage the subgraph mappings, we extend an existing mapping method based on a genetic algorithm. Experiments on three architectures demonstrated that the proposed method reduces the optimization time by 48%, on an average, for the best case of the three architectures.

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Power Analysis of Directly-connected FPGA Clusters

Iizuka K., Takagi H., Kamei A., Hironaka K., Amano H.

Although low power consumption is a significant advantage of FPGA clusters, almost no power analyses with real systems have been reported. This study reports the detailed power consumption analyses of two FPGA clusters, namely, M-KUBOS and FiC, with power measurement tools and real applications. In both clusters, the type of logic design shells determines the base power consumption. For building clusters, the power for node communication links is mainly determined by the number of activated links and not influenced by the number of actually used links. Therefore, applying the link aggregation technique does not affect the power consumption. Increasing the clock frequency of the application logic mildly increases the power consumption. The obtained results suggest that the best way to reduce the total power consumption of an FPGA cluster and improve its performance is to use the minimum number of links for the application, apply link aggregation, and aggressively increase the clock frequency.

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Power Consumption Reduction Method and Edge Offload Server for Multiple Robots

Natsuho S., Ohkawa T., Amano H., Sugaya M.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)) 12990 LNCS 1 - 19 2022

ISSN 03029743

There are emerging services for the transports and nursing with multiple robots has become more familiar to our society. Considering the increasing demand for automatic multiple robotic services, it appears the research into automatic multiple robotic services is not satisfactory. Specifically, the issues of power consumption of these robots, and its potential reduction have not been sufficiently discussed. In this research, we propose a method and system to reduce the aggregated power consumption of multiple robots by modelling the characteristics of the hardware and service of each robot. We firstly discuss the prediction model of the robot and improve the formula with consideration of its use in a wide range of situations. Then, we achieve the objective of reducing the aggregate power consumption of multiple robots, using consumption logs and re-allocating tasks of them based on the power consumption prediction model of the individual robot. We propose the design and develop a system using ROS (Robot Operating System) asynchronous server to collect the data from the robots, and make the prediction model for each robot, and reallocate tasks based on the findings of the optimized combination on the server. Through the evaluation of the design and implementation with the proposed system and the actual robot Zoom (GR-PEACH + Rasberry pi), we achieve an average power reduction effect of 14%. In addition, by offloading high-load processing to an edge server configured with FPGA instead the Intel Core i7 performance computer, we achieved and increase in processing speed of up to about 70 times.

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Analytical performance estimation for large-scale reconfigurable dataflow platforms

Yasudo R., Coutinho J.G.F., Varbanescu A.L., Luk W., Amano H., Becker T., Guo C.

ACM Transactions on Reconfigurable Technology and Systems (ACM Transactions on Reconfigurable Technology and Systems) 14 ( 3 ) 2021.09

ISSN 19367406

Next-generation high-performance computing platforms will handle extreme data- and compute-intensive problems that are intractable with today's technology. A promising path in achieving the next leap in high-performance computing is to embrace heterogeneity and specialised computing in the form of reconfigurable accelerators such as FPGAs, which have been shown to speed up compute-intensive tasks with reduced power consumption. However, assessing the feasibility of large-scale heterogeneous systems requires fast and accurate performance prediction. This article proposes Performance Estimation for Reconfigurable Kernels and Systems (PERKS), a novel performance estimation framework for reconfigurable dataflow platforms. PERKS makes use of an analytical model with machine and application parameters for predicting the performance of multi-accelerator systems and detecting their bottlenecks. Model calibration is automatic, making the model flexible and usable for different machine configurations and applications, including hypothetical ones. Our experimental results show that PERKS can predict the performance of current workloads on reconfigurable dataflow platforms with an accuracy above 91%. The results also illustrate how the modelling scales to large workloads, and how performance impact of architectural features can be estimated in seconds.

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A programming environment for multi-FPGA systems based on CyberWorkBench: An integrated design tool

Suzuki H., Takahashi W., Wakabayashi K., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 2021.06

This paper proposes a multi-FPGA programming environment based on NEC's integrated design tool CyberWorkBench (CWB) for a multi-FPGA system FiC (Flow-in-Cloud). Programmers describe their program in SystemC as small modules connected with FIFO channels, then verify the operation with the behavioral simulation considering parallel execution. After the high-level synthesis (HLS) is done with CWB, modules distributed to each board are decided, and the interface module is inserted. The cycle accurate simulation is applied to ensure the operation and estimate the performance. Finally, generated Verilog HDL code for each board is implemented with Xilinx's Vivado just like the traditional design and configuration is obtained. As an example, a simple convolutional neural network LeNet is described and implemented on a real system using the tool. Although the cycle accurate simulation takes 105.34sec, the estimated cycles are only 2.2% difference from the real boards execution result. Since the example CNN LeNet is too small, it can be implemented into a single board with a traditional design tool. However, considering the pipeline execution, parallel execution with two boards can distribute the input and output into different FPGAs, and relax the bottleneck.

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GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph

Kawano R., Matsutani H., Koibuchi M., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 51 - 55 2021.06

The design of the network topology of a large-scale parallel computer system can be represented as an order/degree problem in the graph theory. To solve the order/degree problem, we have to obtain all-pairs-shortest-path (APSP) for the graph. A conventional APSP algorithm for GPUs is based on the adjacency matrix (ADJ-APSP). When focusing on low-degree and unweighted graphs, most of the matrix elements are zero in the first few iterations of the algorithm. We will further speed up the APSP algorithm by treating the adjacency matrix as a sparse matrix in the first iterations of the algorithm. Evaluation results show that our proposed algorithm on a single GPU (NVIDIA GeForce RTX 3080) reduces the execution time by up to 32.7 % compared to the conventional algorithm.

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Implementing VTA, a tensor accelerator on Flow-in-Cloud

Hironaka K., Iizuka K., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 46 - 50 2021.06

A multi-FPGA system Flow-in-Cloud (FiC) consists of nodes with a mid-class cost-efficient FPGA and Raspberry Pi3B connected with high speed serial links. It aims to implement a large scale AI applications which is difficult to be implemented on a single FPGA by dividing the target into a number of boards. On the other hand, overlay domain specific architecture receives attention for implementing complicated application programs easily on the FPGA. Here, we focus on an open-source AI compiler framework Apache TVM, and its implementation for FPGA, VTA(Versatile Tensor Accelerator). In order to use FiC through the TVM, we implemented it on FiC and executed the ResNet-18 inference benchmark. The preliminary evaluation results showed that VTA on FiC-SW achieved up to 10 times performance compared to the execution on ARM Cortex-A54 software.

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Recovering faulty non-volatile flip flops for coarse-grained reconfigurable architectures

IKEZOE T., KOJIMA T., AMANO H.

IEICE Transactions on Electronics (IEICE Transactions on Electronics) 1 ( 6 ) 215 - 225 2021.06

ISSN 09168524

Recent IoT devices require extremely low standby power consumption, while a certain performance is needed during the active time, and Coarse-Grained Reconfigurable Arrays (CGRAs) have received attention because of their high energy efficiency. For further reduction of the standby energy consumption of CGRAs, the leakage power for their configuration memory must be reduced. Although the power gating is a common technique, the lost data in flip-flops and memory must be retrieved after the wake-up. Recovering everything requires numerous state transitions and considerable overhead both on its execution time and energy. To address the problem, Non-volatile Cool Mega Array (NVCMA), a CGRA providing non-volatile flip-flops (NVFFs) with spin transfer torque type non-volatile memory (NVM) technology has been developed. However, in general, non-volatile memory technologies have problems with reliability. Some NVFFs are stacked-at-0/1, and cannot store the data in a certain possibility. To improve the chip yield, we propose a mapping algorithm to avoid faulty processing elements of the CGRA caused by the erroneous configuration data. Next, we also propose a method to add an error-correcting code (ECC) mechanism to NVFFs for the configuration and constant memory. The proposed method was applied to NVCMA to evaluate the availability rate and reduction of write time. By using both methods, the average availability ratio of 94.2% was achieved, while the average availability ratio of the nine applications was 0.056% when the probability of failure of the FF was 0.01. The energy for storing data becomes about 2.3 times because of the hardware overhead of ECC but the proposed method can save 8.6% of the writing power on average.

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Hybrid Network of Packet Switching and STDM in a Multi-FPGA System

Shimizu T., Ito K., Iizuka K., Hironaka K., Amano H.

IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings (IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings) 2021.04

A multi-FPGA system, Flow-in-Cloud (FiC) system is currently being developed as a server for Multi-access Edge Computing (MEC), one of the core technologies of 5G. FiC system is composed of mid-range FPGAs directly connected by highspeed serial links and works virtually as a single FPGA with huge resources. Since the applications of MEC are sometimes timing- critical, a Static Time Division Multiplexing (STDM) network has been built on the FiC system. However, the STDM network suffers from the extended latency and low usage of the network resource especially when the network traffic is light. Here, we propose a hybrid router that allows packet switching to use empty slots of the STDM. The evaluation results from a real system appear that packet switching is 2.42 times faster than STDM with 8 boards FFT. Also, we propose and evaluate a dynamic allocation method that changes the switching mode according to the network load.

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A Case for Low-Latency Network-on-Chip using Compression Routers

Niwa N., Shikama Y., Amano H., Koibuchi M.

Proceedings - 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021 (Proceedings - 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021) 134 - 142 2021.03

The communication latency is a primary concern for designing Network-on-Chips (NoCs) since it significantly affects the parallel application performance on a many-core computer system. To reduce the communication latency, we propose an on-chip router that (de)compresses the contents of an incoming packet before completing switch arbitration. The compression router thus has no latency penalty for the compression operation, whereas it shortens a packet length that decreases the network injection-and-ejection latency. Evaluation results show that the compression router improves 7.7% of the parallel application performance (IS, CG, FT, and TSP) and 49% of the effective network throughput by 1.8 compression ratio on NoC. The drawback is that the router area and its energy consumption per bit increase by 0.12mm2 and 1.4 times compared to the conventional virtual-channel router.

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Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths

Shikama Y., Kawano R., Matsutani H., Amano H., Nagasaka Y., Fukumoto N., Koibuchi M.

Three-dimensional stack memory that provides both high-bandwidth access and large capacity is a promising technology for next-generation computer systems. While a large number of memory cubes increase the aggregate memory capacity, the communication latency and power consumption would become significant due to its low-radix large-diameter packet network. In this context, we propose a memory-cube network called Diagonal Memory Network (DMN). A diagonal network topology, its floor layout, and its lightweight router are designed for low-latency and low-voltage memory-read communication. Our evaluation results show that a DMN router decreases 31% of the hardware resources than a conventional virtual-channel router. The DMN router reduces 13% and 67% energy consumption to transit a packet along with the original datapath and bypassing datapath, respectively.

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TCI Tester: Tester for through Chip Interface

Kayashima H., Amano H.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC) 103 - 104 2021.01

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CLAHE implementation and evaluation on a low-end FPGA board by high-level synthesis

Honda K., Wei K., Arai M., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E104D ( 12 ) 2048 - 2056 2021

ISSN 09168532

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing to improve the quality of the image. Contrast Limited Adaptive Histogram Equalization (CLAHE) is one of such techniques to improve the quality of the image for the side mirror camera, which requires a large computation performance. Here, an implementation method of CLAHE on a low-end FPGA board by high-level synthesis is proposed. CLAHE has two main processing parts: cumulative distribution function (CDF) generation, and bilinear interpolation. During the CDF generation, the effect of increasing loop initiation interval can be greatly reduced by placing multiple Processing Elements (PEs). and during the interpolation, latency and BRAM usage were reduced by revising how to hold CDF and calculation method. Finally, by connecting each module with streaming interfaces, using data flow pragmas, overlapping processing, and hiding data transfer, our HLS implementation achieved a comparable result to that of HDL. We parameterized the components of the algorithm so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga clahe.

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CASE: CNN Acceleration for Speech-Classification in Edge-Computing

Gulzar H., Shakeel M., Nishida K., Itoyama K., Nakadai K., Amano H.

Proceedings - 2021 IEEE Cloud Summit, Cloud Summit 2021 (Proceedings - 2021 IEEE Cloud Summit, Cloud Summit 2021) 63 - 68 2021

High performance of Machine Learning algorithms has enabled numerous applications based upon speech interface in our daily life, but most of the frameworks use computationally expensive algorithms deployed on cloud servers as speech recognition engines. With the recent surge in the number of IoT devices, a robust and scalable solution for enabling AI applications on IoT devices is inevitable in form of edge computing. In this paper, we propose the application of Systemon-Chip (SoC) powered edge computing device as accelerator for speech commands classification using Convolutional Neural Network (CNN). Different aspects affecting the CNN performance are explored and an efficient and light-weight model named as CASENet is proposed which achieves state-of-the-art performance with significantly smaller number of parameters and operations. Efficient extraction of useful features from audio signal helped to maintain high accuracy with a 6X smaller number of parameters, making CASENet the smallest CNN in comparison to similarly performing networks. Light-weight nature of the model has led to achieve 96.45% validation accuracy with a 14X smaller number of operations which makes it ideal for low-power IoT and edge devices. A CNN accelerator is designed and deployed on FPGA part of SoC equipped edge server device. The hardware accelerator helped to improve the inference latency of speech command by a 6.7X factor as compared to standard implementation. Memory, computational cost and latency are the most important metrics for selecting a model to deploy on edge computing devices, and CASENet along with the accelerator surpasses all of these requirements.

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Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface

Kayashima H., Amano H.

Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 (Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021) 292 - 296 2021

The building block computing system can build several systems by stacking small chips with inductive coupling wireless chip-to-chip connection TCI (Through Chip Interface). TCI IP (Intellectual Property) was developed by using the Renesas 65nm SOTB process, and several family chips have been developed with the IP. Although all of the chips worked alone without problems, when they were stacked to construct a system, problems were found on some combinations of chips that TCI did not work as designed. This paper analyzes the resistances of power grid of chips with IPs from their layout to investigate the reason of the problems. Then, the voltage drop is estimated with the model built from the real chip evaluation. The analysis results appeared that in some chips, the resistances of the power grid are more than double of the target value, and because of the voltage drop, the supply voltage given to the IP of the largest chip SMTT is about the half of given to the power pad. Although it comes from the limitation of the I/O pads for chip stacking and fixed location of TCI IPs, we must take special care of the design of the transmitter power grid.

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An FPGA-based optimizer design for distributed deep learning with multiple GPUs

Itsubo T., Koibuchi M., Amano H., Matsutani H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E104D ( 12 ) 2057 - 2067 2021

ISSN 09168532

Since deep learning workloads perform a large number of matrix operations on training data, GPUs (Graphics Processing Units) are efficient especially for the training phase. A cluster of computers each of which equips multiple GPUs can significantly accelerate the deep learning workloads. More specifically, a back-propagation algorithm following a gradient descent approach is used for the training. Although the gradient computation is still a major bottleneck of the training, gradient aggregation and optimization impose both communication and computation overheads, which should also be reduced for further shortening the training time. To address this issue, in this paper, multiple GPUs are interconnected with a PCI Express (PCIe) over 10Gbit Ethernet (10GbE) technology. Since these remote GPUs are interconnected with network switches, gradient aggregation and optimizers (e.g., SGD, AdaGrad, Adam, and SMORMS3) are offloaded to FPGA-based 10GbE switches between remote GPUs; thus, the gradient aggregation and parameter optimization are completed in the network. The proposed FPGA-based 10GbE switches with the four optimizers are implemented on NetFPGA-SUME board. Their resource utilizations are increased by PEs for the optimizers, and they consume up to 56% of the resources. Evaluation results using four remote GPUs connected via the proposed FPGA-based switch demonstrate that these optimizers are accelerated by up to 3.0x and 1.25x compared to CPU and GPU implementations, respectively. Also, the gradient aggregation throughput by the FPGA-based switch achieves up to 98.3% of the 10GbE line rate.

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A multi-tenant resource management system for multi-FPGA systems

Yamakura M., Takano R., Ben Ahmed A., Sugaya M., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E104D ( 12 ) 2078 - 2088 2021

ISSN 09168532

FPGA (Field Programmable Gate Array) based accelerators are attracting significant interest in cloud computing systems. Combining multi-FPGA systems with cloud computing brings a new perspective to the reconfigurable computing research. However, the multi-tenancy of a multi-FPGA system has not been fully discussed in the previous researches. In this paper, we propose a multi-tenant resource management system, named FiC-RM, for a multi-FPGA cloud system. FiC-RM provides users with a set of FPGA resources according to their requirements and allows them to exclusively access FPGA boards and the interconnection network. To achieve this, we propose a placement algorithm which is a key to efficiently share the limited resources. We demonstrate FiC-RM controls a practical scale multi-FPGA system. Moreover, Our simulation study shows that our placement algorithm achieved 3 to 4% improvement in the average resource usage and a 20-second reduction in the response time, compared to other existing naive algorithms.

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Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops

Kamei A., Kojima T., Amano H., Yokoyama D., Miyauchi H., Usami K., Hiraga K., Suzuki K., Bessho K.

Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021 (Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021) 273 - 280 2021

In this study, a second-generation coarse-grained reconfigurable array with non-volatile flip-flops (NVFFs), known as the non-volatile cool mega array with multi-context (NVCMA/MC), is proposed. Similar to the previous NVCMA, verify-and-retriable NVFFs (VR-NVFFs) are provided for their configuration memory, constant memory, data memory, and instruction memory. The dedicated instructions for controlling the store, verify, and restore operations of the NVFFs are provided to the microcontroller in addition to power gating functions. Based on experience of the NVCMA, four hardware contexts are introduced to maintain the configuration data for four tasks, without the sacrifice of memory leakage. The array size is expanded, and pipeline registers are introduced to reduce the trade-off between the performance and power consumption. This study mainly focuses on the energy-saving effect of the VR-NVFFs and the multi-context facility of the NVCMA/MC, including the measurement of the break-even point. The evaluation of a real chip implemented with 40 nm MTJ/MOS hybrid process technology demonstrates that the store energy is reduced by 65% with the two-step store control of the VR-NVFFs. Moreover, applications that run intermittently for intervals as short as approximately 3 μs can benefit from the multi-context power gating.

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Weight Least Square Filter for Improving the Quality of Depth Map on FPGA

Mao R., Wei K., Amano H., Kuno Y., Arai M.

The techniques based on measuring the distance between objects and the camera itself have made progress in recent years. Through this technology, the system used for 3D imaging will provide a great convenience for people's lives. In this project, we focus on optimizing depth maps with better quality for the 3D scene display system on the car. During the 3D imaging process, to calculate the distance between a certain location and one of the specific points of the scene, it will produce two depth maps computed from two images as an intermediate product for 3D imaging processing. However, there is a great number of invalid pixels that distance cannot be measured. In dealing with such drawbacks, post-filtering has been introduced as a solution. In this project, we propose implementing the Weight Least Square (WLS) filter on FPGA, which can fill the invalid pixels by using the results of neighboring pixels. Through our approach, we can improve the quality of the depth map on M-KUBOS. Besides that, the optimized memory usage can successfully suit the size of the memory on-chip, and a 69.29% acceleration compared to the ARM core.

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Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim

Yan Y.J., Amano H., Aono M., Ohkoda K., Fukuda S., Saito K., Kasai S.

2021 International Conference on Field-Programmable Technology, ICFPT 2021 (2021 International Conference on Field-Programmable Technology, ICFPT 2021) 2021

The Boolean satisfiability problem (SAT) is an NP-complete combinatorial optimization problem, where fast SAT solvers are useful for various smart society applications. Since these edge-oriented applications require time-critical control, a high speed SAT solver on FPGA is a promising approach. Here the authors propose a novel FPGA implementation of a bio-inspired stochastic local search algorithm called 'AmoebaSAT' on a Zynq board. Previous studies on FPGA-AmoebaSATs tackled relatively smaller-sized 3-SAT instances with a few hundred variables and found the solutions in several milli seconds. These implementations, however, adopted an instance-specific approach, which requires synthesis of FPGA configuration every time when the targeted instance is altered. In this paper, a slimmed version of AmoebaSAT named 'AmoebaSATslim,' which omits the most resource-consuming part of interactions among variables, is proposed. The FPGA-AmoebaSATslim enables to tackle significantly larger-sized 3-SAT instances, accepting 30,000 variables with 130, 800 clauses. It achieves up to approximately 24 times faster execution speed than the software-AmoebaSATslim implemented on a CPU of the x86 server.

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Remote dynamic reconfiguration of a multi-FPGA system FiC (flow-in-cloud)

Hironaka K., Iizuka K., Yamakura M., Ben Ahmed A., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E104D ( 8 ) 1321 - 1331 2021

ISSN 09168532

Multi-FPGA systems have been receiving a lot of attention as a low cost and energy efficient system for Multi-access Edge Computing (MEC). For such purpose, a bare-metal multi-FPGA system called FiC (Flow-in-Cloud) is under development. In this paper, we introduce the FiC multi FPGA cluster which is applied partial reconfiguration (PR) FPGA design flow to support online user defined accelerator replacement while executing FPGA interconnection network and its low-level multiple FPGA management software called remote PR manager. With the remote PR manager, the user can define the FiC FPGA cluster setup by JSON and control the cluster from user application with the cooperation of simple cluster management tool / library called ficmgr on the client host and REST API service provider called ficwww on Raspberry Pi 3 (RPi3) on each node. According to the evaluation results with a prototype FiC FPGA cluster system with 12 nodes, using with online application replacement by PR and on-the-fly FPGA bitstream compression, the time for FPGA bitstream distribution was reduced to 1/17 and the total cluster setup time was reduced by 21∼57% than compared to cluster setup with full configuration FPGA bitstream.

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Parallel Implementation of CNN on Multi-FPGA Cluster

Fukushima Y., Iizuka K., Amano H.

We developed a PYNQ cluster called M-KUBOS that consists of economical Zynq boards that are interconnected through low-cost high-performance GTH serial links. For the software environment, we employed the PYNQ open-source software platform. The PYNQ cluster is anticipated to be a multi-access edge computing (MEC) server for 5G mobile networks. We implemented the ResNet-50 inference accelerator on the PYNQ cluster for image recognition of MEC applications. By estimating the execution time of each ResNet-50 layer, layers of ResNet-50 were divided into four boards so that the execution time of each board would be as equal as possible for efficient pipeline processing. Owing to the PYNQ cluster in which FPGAs were directly connected by high-speed serial links, stream processing without network bottlenecks and pipeline processing between boards were readily realized. The implementation achieved 292 GOPS performance, 75.1 FPS throughput, and 5.15 GOPS/W power efficiency. It achieved 17 times faster speed and 86 times more power efficiency compared to the implementation on the CPU, and 3.8 times more power efficiency compared to the implementation on the GPU.

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M-KUBOS/PYNQ Cluster for multi-Access edge computing

Inage T., Hironaka K., Iizuka K., Ito K., Fukushima Y., Namiki M., Amano H.

Proceedings - 2021 9th International Symposium on Computing and Networking, CANDAR 2021 (Proceedings - 2021 9th International Symposium on Computing and Networking, CANDAR 2021) 95 - 101 2021

The M-KUBOS/PYNQ cluster is proposed as an energy efficient computing server for MEC(Multi-Access Edge Computing) which treats various tasks including time-critical jobs at 5G base stations. M-KUBOS boards each of which provides the largest model of Zynq UltraScale+ are connected with high speed serial GTH links and STDM (static time division multiplexing) switches. PYNQ(Python productivity for Zynq), an open-source software platform by Xilinx was introduced so that the multi-Zynq system can be used as a multitenant server. The PYNQ cluster can be programmed by extension of a single PYNQ system, and RESTful APIs are introduced for runtime management of multiple Zynq boards from a remote server. The design examples and evaluation results demonstrate that the M-KUBOS/PYNQ cluster achieved 1.0-17.2 times the performance and 1.75-85.8 times the performance per watt of the recent Ryzen-7 server.

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Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression

Niwa N., Amano H., Koibuchi M.

Proceedings - 2021 9th International Symposium on Computing and Networking, CANDAR 2021 (Proceedings - 2021 9th International Symposium on Computing and Networking, CANDAR 2021) 56 - 64 2021

Interconnection network ideally transfers the maximum amount of communication dataset within the least amount of time to fully exploit the parallelism of target applications on parallel computer systems. To this goal, we propose a selective data-compression interconnection network. Data compression virtually increases the effective network bandwidth, while each compute node introduces additional latency overhead to perform (de-)compression operation to end-To-end communication latency. To minimize the effect of the compression latency overhead on the end-To-end communication latency, we selectively apply a compression technique to a packet. The compression operation is taken for long packets and is also taken when network congestion is detected at a network interface. Evaluation results show that simple lossless and lossy compression algorithms have up to 3.0 and 1.8 compression ratios for integer and floating-point communication data in some parallel applications, respectively, while the lossy compression algorithm successfully satisfies the required quality of results. Through a cycle-network simulation, the selective compression method using the above compression algorithms improves by up to 46% the network throughput with the moderate increase of the communication latency of short packets.

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Improving the performance of circuit-switched interconnection network for a multi-FPGA system

Ito K., Iizuka K., Hironaka K., Hu Y., Koibuchi M., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E104D ( 12 ) 2029 - 2039 2021

ISSN 09168532

SUMMARY Multi-FPGA systems have gained attention because of their high performance and power efficiency. A multi-FPGA system called Flow-in-Cloud (FiC) is currently being developed as an accelerator of multi-access edge computing (MEC). FiC consists of multiple mid-range FPGAs tightly connected by high-speed serial links. Since time-critical jobs are assumed in MEC, a circuit-switched network with static time-division multiplexing (STDM) switches has been implemented on FiC. This paper investigates techniques of enhancing the interconnection performance of FiC. Unlike switching fabrics for Network on Chips or parallel machines, economical multi-FPGA systems, such as FiC, use Xilinx Aurora IP and FireFly cables with multiple lanes. We adopted the link aggregation and the slot distribution for using multiple lanes. To mitigate the bottleneck between an STDM switch and user logic, we also propose a multi-ejection STDM switch. We evaluated various combinations of our techniques by using three practical applications on an FiC prototype with 24 boards. When the number of slots is large and transferred data size is small, the slot distribution was sometimes more effective, while the link aggregation was superior for other most cases. Our multi-ejection STDM switch mitigated the bottleneck in ejection ports and successfully reduced the number of time slots. As a result, by combining the link aggregation and multi-ejection STDM switch, communication performance improved up to 7.50 times with few additional resources. Although the performance of the fast Fourier transform with the highest communication ratio could not be enhanced by using multiple boards when a lane was used, 1.99 times performance improvement was achieved by using 8 boards with four lanes and our multi-ejection switch compared with a board.

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FiC-RNN: A multi-FPGA acceleration framework for deep recurrent neural networks

Sun Y., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E103D ( 12 ) 2457 - 2462 2020.12

ISSN 09168532

Recurrent neural networks (RNNs) have been proven effective for sequence-based tasks thanks to their capability to process temporal information. In real-world systems, deep RNNs are more widely used to solve complicated tasks such as large-scale speech recognition and machine translation. However, the implementation of deep RNNs on traditional hardware platforms is inefficient due to long-range temporal dependence and irregular computation patterns within RNNs. This inefficiency manifests itself in the proportional increase in the latency of RNN inference with respect to the number of layers of deep RNNs on CPUs and GPUs. Previous work has focused mostly on optimizing and accelerating individual RNN cells. To make deep RNN inference fast and efficient, we propose an accelerator based on a multi-FPGA platform called Flow-in-Cloud (FiC). In this work, we show that the parallelism provided by the multi-FPGA system can be taken advantage of to scale up the inference of deep RNNs, by partitioning a large model onto several FPGAs, so that the latency stays close to constant with respect to increasing number of RNN layers. For single-layer and four-layer RNNs, our implementation achieves 31x and 61x speedup compared with an Intel CPU.

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Traffic-independent multi-path routing for high-throughput data center networks

Kawano R., Yasudo R., Matsutani H., Koibuchi M., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E103D ( 12 ) 2471 - 2479 2020.12

ISSN 09168532

Network throughput has become an important issue for big-data analysis on Warehouse-Scale Computing (WSC) systems. It has been reported that randomly-connected inter-switch networks can enlarge the network throughput. For irregular networks, a multi-path routing method called k-shortest path routing is conventionally utilized. However, it cannot efficiently exploit longer-than-shortest paths that would be detour paths to avoid bottlenecks. In this work, a novel routing method called koptimized path routing to achieve high throughput is proposed for irregular networks. We introduce a heuristic to select detour paths that can avoid bottlenecks in the network to improve the average-case network throughput. Experimental results by network simulation show that the proposed k-optimized path routing can improve the saturation throughput by up to 18.2% compared to the conventional k-shortest path routing. Moreover, it can reduce the computation time required for optimization to 1/2760 at a minimum compared to our previously proposed method.

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Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems

Leal D.P., Sugaya M., Amano H., Ohkawa T.

Proceedings - 2020 International Conference on Field-Programmable Technology, ICFPT 2020 (Proceedings - 2020 International Conference on Field-Programmable Technology, ICFPT 2020) 292 - 293 2020.12

Integrating FPGAs to robot systems can be a demanding task. In this paper we present Forest, an open-source tool that automatically generates ROS2 nodes for high-level synthesis-based FPGA modules, greatly facilitating the integration of FPGAs with other robot components. Forest runs on the PYNQ version 2.5 environment with ROS2 Eloquent and can be used with Xilinx SoCs, such as Xilinx Zynq-7000. The ROS2-FPGA node generated by Forest is evaluated in an image processing task, where the FPGA logic performs a linear contrast stretch on images of three different sizes, and an average speed-up of 36.3x and a performance per watt improvement of 432.2x is observed when compared to a ROS2 node running on a modern CPU.

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An implementation methodology for Neural Network on a Low-end FPGA Board

Wei K., Honda K., Amano H.

Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020 (Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020) 228 - 234 2020.11

Artificial Intelligence(AI) has achieved unprecedented success in various fields including image/speech recognition which is useful for edge computing. Most of AI systems are implemented on power-hungry devices like GPU, high-end FPGA, or even TPU to process data with high performance. However, these energy budgets are often not affordable to edge computing. Low-end FPGA taking advantage of high energy-efficiency is a desirable platform to meet the requirements of image recognition working on small autonomous vehicles. In this paper, we propose the design methodology and implementation to adapt a neural network system to a low-end FPGA board using HLS description. The whole design consists of algorithm-level downscaling and hardware optimization. The former emphasizes the model downscale by considering accuracy. The latter applies various HLS design techniques to speed-up the application running on the target board. In the case study of tiny YOLO (You Only Look Once) v3, the model running on PYNQ-Z1 presents up to 22× acceleration comparing with the PYNQ ARM CPU. Energy efficiency also achieves 3× better than Xeon E5-2667.

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CLAHE implementation on a low-end FPGA board by high-level synthesis

Honda K., Wei K., Arai M., Amano H.

Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020 (Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020) 282 - 285 2020.11

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing for improving quality. This paper describes a design of Contrast Limited Adaptive Histogram Equalization (CLAHE), which improves the quality of the dark image for the side mirror camera, on a low-end FPGA board by high-level synthesis. By constituting CLAHE as a data flow design flow, we could achieve performance comparable to the implementation with HDL. The code is parameterized so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga_clahe.

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Exploiting temporal parallelism in particle-based incompressive fluid simulation on FPGA

Orsztynowicz M., Amano H., Kubota K., Miyajima T.

Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020 (Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020) 195 - 201 2020.11

—While the semiconductor manufacturing process is shrinking, the Bytes per Flop (B/F) ratio on recent machines is becoming lower. Particle-based computational fluid dynamics (CFD) methods such as Moving Particle Simulation (MPS) require a higher B/F ratio than that of stencil-based CFD methods. Techniques to reduce the B/F ratio by exploiting temporal parallelism is becoming popular in stencil-based CFD methods on CPU and GPU. It is also reported that a technique to combine temporal blocking with stencil buffer is suitable for FPGA and can outperform CPU and GPU. On the other hand, it has been considered that temporal parallelism cannot be exploited in the particle-based CFD methods. This is because the number of particles in each bucket, a three-dimensional grid covering a computational domain, changes every time-step. In this paper, we propose a technique to exploit temporal parallelism in MPS method, a particle-based CFD method for incompressive fluid. The key idea is that the buckets in MPS can be considered as stencils in stencil-based CFD. This is because the maximum number of particles in a bucket can be assumed empirically in the case of an incompressible fluid. To the best of our knowledge, this is the first research which exploits temporal parallelism in the particle-based incompressible fluid method. We implemented the proposed technique with a degree of temporal parallelism of three. We also optimized it on Intel Arria10 FPGA in Intel HLS, and measured the performance and resource consumption. The result shows that the optimized implementation with a degree of temporal parallelism of three achieved 2.1 times speedup compared with implementation without exploiting temporal parallelism on CPU.

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Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks

Kawano R., Matsutani H., Amano H.

As the scale of supercomputers has increased, the end-to-end network latency has become non-negligible on the performance of parallel applications. For this reason, low-latency network topologies achieving the smallest number of hops among switches are drawing attention. The Order/Degree Problem to find the topology with the smallest diameter has revealed that a topology based on graph symmetry and simulated annealing (SA) is optimal for a wide range of system sizes. Focusing on the characteristics of clustering and symmetry of this graph, we extend the method to guarantee the lower limit of the number of cables in each cabinet. The total cable length and cost can be minimized as well as minimizing the deterioration of communication delay. Compared with the conventional network topologies, the proposed network topology can attain higher performance with the smaller total cable length and cost.

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Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System

Ito K., Iizuka K., Hironaka K., Hu Y., Koibuchi M., Amano H.

A multi-FPGA System called Flow-in-Cloud (FiC) is currently being developed as an accelerator of Multi-access Edge Computing (MEC), which is one of the core 5G technologies. FiC is a system that consists of multiple mid-range FPGAs tightly connected by high-speed serial links. Since timing-critical jobs are assumed to be executed in MEC, a circuit-switched network with static time-division multiplexing (STDM) switches has been implemented on FiC. In this paper, we investigate the methods to enhance the interconnection performance of FiC. We proposed the link aggregation and the slot distribution for making the use of multiple lanes naturally supported with Aurora-IP and economical FireFly cables. We evaluated combinations of the techniques by using three practical applications on a real FiC prototype with 24 boards. When the number of slots is large and the number of packets is small, the slot distribution is sometimes more effective, while the link aggregation is superior for other most cases. As a result, the communication performance could be improved up to 3.01 times by using four lanes. Furthermore, we found that application designers can use enough resources even using four lanes and the link aggregation is better than the slot distribution.

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Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system

Yamauchi Y., Ahmed A.B., Hironaka K., Iizuka K., Amano H.

Although convolutional neural networks (CNNs) have plenty of parallelism, traditional layer-by-layer task division designs for multi-FPGA systems have the following problems: (1) The computational load of each layer is different from each other, so the execution time is dominated with the heaviest one. (2) Each FPGA must be designed independently, it means that we must design, generate and manage various configuration files. To address this problem, we propose a horizontal division method that enables us to use of a single design for each FPGA. All layers are divided horizontal direction of the target CNN, and a set of layers is implemented on an FPGA. It reduces the time of design as well as management costs for the execution. Also, since the weight data can be separated, the usage of local memory can be reduced. The apparent disadvantage of this method is that it requires all-to-all data communication between FPGA boards, and so it is not suitable to traditional multi-FPGA systems with a simple linear network. Here, we tried to apply the method to FiC (Flow-in-Cloud) which has a powerful network to enable efficient broadcasting. A simple CNN LeNet and a matrix multiplication for more practical fully connected layer is implemented on the FiC prototype. As a result of the evaluation, LeNet using 8 FP-GAs achieved 7.5 times faster than that with a single FPGA, and achieved 12.6 times faster than the optimized software of a high-end CPU.

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GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures

Kojima T., Doan N.A.V., Amano H.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE Transactions on Very Large Scale Integration (VLSI) Systems) 28 ( 11 ) 2383 - 2396 2020.11

ISSN 10638210

Coarse-grained reconfigurable architectures (CGRAs) are expected to be used for embedded systems, Internet of Things (IoT) devices, and edge computing thanks to their high-energy efficiency and programmability. In essence, a CGRA is an array of numerous processing elements. To exploit this abundant computation resource, a compiler for CGRAs has to fulfill more tasks compared that for general-purpose processors. Therefore, many studies have proposed optimization methods, especially for application mapping, because the performance and energy efficiency strongly depend on optimization at compile time. However, many works focus only on performance improvement or resource minimization, although such optimization objectives are not always appropriate when considering various use cases. In this work, we propose GenMap, an application mapping framework using multiobjective optimization based on a genetic algorithm so that users can set optimization criteria as needed. Besides, it provides aggressive power optimization using our dynamic power model and leakage minimization technique. The proposed method is applied to three fabricated CGRA chips for evaluation. Experimental results show that GenMap achieves 15.7% reduction of wire length while keeping processing element utilization when compared with conventional methods. In addition, according to real chip experiments, 12.1%-46.8% of energy consumption is reduced, and up to 2\times speedup is archived for several architectures when compared with other two approaches.

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FPGA Acceleration of ROS2-Based Reinforcement Learning Agents

Leal D.P., Sugaya M., Amano H., Ohkawa T.

Reinforcement learning agents have shown very good results in robot control and navigation tasks, allowing robots to learn how to interact with an environment appropriately in a model-free manner. However, real-world robot systems have strict latency, power, and cost constraints, thus requiring special hardware consideration for the demanding computations of neural networks. Furthermore, reinforcement learning networks should be able to interface efficiently with the various other robot components. To address these challenges, we propose a method for applying FPGA hardware accelerators to robotics reinforcement learning agents at the inference stage and seamlessly integrating the FPGA hardware module to the robot system by automatically wrapping it in a Robot Operating System 2 (ROS2) node. The proposed system is evaluated in three OpenAI gym control environments: Cartpole-v1, Acrobot-v1, and Pendulum-v0. In the evaluation, both quantized and non-quantized reinforcement learning neural networks are used, and the proposed FPGA system is observed to provide up to a 3.69x speed up and up to 52.7x better performance per watt when compared to an agent running on a ROS2 node on a modern CPU.

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A Method of Partitioning Convolutional Layer to Multiple FPGAs

Iizuka K., Ito K., Hironaka K., Amano H.

Proceedings - International SoC Design Conference, ISOCC 2020 (Proceedings - International SoC Design Conference, ISOCC 2020) 25 - 26 2020.10

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Nishio S., Pan Y., Satoh T., Amano H., Meter R.V.

ACM Journal on Emerging Technologies in Computing Systems (ACM Journal on Emerging Technologies in Computing Systems) 16 ( 3 ) 2020.07

ISSN 15504832

NISQ (Noisy, Intermediate-Scale Quantum) computing requires error mitigation to achieve meaningful computation. Our compilation tool development focuses on the fact that the error rates of individual qubits are not equal, with a goal of maximizing the success probability of real-world subroutines such as an adder circuit. We begin by establishing a metric for choosing among possible paths and circuit alternatives for executing gates between variables placed far apart within the processor, and test our approach on two IBM 20-qubit systems named Tokyo and Poughkeepsie. We find that a single-number metric describing the fidelity of individual gates is a useful but imperfect guide. Our compiler uses this subsystem and maps complete circuits onto the machine using a beam search-based heuristic that will scale as processor and program sizes grow. To evaluate the whole compilation process, we compiled and executed adder circuits, then calculated the Kullback-Leibler divergence (KL-divergence, a measure of the distance between two probability distributions). For a circuit within the capabilities of the hardware, our compilation increases estimated success probability and reduces KL-divergence relative to an error-oblivious placement.

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Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Usami K., Akiba S., Amano H., Ikezoe T., Hiraga K., Suzuki K., Kanda Y.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings) 2020.04

Non-volatile power gating introducing MTJ into a flip-flop is an attractive technique for IoT devices. However, the time required for a successful store operation to MTJs varies at non-volatile flip-flops (NVFFs) due to process and voltage variation. This paper describes implementation and real-chip evaluation of a non-volatile Coarse Grained Reconfigurable Array employing verify-and-retryable NVFF (VR-NVFF) circuits and two-step store (TSS) control by instructions of a microcontroller. Test chips fabricated in a 40nm CMOS/MTJ hybrid technology have demonstrated that the TSS approach using both 30ns/100ns store operations reduces power by 37-42% when running an image processing program at 100MHz.

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Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch

Itsubo T., Koibuchi M., Amano H., Matsutani H.

Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020 (Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020) 102 - 109 2020.03

A back-propagation algorithm following a gradient descent approach is used for training deep neural networks. Since it iteratively performs a large number of matrix operations to compute the gradients, GPUs (Graphics Processing Units) are efficient especially for the training phase. Thus, a cluster of computers each of which equips multiple GPUs can significantly accelerate the training phase. Although the gradient computation is still a major bottleneck of the training, gradient aggregation and parameter optimization impose both communication and computation overheads, which should also be reduced for further shortening the training time. To address this issue, in this paper, multiple GPUs are interconnected with a PCI Express (PCIe) over 10 Gbit Ethernet (10GbE) technology. Since these remote GPUs are interconnected via network switches, gradient aggregation and optimizers (e.g., SGD, Adagrad, Adam, and SMORMS3) are offloaded to an FPGA-based network switch between a host machine and remote GPUs; thus, the gradient aggregation and optimization are completed in the network. Evaluation results using four remote GPUs connected via the FPGA-based 10GbE switch that implements the four optimizers demonstrate that these optimization algorithms are accelerated by up to 3. 0x and 1. 25x compared to CPU and GPU implementations, respectively. Also, the gradient aggregation throughput by the FPGA-based switch achieves 98.3% of the 10GbE line rate.

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Body bias optimization for real-time systems

Torres C.C.C., Yasudo R., Amano H.

Journal of Low Power Electronics and Applications (Journal of Low Power Electronics and Applications) 10 ( 1 ) 2020.03

The energy of real-time systems for embedded usage needs to be efficient without affecting the system’s ability to meet task deadlines. Dynamic body bias (BB) scaling is a promising approach to managing leakage energy and operational speed, especially for system-on-insulator devices. However, traditional energy models cannot deal with the overhead of adjusting the BB voltage; thus, the models are not accurate. This paper presents a more accurate model for calculating energy overhead using an analytical double exponential expression for dynamic BB scaling and an optimization method based on nonlinear programming with consideration of the real-chip parameter constraints. The use of the proposed model resulted in an energy reduction of about 32% at lower frequencies in comparison with the conventional model. Moreover, the energy overhead was reduced to approximately 14% of the total energy consumption. This methodology provides a framework and design guidelines for real-time systems and computer-aided design.

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A generalized theory based on the turn model for deadlock-free irregular networks

Kawano R., Yasudo R., Matsutani H., Koibuchi M., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E103D ( 1 ) 101 - 110 2020

ISSN 09168532

Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve the performance of parallel applications. However, these networks usually suffer from deadlocks in routing packets when using a naive minimal path routing algorithm. To solve this problem, we focus attention on a lately proposed theory that generalizes the turn model to maintain the network performance with deadlock-freedom. The theorems remain a challenge of applying themselves to arbitrary topologies including fully irregular networks. In this paper, we advance the theorems to completely general ones. Moreover, we provide a feasible implementation of a deadlock-free routing method based on our advanced theorem. Experimental results show that the routing method based on our proposed theorem can improve the network throughput by up to 138 % compared to a conventional deterministic minimal routing method. Moreover, when utilized as the escape path in Duato’s protocol, it can improve the throughput by up to 26.3 % compared with the conventional up*/down* routing.

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Designing low-diameter interconnection networks with multi-ported host-switch graphs

Yasudo R., Nakano K., Koibuchi M., Matsutani H., Amano H.

Concurrency Computation (Concurrency Computation) 2020

ISSN 15320626

A host-switch graph was originally proposed as a graph that represents a network topology of a computer systems with 1-port host computers and (Formula presented.) -port switches. It has been studied from both theoretical and practical aspects in terms of the diameter, the average shortest path length, and the performance of real applications. In recent high-performance computing systems, however, a host computer is connected to multiple switches by using InfiniBand, NVSwitch, or Omni-Path, and consequently they provide high bandwidths. Since a host-switch graph cannot represent such systems, this article extends a host-switch graph so that it can represent such systems. As a result, a host-switch graph can include multi-ported hosts. Furthermore, we propose to use multi-port hosts for reducing the diameter. We show that the diameter minimization is equivalent to solving the degree diameter problem for bipartite graphs of diameter three. Our experimental results show that we can drastically reduce the diameter as well as increasing the bandwidth and improves performance of MPI applications by up to 162% as compared with networks with single-ported hosts.

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Implementation of FM-Index Based Pattern Search on a Multi-FPGA System

Ullah M.M.I., Ben Ahmed A., Amano H.

ISSN 03029743

Pattern matching is a versatile task which has a variety of applications including genome sequencing as a major application. During the analysis, short read mapping technique is used where short DNA sequences are mapped relative to a known reference sequence. This paper discusses the use of reconfigurable hardware to accelerate the short read mapping problem. The proposed design is based on the FM-index algorithm. Although several pattern matching techniques are available, FM-index based pattern search is perfectly suitable for genome sequencing due to the fastest mapping from known indices. In order to make use of inherent parallelism, a multi-FPGA system called Flow-in-Cloud (FiC) is used. FiC consists of multiple boards, mounting middle scale Xilinx’s FPGAs and SDRAMs, which are tightly coupled with high speed serial links. By distributing the input data transfer with I/O ring network and broadcasting I-Table, C-Table and Suffix-Array with the board-to-board interconnection network, about 10 times performance improvement was achieved when compared to the software implementation. Since the proposed method is scalable to the number of boards, we can obtain the required performance by increasing the number of boards.

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A coarse-grained reconfigurable architecture with a fault tolerant non-volatile configurable memory

Ikezoe T., Kojima T., Amano H.

Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019 (Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019) 2019-December 81 - 89 2019.12

Recent IoT devices require extremely low standby power consumption, while a certain performance is needed during the active time, and Coarse Grain Reconfigurable Arrays (CGRAs) are suitable because of their high energy efficiency. However, even in CGRAs, the leakage power for its configuration memory must be reduced. Although the power gating is a popular technique, the data in flip-flops and memory are lost so they must be retrieved after the wake-up. Recovering everything requires numerous state transitions and considerable overhead both on its execution time and energy. To address the problem, Non-volatile Cool Mega Array (NVCMA), a CGRA providing non-volatile flip-flops (NVFFs) with spin transfer torque type non-volatile memory (NVM) technology has been developed. However, in general, non-volatile memory technologies have problems with reliability. Some NVFFs are stacked-at-0/1, and cannot store the data in a certain possibility. To improve the chip yield, we propose a mapping algorithm to avoid faulty processing elements of the CGRA caused by the erroneous configuration data. Then, we also propose a method to add an error-correcting code (ECC) mechanism to NVFFs used for the configuration and constant memory. The proposed method was applied to NVCMA to evaluate the availability rate and reduction of write time. By using both methods, the 99.4% availability ratio is achieved with 0.1% probability of faulty FFs, while almost no chips are available without using them. The energy for storing data becomes about 2.28 times because of the hardware overhead of ECC but the proposed method can save 11.1% of the storing energy on average.

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A rapid optimization method for visual indirect SLAM using a subset of feature points

Kazami R., Amano H.

Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019 (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019) 275 - 279 2019.11

In this paper, we propose a novel optimization method for indirect Simultaneous Localization And Mapping(SLAM). This method avoids error-intended map points using a random subset of extracted feature points. As a result, this method making the calculation time short at the cost of some accuracy. The published code of ORB-SLAM2 has longer calculation time compared to other systems such as Semi-direct odometry(SVO). This is due to feature extraction time of an indirect method, which makes the indirect methods robust. However, considering CPU performance on edge devices like MAVs, a lightweight system is welcome. ORB-SLAM2 is widely known as a robust and rapid visual Simultaneous-Localization-And-Mapping (vSLAM) method than before. It extracts FAST feature points from a given image and optimizes using all of these points for camera-posing estimation. However, some points disturb accurate estimation causing large reprojection error after optimization. Although these points are eliminated as outliers after optimization, they may be an obstacle for accurate pose estimation. To make this system more robust and more rapid, We suggest an improved method to estimate camera-posing, where we use a subset of extracted points for estimation, avoiding mixing large-reprojection-error points in bundle adjustment. The experimental results on the SLAM benchmark dataset KITTI odometry demonstrated that the proposed method outperformed the original implementation of ORB-SLAM2 from the viewpoint of calculation time.

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Deadlock-free layered routing for infiniband networks

Kawano R., Matsutani H., Amano H.

End-to-end network latency has become an important issue for big data processing on large-scale and heterogeneous data centers. To realize them, a low-latency inter-switch network is required. In recent years, a novel network based on a random regular graph such as Jellyfish has been proposed as a solution to these problems. To realize this network on Infiniband, we explore layered shortest path routing that guarantees deadlock freedom. Infiniband can avoid deadlocks by using Virtual Lane (VL), which is a QoS guarantee mechanism. However, the output VL is indirectly determined by using Service Level (SL) held by each packet. In this research, to minimize the number of consumed SLs, we propose an algorithm based on a graph coloring problem to assign SLs to all source-destination pairs. The proposed method can reduce the number of consumed SLs by up to 38%compared to the conventional SL mapping method.

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Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel

Okamoto Y., Amano H.

Radiation transfer (RT) is an important physical processes of energy transfer in the form of electromagnetic wave, and ART method is a ray-tracing for computing RT of re-connected photons in the simulation of protogalaxies formation. It requires a heavy computational power and complicated memory accesses which are not suitable to acceleration with GPUs. Here, for the future use of FPGA-in-Cloud, the acceleration of ART method with SDAccel on Xilinx's cost efficient FPGA board KCU1500 was tried. Although the execution time was not reduced compared with the host CPU with various combination of derivatives, the energy consumption was reduced to 1/3.35.

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Real chip performance evaluation on through chip interface IP for renesas SOTB 65nm process

Kayashima H., Kojima T., Okuhara H., Shidei T., Amano H.

The building block computing system can build various systems by connecting small-sized chips with inductive coupling wireless chip-to-chip connection TCI (Through Chip Interface). First, we have developed TCI IP by using the Renesas 65nm SOTB process and verified it with a simple TEG chip. Then several family chips have been developed with the IP; Geyser-TT (MIPS R3000 compatible processor), SNACC (neural network accelerator), CC-SOTB2 (improved CGRA), KVS (the accelerator for Key-Value-Store database), and SMTT (Shared Memory for Twin Tower). All of these chips worked alone without problems. However, when these chips were stacked to construct a system, problems were found on some combination of chips that TCI did not operate as designed. To investigate the cause of the trouble, we have developed a sophisticated tester chip called the TCI Tester. It provides three modes: RAW mode in which handshake lines can be directly controlled, CUBE mode in which the TCI Tester can write the data into the stacked target chips, and LOOP mode which allows continuous write and read operation for a long time working test. Through the evaluation by using a two-TCI Tester stacking system, the following appeared. (1) The maximum transfer frequency of the TCI IP is much lower than 50MHz which is the target value. Only 14MHz for the downward and 9MHz for the upward. (2) The performance of the upward transfer is lower than that of the downward. The poor upward data transfer performance comes from that the voltage drop on the power grid becomes large because of the location of the upward transmitter coil. We can improve it by increasing the number of power pads for the transmitter and enhancing the power grid. However, with the low transfer frequency, the TCI IP worked more than a day continuously.

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A Preliminary evaluation of building block computing systems

Terashima S., Kojima T., Okuhara H., Musha K., Amano H., Sakamoto R., Kondo M., Namiki M.

Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019 (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019) 312 - 319 2019.10

A building block computing system with inductive coupling Through Chip Interface (TCI) consists of 3-D chip stack, each of which is small dedicated chips. By changing the combination of stacked chips, various types of systems can be built. A MIPS R3000 compatible processor GeyserTT, a neural network accelerator SNACC and the shared memory for building the twin-Tower of chips SMTT have been developed with a Renesas 65nm low leakage CMOS process. They provide the TCI IP (Intellectual Property), and an escalator network is built just by stacking them. This paper shows each chip evaluation results and performance estimation of stacking them with the RTL simulator. The performance of the single-Tower and twin-Tower configuration is estimated by RTL simulation when a part of Alexnet is implemented. The evaluation results showed that the single-Tower configuration with GeyserTT+SNACC achieved about twice performance as the case with GeyserTT. Also, experimental results using each of the single real chip showed that all of them work at least 50MHz with extremely low power consumption. The twin-Tower configuration achieved about 2x of the single-Tower, that is about 6x of GeyserTT. The power consumption was about 276mW for the single-Tower and 496mW for the twin-Tower.

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A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration

Okuhara H., Kazami R., Amano H.

In this work, we present a low-overhead performance monitor which can emulate the maximum operational frequency of a target system by utilizing a delay chain so as to achieve efficient adaptive voltage control. The proposed monitor can be fully built by logic cells provided by general PDKs; thus, an automatic cell-based design flow can be used for its implementation. In addition, interconnect delay behaviors can also be imitated by exploiting wires which are automatically routed. In order to validate our concept, the proposed monitor is fabricated with a 65-nm Fully Depleted Silicon on Insulator (FD-SOI) technology. Real chip experiments reveal that the automated layout design can achieve the reasonable ability to delay emulation. Indeed, when the maximum operational frequency of a CNN accelerator is emulated, the proposed SDM achieved several percents of the performance tracking error. Also, its power overhead is only few percents.

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A Stdm (static time division multiplexing) switch on a multi-fpga system

Azegami K., Musha K., Hironaka K., Ben Ahmed A., Koibuch M., Hu Y., Amano H.

FPGAs can be a promising accelerator used for MEC (Multi-Access Edge Computing) which provides timing critical services for a number of terminals at the base stations near from edges. Although a high-end FPGA can support a fixed latency computation with a relatively small power consumption, they are expensive and the available acceleration circuits are limited into a size of single FPGA. FiC (Flow-in-Cloud) has been developed for building a virtual large FPGA from a number of middle-range economical FPGAs connected with high speed serial links. Although the current target of FiC is cloud computing, it is more suitable for the future MEC, because huge hardware resource can be supported with small cost. One of the problem to use such multi-FPGA systems for timing critical computation is network uncertainty. With a common packet switching, the computation speed is influenced with the network traffic. That is, the fixed latency computation which could be supported by a single FPGA is hard to be supported with multi-FPGA systems using common packet switching networks. In order to address this problem, we introduced STDM (Static Time Division Multiplexing) switch in the FiC system. Since the STDM always supports a constant communication latency, transfer time can be estimated beforehand. Through the implementation of the STDM switch on the FPGA board for FiC, it appeared that the utilization ratio of the LUTs for the STDM switch is smaller than 14%. The required number of slots is less than 16 even for a system with 256 nodes. We implemented the Conjugate Gradient method, which includes all-To-All communication, on 4x2 FiC system. It achieved 17.9 times performance improvement of Intel E5-2667 2.90GHz CPU with 6 cores.

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Fpga/python co-design for lane line detection on a pynq-z1 board

Honda K., Wei K., Amano H.

This paper presents the implementation of lane line detection on FPGA and Python. Lane line detection consists of three functions, median blur, adaptive threshold, and Hough transform. We implemented only accumulation of Hough transform on FPGA. Although the Hough transform cannot be implemented on a low-end FPGA board if implemented directly, by reducing ρθ space, it was successfully implemented on a low-end FPGA board. The rest of the Hough transform was implemented using Python's NumPy and SciPy, and OpenCV. Although it was very easy to write, it did not become a bottleneck for the whole process because of its effectiveness. As a result, we could achieve a 3.9x speedup compared to OpenCV and kept the developing cost down. When implementing median blur and adaptive threshold on an FPGA, we could achieve a 6.34x speedup.

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Demonstration of flow-in-cloud: A multi-FPGA system

Hironaka K., Iizuka K., Ben Ahmed A., Imdad Ullah M.M., Yamauchi Y., Sun Y., Yamakura M., Hiruma A., Amano H.

Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019 (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019) 417 - 418 2019.09

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Demonstration of low power stream processing using a variable pipelined CGRA

Kojima T., Ando N., Matsushita Y., Amano H.

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Multi-FPGA Management on Flow-in-Cloud Prototype System

Hironaka K., Akram B.A., Amano H.

Proceedings - 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2019 (Proceedings - 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2019) 443 - 448 2019.07

FiC (Flow-in-Cloud) is a multi-FPGA system to achieve monolithic large scale FPGA with across multiple FPGAs for computational-heavy applications. The FiC system employs multiple economical mid-range FPGAs and connect them directly with flexible and high bandwidth interconnection network. We developed FiCSW board as a 1st generation of FPGA board in the FiC project. The FiCSW design, since the FPGA is used as both computational resource and the network circuit switch, there are no host server for FPGA needed like other server-based multi FPGA architecture. This design strategy helps scalable FPGA fabric in low-cost. However, from the system manageability's perspective, the strategy is hard to handle multiple FPGA nodes without management system. In this paper, we mainly focused on the management system on the FiCSW multi-FPGA system, introducing the system architecture and implementation, and working application on the FiCSW prototype system.

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Refinements in Data Manipulation Method for Coarse Grained Reconfigurable Architectures

Kojima T., Amano H.

Proceedings - 2019 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2019 (Proceedings - 2019 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2019) 113 - 120 2019.07

Coarse-grained reconfigurable architectures (CGRAs) is one of the suitable devices for IoT (Internet of Things) and edge-computing because of their high energy efficiency and programmability. The CGRAs process a compute-intensive part of an application program (especially a loop part) more efficiently than general purpose processors. CMA (Cool Mega Array) is an energy-conscious CGRA with a task-level reconfiguration instead of a cycle-level one. However, the CMA faces some limitations related to data management because of the aggressive pursuit of power saving. In this paper, we introduce a new CMA architecture VPCMA2 to relax the constraints and to improve energy efficiency. Then, we implement it with a 65-nm process technology to evaluate a hardware overhead due to the improvement. According to the evaluation results, the new design does not influence its maximum operating frequency. Although new functionalities brought about 17% power overhead and 10% area overhead, a remarkable improvement of application mappability and data handling was achieved.

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Acceleration of deep recurrent neural networks with an FPGA cluster

Sun Y., Ben Ahmed A., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 2019.06

In this paper, we propose an acceleration methodology for deep recurrent neural networks (RNNs) implemented on a multi-FPGA platform called Flow-in-Cloud (FiC). RNNs have been proven effective for modeling temporal sequences, such as human speech and written text. However, the implementation of RNNs on traditional hardware is inefficient due to their long-range dependence and irregular computation patterns. This inefficiency manifests itself in the proportional increase of run time with respect to the number of layers of deep RNNs when running on traditional hardware platforms such as a CPUs. Previous works have mostly focused on the optimization of a single RNN cell. In this work, we take advantage of the multi-FPGA system to demonstrate that we can reduce the run time of deep RNNs from O(k) to O(1).

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An ARM-based heterogeneous FPGA accelerator for hall thruster simulation

Noda H., Orsztynowicz M., Iizuka K., Miyajima T., Fujita N., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 2019.06

The Full Particle-In-Cell (Full-PIC) method is a numerical simulation technique used in the research and development of Hall-thrusters, a propulsion mechanism of satellites. The Japan Aerospace Exploration Agency (JAXA) has been developing a software package called NSRU-Full-PIC for the design of Hall thrusters. Since the numerical simulation of NSRU-Full-PIC requires a large computing power, energy efficient accelerators are essential. However, because of the frequent random memory access and Read-After-Write (RAW) hazard, acceleration with GPUs is difficult. In this paper, we tackle the problems by cooperating a CPU and an FPGA in an ARM-based heterogeneous FPGA accelerator. We use Intel’s mid-range SoC, Arria 10 which embeds floating point DSPs for high performance yet low power numerical computation. Intel FPGA SDK for OpenCL is available in the platform for easy offloading of complex tasks. Heavy load processes in NSRU-Full-PIC are implemented with a hardware/software co-design on Arria 10 SoC. Our implementation improved the power consumption by 5.66 times compared to the original code on a Xeon E5-2680 v2 2.8 GHz . The total energy consumption was reduced to 88.44% of the Xeon implementation. The target tasks become 3.48 times faster than the original code on an only ARM Cortex-A9 1.5 GHz in Arria 10 SoC, and 2.50 times faster than the implementation using atomic instructions on an NVIDIA K20c GPU.

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The evaluation of partial reconfiguration for a multi-board FPGA system FiCSW

Yamakura M., Hironaka K., Azegami K., Musha K., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 2019.06

FiC (Flow-in-Cloud) is a multi-FPGA system to realize a monolithic large FPGA image with multiple cost-efficient mid-range FPGAs connected withfl exible and high bandwidth interconnection network. The FPGA is used as both for computational resource and the network circuit switch, and separating FPGA regions by partial reconfiguration (PR) design technique. In this paper, we will introduce the FPGA design methodology with the PR technique for the FiC system. Evaluation result shows that the proposed design methodology reduces design and configuration time, and it enables to replace the region for computation without stopping the network running on the same FPGA.

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Sparse 3-D NoCs with inductive coupling

Koibuchi M., Leong L., Totoki T., Niwa N., Matsutani H., Amano H., Casanova H.

Proceedings - Design Automation Conference (Proceedings - Design Automation Conference) 2019.06

ISSN 0738100X

Wireless interconnects based on inductive coupling technology are compelling propositions for designing 3-D integrated chips. This work addresses the heat dissipation problem on such systems. Although effective cooling technologies have been proposed for systems designed based on Through Silicon Via (TSV), their application to systems that use inductive coupling is problematic because of increased wireless-communication distance. For this reason, we propose two methods for designing sparse 3-D chips layouts and Networks on Chip (NoCs) based on inductive coupling. The first method computes an optimized 3-D chip layout and then generates a randomized network topology for this layout. The second method uses a standard stack chip layout with a standard network topology as a starting point, and then deterministically transforms it into either a "staircase" or a "checkerboard" layout. We quantitatively compare the designs produced by these two methods in terms of network and application performance. Our main finding is that the first method produces designs that ultimately lead to higher parallel application performance, as demonstrated for nine OpenMP applications in the NAS Parallel Benchmarks.

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Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud

Yamauchi Y., Musha K., Amano H.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings) 2019.05

In order to cope with computation cost and energy required for the recent deep learning technology, domain specific systems have been used in the cloud computing so as to be shared by many application developers efficiently. Although GPU(Graphics Processing Unit)s and more specialized systems like TPU (Tensor Processing Unit)s have been popularly utilized, FPGAs have been receiving an attention especially for their power efficiency and flexibility. Since energy efficiency is one of the most important issues in recent cloud computing, a lot of researches to use FPGAs in the cloud have been asserted[3], and commercial systems including Amazon's F1 instance are available. However, the performance improvement in the FPGA is limited by the upper limit of the FPGA resource, even an FPGA in the cloud. Thus, in order to implement a large deep layer learning application, we must use an expensive high-end FPGA or adopt a lightweight algorithm sacrificing throughput and accuracy. To deal with this problem, in the project 'Power-saving AI engine and platform with heterogeneous engine integrated cloud' supported by NEDO started to develop a large-scale AI system called Flow-in-Cloud (FiC)[4]. FiC is consisting of a number of middle-scale economical FPGAs interconnected with high communication bandwidth network. From an HLS (High Level Synthesis) programmer, a lot of FPGAs can be handled as if they were a single large FPGA. The programmer can implement a large-scale deep learning model without caring resources on a single FPGA. FiC is managed by the Flow-OS, and shared efficiently by many users. Although FiC is designed to build a heterogeneous computing system, the current prototype is consisting of multiple FPGA boards called 'FiC-SW' each of which provides both the switching and computing capabilities. Here, as a case study of such an energy efficient multi-FPGA board computing, we implemented the inference part of Long Short Term Memory (LSTM) [1].

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Key-value Store Chip Design for Low Power Consumption

Tokusashi Y., Matsutani H., Amano H.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings) 2019.05

Low-power embedded systems often require simple but flexible functionality for data management. Key-value store is one of data stores, which provides simple API and is easy to scale-out. We developed a dedicated key-value store core as a low-power embedded storage. In this paper, key-value store chip is fabricated with Renesas SOTB 65-nm process technology. We evalute the real chip in terms of power consumption and operating frequency by tuning VDD and body bias voltage. The chip achieved 11.2mW as power consumption with 0.7V VDD if the target frequency is 40MHz. When data rate is low, the system can reduce power consumption by tuning VDD and body bias voltage.

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A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops

Ikezoe T., Amano H., Akaike J., Usami K., Kudo M., Hiraga K., Shuto Y., Yagami K.

2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018 (2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018) 2019.02

Recent IoT devices are required to be an extremely low power in idle time, while a certain performance is required in active time. NVCMA (Non-volatile Cool Mega Array) is a coarse-grain reconfigurable accelerator (CGRA) providing memory elements with spin transfer torque type non-volatile memory technology to keep data when the power gating is applied. Here, in order to reduce the energy for storing data into non-volatile Flip Flops (NVFF)s, a verification mechanism is introduced. The data are written with a storing time much shorter than usual. If the verification result is not correct, the next trial is done until all results are verified. This approach can omit unnecessary energy for using long writing time with margin considering variation and temperature. For NVCMA, we propose a power manager which controls store, restore, verification, sleep-down and wake-up by extending micro-instructions of the original CMA. Sophisticated power management both for storing data into NVFFs and power gating is integrated into the application program, and the content of data memory can be stored in NVFFs as required as well as configuration data and micro-instructions. Total NVFFs are divided into 10 independent domains which can be controlled independently. Power management instructions are designed so as to reduce the number of instructions as possible by using the bit-map registers and compound instructions. By using the short store with verification, the energy for storing data was reduced by 30% in average. The ever-on leakage power is just about 4% of the total leakage which can be saved by the power gating. Compared with the hard-wired implementation, the proposed power manager increases the area by 17.7%, yet the total area overhead is only 4%.

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Designing High-Performance Interconnection Networks with Host-Switch Graphs

Yasudo R., Koibuchi M., Nakano K., Matsutani H., Amano H.

IEEE Transactions on Parallel and Distributed Systems (IEEE Transactions on Parallel and Distributed Systems) 30 ( 2 ) 315 - 330 2019.02

ISSN 10459219

This paper aims at establishing a method for designing high-performance network topologies to bridge a gap between theoretical and practical studies. To this end, we present a novel graph called a host-switch graph, which consists of host vertices and switch vertices with maximum degree 1 and r, respectively. This graph represents a network topology of a practical parallel/distributed computer system with host computers connected by r-port switches. We discuss important metrics for designing high-performance interconnection networks: the host-to-host average shortest path length (h-ASPL) and the bisection width (BiW). In particular, we explore a method for constructing host-switch graphs with low h-ASPL and high BiW that connect the fixed number of hosts via any number of r-port switches. We demonstrate that the number of switches that provides the minimum h-ASPL can mathematically be approximated, and the minimum number of switches that provides a certain BiW can experimentally be approximated. On the basis of the approximations, we propose a randomized algorithm for searching host-switch graphs. We then apply the graphs to interconnection networks and compare them with typical network topologies. As compared with the torus, the dragonfly, and the fat-tree, our networks attain higher performance and smaller power and costs.

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A fine-grained multicasting of configuration data for coarse-grained reconfigurable architectures

Kojima T., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E102D ( 7 ) 1247 - 1256 2019

ISSN 09168532

A novel configuration data compression technique for coarse-grained reconfigurable architectures (CGRAs) is proposed. Reducing the size of configuration data of CGRAs shortens the reconfiguration time especially when the communication bandwidth between a CGRA and a host CPU is limited. In addition, it saves energy consumption of configuration cache and controller. The proposed technique is based on a multicast configuration technique called RoMultiC, which reduces the configuration time by multicasting the same data to multiple PEs (Processing Elements) with two bit-maps. Scheduling algorithms for an optimizing the order of multicasting have been proposed. However, the multicasting is possible only if each PE has completely the same configuration. In general, configuration data for CGRAs can be divided into some fields like machine code formats of general perpose CPUs. The proposed scheme confines a part of fields for multicasting so that the possibility of multicasting more PEs can be increased. This paper analyzes algorithms to find a configuration pattern which maximizes the number of multicasted PEs. We implemented the proposed scheme to CMA (Cool Mega Array), a straight forward CGRA as a case study. Experimental results show that the proposed method achieves 40.0% smaller configuration than a previous method for an image processing application at maximum. The exploration of the multicasted grain size reveals the effective grain size for each algorithm. Furthermore, since both a dynamic power consumption of the configuration controller and a configuration time are improved, it achieves 50.1% reduction of the energy consumption for the configuration with a negligible area overhead.

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Level-Shifter-Less Approach for Multi-V<inf>DD</inf> SoC Design to Employ Body Bias Control in FD-SOI

Usami K., Kogure S., Yoshida Y., Magasaki R., Amano H.

IFIP Advances in Information and Communication Technology (IFIP Advances in Information and Communication Technology) 500 1 - 21 2019

ISSN 18684238

Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) at pMOS transistors in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip showed that the chip applying the LSL approach correctly operates at VDDL = 0.6 V and VDDH = 1.2 V under 2 V pMOS RBB while suppressing the static dc current in the VDDH domain. We also demonstrate that adaptive RBB control for pMOS can maintain effectiveness of this approach under process and temperature variations.

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K-Optimized Path Routing for High-Throughput Data Center Networks

Kawano R., Yasudo R., Matsutani H., Amano H.

Proceedings - 2018 6th International Symposium on Computing and Networking, CANDAR 2018 (Proceedings - 2018 6th International Symposium on Computing and Networking, CANDAR 2018) 99 - 105 2018.12

Network throughput has become an important issue for big-data analysis on Warehouse-Scale Computing (WSC) systems. It has been reported that randomly-connected inter-switch networks can enlarge the network throughput. For irregular networks, a multi-path routing method called k-shortest path routing is conventionally utilized. However, it cannot efficiently exploit longer-than-shortest paths that would be detour paths to avoid bottlenecks. In this work, a novel routing method called k-optimized path routing to achieve high throughput is proposed for irregular networks. We introduce a heuristic to select detour paths that can avoid bottlenecks in the network to improve the network throughput. Experimental results show that the proposed k-optimized path routing can improve the throughput by up to 133 % compared to the conventional k-shortest path routing. Moreover, it can improve the network bandwidth while maintaining the low network latency.

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An extension of a temperature modeling tool hotspot 6.0 for castle-of-chips stacking

Totoki T., Koibuchi M., Amano H.

Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018 (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018) 363 - 369 2018.12

HotSpot is an open source analysis tool for estimating temperature of both 2D and 3D chip stacks. It counts both the primary path of the heat transfer through the heat-sink and the secondary path through the print circuit board. It can estimate the temperature of chips. However, HotSpot-6.0 cannot treat a complicated chip stacking such as the castle of chips (CoC) with inductive wireless coupling through-chip interface (TCI). Therefore, in this report we have extended the HotSpot simulator and updated it in order to evaluate CoC. Compared to the original HotSpot, the extended version of HotSpot had an average execution time increase of about 6% when evaluating the same vertical stacking. The execution time of CoC with the same number of chips is shorter than when executing vertical stacking, but when the number of layers is the same, the execution time is almost equal. Moreover, our design considers high productivity, e.g. it can easily set air cooling, oil cooling, water cooling evaluation and chip rotation setting.

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C4: An FPGA-based compression algorithm for expether

Shimura H., Noda H., Amano H.

PCI Express (PCIe) has been widely used as an I/O bus connecting CPU and GPUs. In order to resolve the limitation of the number of PCIe ports, NEC Corporation developed ExpEther for expanding PCIe to Ethernet. Since Ethernet often becomes a bottleneck of communication, a conventional research proposed to implement a compression/decompression mechanism by using existing data compression mechanisms to reduce the size of data transferring on Ethernet. However, data compression mechanisms used in the research were only efficient for a limited input data pattern. In this paper, we proposed a novel data compression algorithm called C4, and implemented it on Xilinx Virtex-7 FPGA as an experimental environment of ExpEther. As a result, the proposed method can reduce the transfer time by 52.5%, superior to 49.7% with the conventional method. According to the evaluation of the hardware resource utilization rate, we showed that the proposed algorithm can be implemented in the FPGA used in the ExpEther NIC.

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An trace-driven performance prediction method for exploring noc design optimization

Niwa N., Totoki T., Matsutani H., Koibuchi M., Amano H.

The performance prediction for a NoC-based Chip Multi-Processor (CMP) is one of the main design concerns. Generally, there is a trade-off between accuracy and time overhead on the performance prediction of computer systems. In particular, the time overhead is proportional or exponential to the number of cores when using a cycle-accurate full-system simulation, such as gem5. In this study, we propose an accurate and scalable method to predict the influence of design NoC parameters on its performance. Our method counts the number of execution cycles when employing the target NoC based on the statistics of one-time execution of a full-system simulation using a fully-connected NoC. To evaluate the accuracy and execution time overhead, we use the case that randomly generates allocations of processors with 3D mesh topology NoC. Its Mean Absolute Percentage Error of the estimated cycles is about 4.7%, and the Maximum Absolute Percentage Error is about 8.5%.

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FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks

Wei K., Honda K., Amano H.

Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018 (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018) 428 - 431 2018.12

We propose an autonomous vehicle controlled by FPGAs. In our design, considering embedded systems, we apply the binarized neural networks (BNNs) which can realize a satis-fying result in high speed and accuracy to recognize pedestrians and some obstacles on a given road. To detect the traffic light, a passive camera-based pipeline is applied. Furthermore, the implementation of road lane detection is based on color selection algorithm, Canny Edge Detection, and Hough Transformation. The proposed design is realized by two Xilinx boards: PYNQ-Z1 and Zynq-Xc7Z010. These two FPGA boards cooperate with each other through a shared network cable. In the proposed design, the resource used by Zynq-Xc7Z010 can be greatly reduced and the inference time on the FPGA has been thousands times faster than the software implementation.

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Performance Estimation for Exascale Reconfigurable Dataflow Platforms

Yasudo R., Coutinho J., Varbanescu A., Luk W., Amano H., Becker T.

Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018 (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018) 317 - 320 2018.12

The next generation high-performance computing platforms will need to support exascale computing. A promising path in achieving exascale is to embrace heterogeneity and specialised computing in the form of reconfigurable accelerators. However, assessing the feasibility of heterogeneous exascale systems requires fast and accurate performance prediction. This paper proposes PERKS, a novel performance estimation frame-work for reconfigurable dataflow platforms (RDPs). PERKS uses machine and application parameters to build an analytical model for predicting the performance of multi-Accelerator systems. Moreover, model calibration is automatic, making the model flexible and usable for different machine configurations and applications. Our experimental results demonstrate that PERKS can predict the performance of current workloads and RDPs with an accuracy above 95%. We also demonstrate how the modelling scales to exascale workloads and exascale platforms.

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Adaptive body bias control scheme for ultra low-power network-on-chip systems

Ben Ahmed A., Okuhara H., Matsutani H., Koibuchi M., Amano H.

Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018 (Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018) 146 - 153 2018.11

Over the past decade, the power consumption has been one of the main design challenges in Network-on-Chips (NoCs) as it significantly defines the performance of a given Chip-Multiprocessor (CMP). Body bias control is one of the solutions that provide an efficient trade-off between leakage power and performance. However, employing such a method is not straightforward since several factors should be taken into consideration, especially when adaptively implemented on-chip. In this paper, we propose a new router design and on-chip body bias control mechanism to adaptively control the body bias voltages supply in ultra low-power NoC systems. With the help of a light-weight monitoring circuit, the proposed router predicts the traffic load at each input-port and accordingly adjusts its pipeline depth in a fine-grained fashion. To satisfy the timing constraints, the router adaptively supplies each one of its input-ports with the appropriate body bias voltages to either boost the performance or to reduce the leakage power at the standby state. The evaluation results, using the SOTB 65nm Fully Depleted Silicon On Insulator (FD-SOI) technology, shows the ability of the proposed router in reducing both dynamic and static energies. When compared to two fixed-pipeline baseline routers (3-stages and 2-stages), the total energy reduction could reach up to 67% and 59%, respectively. At the same time, a reasonable performance tendency can be obtained with less than 6% area overhead.

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Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami K., Akaike J., Akiba S., Kudo M., Amano H., Ikezoe T., Hiraga K., Shuto Y., Yagami K.

Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018 (Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018) 91 - 98 2018.11

A non-volatile flip-flop (NVFF) introducing MTJ has many strong points in high endurance and read/write performance, and hence is very attractive as a component to be used for power gating of sequential circuits. However, large write-energy to MTJ becomes a big obstacle in achieving low energy dissipation. This paper proposes a NVFF circuit enabling to verify the success of a store operation to MTJ and retry it by prolonging the store time. We designed a NVFF circuit with this feature and applied it to 20,000 flip-flops in a dynamically reconfigurable processor (DRP). We conducted simulations considering write time variations caused by various factors such as process variations and thermal fluctuations. The results demonstrated that the proposed approach reduces store energy by 35-36% at four image-processing applications and the break-even time (BET) for non-volatile power gating is 2.0-2.9us at the 0.004% write error rate, at which no failures occur for the total number of NVFFs in the DRP.

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A configuration data multicasting method for coarse-grained reconfigurable architectures

Kojima T., Amano H.

Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018 (Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018) 239 - 242 2018.11

This paper proposes a novel configuration data compression technique for coarse-grained reconfigurable architectures (CGRAs). The proposed technique is based on a multicast configuration technique called RoMultiC, which reduces the configuration time by multicasting the same data to multiple PEs(Processing Elements) with two bit-maps. Scheduling algorithms for an optimizing the order of multicasting have been proposed. In general, configuration data for CGRAs can be divided into some fields like machine code formats. The proposed scheme confines a part of fields for multicasting so that the possibility of multicasting more PEs can be increased. This paper analyzes algorithms to find a configuration pattern which maximizes the number of multicasted PEs. We implemented the proposed scheme to CMA (Cool Mega Array), a straight forward CGRA as a case study. Experimental results show that the proposed method achieves 40.0% smaller configuration for an image processing application at maximum. Furthermore, it achieves 35.6% reduction of the power consumption for the configuration with a negligible area overhead.

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AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Ahmed A.B., Fujiki D., Matsutani H., Koibuchi M., Amano H.

2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018 (2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018) 2018.10

Various parallel applications, such as numerical convergent computation and multimedia processing, have intrinsic tolerance to inaccuracies that allow soft errors, i.e. bit flips, on a chip. However, existing Network-on-Chips (NoCs) guarantee error-free data transfer; thus, encountering limits to reduce the power consumption. In this context, we propose an approximate dual-voltage NoC, called AxNoC. An AxNoC router uses a per-flit look-ahead power management so that headers and important-data flits are perfectly transferred at a high voltage while the remaining flits may incur bit flips by decreasing the supply voltage. An AxNoC router isolates the critical path when the supply voltage is low since such a critical path is enabled only at high voltage. The critical path isolation enables low-voltage operation to work at the same operating frequency at high voltage. An AxNoC router was implemented using a 28nm process and the evaluation results illustrate its efficiency to reduce the power consumption reaching up to 43% while incurring a small area overhead that does not exceed 6.2%. We also demonstrate that AxNoC exhibits an acceptable accuracy illustrated in a sufficiently small geomean of error.

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Body Bias Control for Renewable Energy Source with a High Inner Resistance

Azegami K., Okuhara H., Amano H.

IEEE Transactions on Multi-Scale Computing Systems (IEEE Transactions on Multi-Scale Computing Systems) 4 ( 4 ) 605 - 612 2018.10

Sensor nodes used in Internet of Things (IoT) are required to work an extremely long time without replacing the battery. Natural renewable energy such as a solar battery is a hopeful candidate for such nodes. Here, a power model for operating an Silicon on Insulator (SOI) device with a solar battery including a large inner resistance is proposed, and applied to a micro-controller V850E-star and an accelerator CMA-SOTB2. Unlike the ideal case, the maximum operational frequency was achieved with reverse biasing by suppressing the leakage current which decreases the supply voltage. Under the room light with a large inner resistance, the strong reverse bias is effective, while a relatively weak reverse bias is advantageous under the bright light. The proposed model is appeared to be useful to estimate the appropriate body bias voltage both for V850E-star and CMA-SOTB2. In the V850E-star, the estimated operational frequencies were different from the real chip, while they were relatively matched when CMA-SOTB2 was used under the low illuminance.

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Performance Prediction for Large-Scale Heterogeneous Platforms

Yasudo R., Varbanescu A., Coutinho J., Luk W., Amano H.

Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018 (Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018) 2018.09

This paper presents an approach for analysing, modelling and predicting application performance of large-scale heterogeneous platforms. Our approach combines analytical and statistical modelling techniques, and aims to: (1) identify and characterise code regions that are the most promising candidates to benefit from acceleration; (2) provide statistical models that predict application behaviour for unobserved inputs; and (3) predict performance gain with different system architectures.

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Accelerator-in-Switch: a framework for tightly couple switching hub and an accelerator with FPGA

Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano

International Conference on Filed Programmable Logic and Applications 2018.09

Research paper (international conference proceedings), Joint Work, Accepted

Proxy responses by FPGA-based switch for MapReduce stragglers

Mitsuzuka K., Koibuchi M., Amano H., Matsutani H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E101D ( 9 ) 2258 - 2268 2018.09

ISSN 09168532

In parallel processing applications, a few worker nodes called "stragglers", which execute their tasks significantly slower than other tasks, increase the execution time of the job. In this paper, we propose a network switch based straggler handling system to mitigate the burden of the compute nodes. We also propose how to offload detecting stragglers and computing their results in the network switch with no additional communications between worker nodes. We introduce some approximate techniques for the proxy computation and response at the switch; thus our switch is called "ApproxSW." As a result of a simulation experiment, the proposed approximation based on task similarity achieves the best accuracy in terms of quality of generated Map outputs. We also analyze how to suppress unnecessary proxy computation by the ApproxSW. We implement ApproxSW on NetFPGA-SUME board that has four 10Gbit Ethernet (10GbE) interfaces and a Virtex-7 FPGA. Experimental results shows that the ApproxSW functions do not degrade the original 10GbE switch performance.

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Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU

Naoki Nishikawa, Hideharu Amano, Keisuke Iwai

International Conference on Network and System Security 2018.08

Research paper (international conference proceedings), Joint Work, Accepted

Optimization of Body Biasing for Variable Pipelined Coarse Grained Reconfigurable Architecture

Takuya Kojima, Naoki Ando, Anh Vu Doan, Hideharu Amano

IEICE Transactions on Information and Systems E10－D ( 6 ) 2018.08

Research paper (scientific journal), Joint Work, Accepted

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI systems

Okuhara Hayate, Ben Ahmed Akram, Hideharu Amano

IEEE Transactions on Circuits and Systems I: Regular Papers (IEEE Transactions on Circuits and Systems I: Regular Papers) 65 ( 10 ) 3241 - 3254 2018.08

Research paper (scientific journal), Joint Work, Accepted, ISSN 15498328

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Asymmetric Body Bias Control with Low-Power FD-SOI Technologies: Modeling and Power Optimization

Hayate Okuhara, A.Ben Arhmed , J.M.Muehn, Hideharu Amano

IEEE Transactions on VLSI Systems (IEEE Transactions on Very Large Scale Integration (VLSI) Systems) 26 ( 7 ) 1254 - 1267 2018.08

Research paper (scientific journal), Joint Work, ISSN 10638210

Body bias control is a fundamental technique widely used to provide an efficient tradeoff between leakage power and performance in ultralow-power systems. Therefore, a lot of research about power optimization which provides optimal power supply and body bias voltages has been carried out. However, considering the actual voltage sources, the conventional approaches suffer from limited performance/power control granularity and may lead to degradation in terms of the energy efficiency. Therefore, in this paper, a power optimization method that improves the performance/power control granularity is proposed and evaluated with real processor chips. In the proposed optimization, the body biases for nMOSFET and pMOSFET are controlled independently, while the conventional methods control them uniformly. This increases the number of possible voltage combinations and allows finer target frequency selection leading to lower power consumption than the conventional methods at the cost of the optimization complexity. In order to ease this complexity, the proposed optimization is based on simple power and delay models. The model-based optimization does not require brute force search in the phase of real chip testing; thus, the testing time and cost can be significantly reduced. Since the coefficients of the models are extracted with real chip measurements, the error of the model can be suppressed to a few percent in average. The proposed approach is validated by real chips implemented with a 65-nm fully depleted silicon on insulator technology. The evaluation results show that the proposed optimization is an efficient mean of power reduction for a leakage current dominant chip. In fact, when compared with the conventional method, the proposed approach achieves 9.617% of average power reduction reaching up to 22.77% in the case of the V850 microcontroller.

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Superpixel accelerator for computer vision applications on arria 10 SoC

Akagic A., Buza E., Turcinhodzic R., Haseljic H., Hiroyuki N., Amano H.

Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018 (Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018) 55 - 60 2018.07

Superpixel segmentation is a very popular image segmentation technique used in various computer vision tasks. Recently, a number of superpixel algorithms have been proposed in literature. One such algorithm is considered as the-state-of-the-art in superpixel segmentation: Simple Linear Iterative Clustering or SLIC. However, its original implementation has a long execution time on high performance processors designed within the common mobile and enterprise applications, as well on high-end processors such as Intel Xeon. Overall, the execution time for single-threaded implementation is considered critical for real-time or near real-time applications. In this paper, we explore the possibility of accelerating parts of the SLIC image segmentation critical for performance, by designing the image segmentation accelerator for Intel's Arria 10 SoC. We propose a novel architecture to enable hardware acceleration by addressing the problem of hardware/software partitioning to minimize the overall program latency.

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Real chip evaluation of a low power CGRA with optimized application mapping

Kojima T., Ando N., Matshushita Y., Okuhara H., Doan N.A.V., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 2018.06

Even though many optimization methods for CGRAs (Coarse-Grained Reconfigurable Architectures) have been proposed, aggressive power optimization still remains a complex problem to be solved. Moreover, the developments of these methods have mainly been proven on the basis of simulations. Therefore, the questions remains whether they can be applied for a real chip. Here, we consider a real implemented low power CGRA called CCSOTB2, and explore the possibility of the power reduction for this design. This paper proposes to use a metaheuristic method to optimize the power while considering all configurable factors of the CGRA, especially the mapping of an application. This methodology can generate mappings with their related pipeline structure and body bias control automatically. Optimized configurations to use on the real chip are obtained with this methodology and allow to measure the power consumption. The experimental results show a power reduction of 14.2% in average, when compared to a previously-used mapping method which cannot consider body bias and pipeline structure. In addition, the proposed method enables users to select a mapping from various solutions depending on performance requirement and trade-off possibilities (e.g. throughput vs power consumption).

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Design automation methodology of a critical path monitor for adaptive voltage controls

Kazami R., Okuhara H., Amano H.

21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings (21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings) 1 - 3 2018.06

The development of recent CMOS technologies such as Fully Depleted Silicon on Insulator (FD-SOI) allows VLSI systems to operate with lower power than the conventional bulk transistors [1, 2]. Thanks to its high degree of noise immunity, low power supply voltages (VDD) can be applied to the FD-SOI devices. Also, since the effect of body biasing is further endorsed in such devices, adaptive voltage control for both power supply voltage and body bias voltages (VBN for nMOS and VBP for pMOS) can be aggressively used.

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低電力再構成アクセラレータの実装と評価

増山滉一郎、藤田悠、奥原颯、天野英晴

電子情報通信学会論文誌 2018.06

Accepted

Optimization of body biasing for variable pipelined coarse-grained reconfigurable architectures

Kojima T., Ando N., Okuhara H., Doan N.A.V., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E101D ( 6 ) 1532 - 1540 2018.06

ISSN 09168532

Variable Pipeline Cool Mega Array (VPCMA) is a low power Coarse Grained Reconfigurable Architecture (CGRA) based on the concept of CMA (Cool Mega Array). It provides a pipeline structure in the PE array that can be configured so as to fit target algorithms and required performance. Also, VPCMA uses the Silicon On Thin Buried oxide (SOTB) technology, a type of Fully Depleted Silicon On Insulator (FDSOI), so it is possible to control its body bias voltage to provide a balance between performance and leakage power. In this paper, we study the optimization of the VPCMA body bias while considering simultaneously its variable pipeline structure. Through evaluations, we can observe that it is possible to achieve an average reduction of energy consumption, for the studied applications, of 17.75% and 10.49% when compared to respectively the zero bias (without body bias control) and the uniform (control of the whole PE array) cases, while respecting performance constraints. Besides, it is observed that, with appropriate body bias control, it is possible to extend the possible performance, hence enabling broader trade-off analyzes between consumption and performance. Considering the dynamic power as well as the static power, more appropriate pipeline structure and body bias voltage can be obtained. In addition, when the control of VDD is integrated, higher performance can be achieved with a steady increase of the power. These promising results show that applying an adequate optimization technique for the body bias control while simultaneously considering pipeline structures can not only enable further power reduction than previous methods, but also allow more trade-off analysis possibilities.

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An inductive-coupling link for 3-D Network-on-Chips

Kadomoto J., Amano H., Kuroda T.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 (Proceedings - International SoC Design Conference 2017, ISOCC 2017) 150 - 151 2018.05

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Building block operating system for 3D stacked computer systems with inductive coupling interconnect

Hamada S., Koshiba A., Namiki M., Amano H.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 (Proceedings - International SoC Design Conference 2017, ISOCC 2017) 157 - 158 2018.05

This paper describes the software system for the building block computing systems. The programs on the system are executed by the building block OS that manages configuration information of the 3D stacked chips and virtualizes the accelerators as the OpenCL functions. In addition, the OS controls the power supply of the chips implemented with SOTB (Silicon on Thin Box). This paper introduces the basic concepts and functions of the software systems for the building block computing systems.

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Building block multi-chip systems using inductive coupling through chip interface

Amano H., Kuroda T., Nakamura H., Usami K., Kondo M., Matsutani H., Namiki M.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 (Proceedings - International SoC Design Conference 2017, ISOCC 2017) 152 - 154 2018.05

A building block computing system is consisting of multiple chips connecting with inductive coupling wireless through chip interconnect. Like building Lego blocks, various types of systems can be built by stacking different types of chips. In order to develop such systems, several techniques are investigated in the project: that is, inductive coupling wireless through chip interface, low power circuit technologies, autonomous interconnection network architectures, thermal dissipation and building block operating system. Here, the overview of the project and a prototype system are introduced.

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Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yoshida Y., Usami K., Amano H.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 (Proceedings - International SoC Design Conference 2017, ISOCC 2017) 148 - 149 2018.05

Standard Cell based Memory (SCM) is drawing attention as a technique to use the standard digital design flow to realize embedded memory macros. One of the strong points of SCM is that it correctly operates at such low voltage that SRAM macros provided by vendors usually do not work. This paper describes a design of energy-efficient SCM using Silicon-on-Thin-BOX (SOTB). We present automatic layout methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Results from simulations and chip measurements have demonstrated effectiveness of this approach.

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Scalable deep neural network accelerator cores with cubic integration using through chip interface

Sakamoto R., Takata R., Ishii J., Kondo M., Nakamura H., Ohkubo T., Kojima T., Amano H.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 (Proceedings - International SoC Design Conference 2017, ISOCC 2017) 155 - 156 2018.05

Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embedded systems. Developing high-performance and power-efficient DNN engines becomes one of the important challenges for embedded systems. Since DNN algorithms or structures are frequently updated, flexibility and performance scalability to deal with various types of networks are crucial requirement of the DNN accelerator design. In this paper, we describe the architecture and LSI design of a flexible and scalable CNN accelerator called SNACC (Scalable Neuro Accelerator Core with Cubic integration) which consists of several processing cores, on-chip memory modules, and ThruChip Interface (TCI).

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HiRy: An advanced theory on design of deadlock-free adaptive routing for arbitrary topologies

Kawano R., Yasudo R., Matsutani H., Koibuchi M., Amano H.

Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS (Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS) 2017-December 664 - 673 2018.05

ISSN 15219097

Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve the performance of parallel application. However, these networks usually suffer from deadlocks in routing packets when using a naive minimal path routing algorithm. To solve this problem, we focus attention on a lately proposed theory that generalizes the turn model to maintain the network performance with deadlock-freedom. The theorems remain a challenge of applying themselves to arbitrary topologies including fully irregular networks. In this paper, we advance the theorems to completely general ones. To apply the idea of the turn model to arbitrary topologies, we introduce a concept of regions that define continuous directions of channels on an n-dimensional space. Moreover, we provide a feasible implementation of a deadlock-free routing method based on our advanced theorem. To reduce the latency and the number of required Virtual Channels (VCs) with this method, a heuristic approach is introduced to reduce the number of prohibited turns between channels. Experimental results show that the routing method based on our proposed theorem can improve the network throughput by up to 138 % compared to a conventional deterministic minimal routing method. Moreover, it can reduce the latency by up to 2.9 % compared to another fully adaptive routing method.

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A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface

Nomura A., Kadomoto J., Kuroda T., Amano H.

Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017 (Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017) 2018-January 126 - 131 2018.04

One of the benefits of wireless inductive through chip interface is that it allows to build a shared bus just by placing a coil on the same location in each chip. Since providing dedicated channels for arbitration is expensive, carrier sense multiple access with collision detection (CSMA/CD) is hopeful as the bus control method. Here, a rotationpersistent collision avoidance algorithm dedicated for the wireless inter-chip bus is proposed. In the method, after the carrier sense, only a specific chip can instantly send the data, and others must wait for a random time interval. It improved the throughput of 1-persistent CSMA/CD by 33% on average.

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Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach

Carlos Torres, Hayate Okuhara, Nobuyuki Yamasaki, Hideharu Amano

IEICE Transactions on Informations and Systems (IEICE Transactions on Information and Systems) E101-D ( 4 ) 1116 - 1130 2018.04

Research paper (scientific journal), Joint Work, ISSN 09168532

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The design and implementation of scalable deep neural network accelerator cores

Sakamoto R., Takata R., Ishii J., Kondo M., Nakamura H., Ohkubo T., Kojima T., Amano H.

Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 (Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017) 2018-January 13 - 20 2018.03

Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embeddedsystems. Developing high-performance and power-efficient DNN engines becomesone of the important challenges for embedded systems. Since DNN algorithms orstructures are frequently updated, flexibility and performance scalability todeal with various types of networks are crucial requirement of the DNNaccelerator design. In this paper, we describe the architecture and LSI designof a flexible and scalable CNN accelerator called SNACC (Scalable NeuroAccelerator Core with Cubic integration) which consists of several processingcores, on-chip memory modules, and ThruChip Interface (TCI). We evaluate thescalability of SNACC with detailed simulation varying the number of cores andoff-chip memory access bandwidth. The results show that the energy efficiency of the accelerator becomes the highest in eight cores configuration with500MB/s off-chip bandwidth.

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Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology

Cortes C., Amano H., Yamasaki N.

2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings (2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings) 2017-November 1 - 6 2018.03

It is essential for any embedded systems and increasing popularity of Internet of Things (IoT) be energy efficient. Such systems tend to work intermittently and reducing leakage in the idle time is essential. Energy reduction techniques bring the system to a low power mode which also provokes transition overheads. If such overheads are not considered, the task may not be schedulable under a given deadline. To get a gain in energy savings, the idle state must be longer than a minimum required time. This time is referred as Break Even Time (BET). To properly design efficient algorithms and schedulers we must calculate and include the BET. In this paper, we present the first studies to examine the BET using accurate parameters extracted from a real chip using Silicon On Thin Box (SOTB) technology employing Body Bias Control (BB) energy saving technique. In this study, we demonstrate the BET range for SOTB microcontrollers, on the order of 0.5ms up to 1ms.

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Level-shifter free approach for multi-V<inf>dd</inf> SOTB employing adaptive Vt modulation for pMOSFET

Usami K., Kogure S., Yoshida Y., Magasaki R., Amano H.

2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017) 2018-March 1 - 3 2018.03

This paper proposes a level-shifter free (LSF) approach for multi-VDD design to employ a combination of body bias control and a superior threshold-voltage (Vt) modulation capability of SOTB (Silicon on Thin BOX) devices. We applied this approach to a microprocessor test chip with low-voltage (VDDL) and high-voltage (VDDH) domains, and fabricated it in a 65nm SOTB technology. Measurement results demonstrated that the chip correctly operates at VDDL=0.6V and VDDH=1.2V under the reverse-body-bias (RBB) of 2V for pMOS transistors in the VDDH domain while suppressing the static dc current.

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FPGA-based accelerator for losslessly quantized convolutional neural networks

Sit M., Kazami R., Amano H.

2017 International Conference on Field-Programmable Technology, ICFPT 2017 (2017 International Conference on Field-Programmable Technology, ICFPT 2017) 2018-January 295 - 298 2018.02

Convolutional Neural Networks (CNN) have been widely used for various computer vision tasks. While GPUs are the most common platform for CNN implementation, FPGAs are promising alternatives to provide better energy efficiency. Recent work demonstrates the potential of network quantization to reduce the model size and enhance computation efficiency while maintaining comparable accuracy to the full precision counterparts. Quantized CNN is especially suitable for FPGA implementation due to the presence of values with non-trivial bitwidth. In this paper, we present the design of an FPGA-based accelerator for losslessly quantized CNNs using High Level Synthesis tool. The experiment result shows that our design achieves 12.9 GOPS/Watt for quantized Alexnet on Imagnet Dataset.

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Glitch-aware variable pipeline optimization for CGRAs

Kojima T., Ando N., Okuhara H., Amano H.

2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017 (2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017) 2018-January 1 - 6 2018.02

Although some coarse grained reconfigurable arrays (CGRAs) have a function to unify multiple processing elements (PEs) to enhance the energy efficiency, it sometimes causes propagation of glitches widely resulting in the power increases. We propose a dynamic power model considering glitches and an optimization technique using it for CGRAs. The model aims to estimate the energy consumption from the switching counts of a PE array approximately. The model and optimization were applied to a real chip of the low power CGRA called the VPCMA (Variable Pipeline Cool Mega Array). Compared with the energy estimation with a post-layout simulation, the model could estimate it with more than 10000 times faster with smaller error from the results of the real chip measurement. The optimized pipeline structure using the proposed method achived better energy consumption compared to fixed pitch pipeline structures in most cases.

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Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano

International Journal of Network and Computing Vol.8 ( 1 ) 124 - 139 2018.01

Research paper (scientific journal), Joint Work, Accepted

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano

International Journal of Network and Computing Vol.8 ( 1 ) 124 - 139 2018.01

Research paper (scientific journal), Joint Work, Accepted

Deep learning on high performance FPGA switching boards: Flow-in-cloud

Musha K., Kudoh T., Amano H.

ISSN 03029743

FiC (Flow-in-Cloud)-SW is an FPGA-based switching node for an efficient AI computing system. It is equipped with a number of serial links directly connected to other nodes. Unlike other multi-FPGA systems, the circuit switching fabric with the STDM (Static Time Division Multiplexing) is implemented on the FPGA for predictable communication and cost-efficient data broadcasting. Parallel convolution modules for AlexNet are implemented on FiC-SW1 prototype boards consisting of Kintex Ultrascale FPGA, and evaluation results show that the parallel execution with 20 boards achieved 4.6 times better performance than the state of art implementation on a single Virtex 7 FPGA board.

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Towards an optimized multi FPGA architecture with STDM network: A preliminary study

Hironaka K., Doan N.A.V., Amano H.

ISSN 03029743

In this work, we propose a multi FPGA architecture with STDM network that aims to tackle compute-intensive applications such as neural networks training or pattern recognition in artificial intelligence while realizing high cost-performance and energy efficiency. To achieve this goal, optimizing different aspects of the system communication is a key challenge. In order to do this, a preliminary study on the application mapping for both the execution time and the number of slots for the STDM is carried out. An optimization based on a multi-criteria paradigm is implemented and the preliminary results show the possibility to optimize several parameters of the communication simultaneously alongside quantitative analyses of different architecture choices.

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HiRy: An Advanced Theory on Design of Deadlock-free Adaptive Routing for Arbitary Topologies

R.Kawano, R.Yasudo, H.Matsutani, M.Koibuchi, H.Amano

International Conference on Parallel and Distributed Systems 2017.12

Research paper (international conference proceedings), Joint Work, Accepted

Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accerelator

Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano

IEICE Transactions on Information and Systems E100-D ( 12 ) 2828 - 2836 2017.12

Research paper (scientific journal), Accepted

Glidge aware variable pipeline optimization for CGRAs

T.Kojima, N.Ando, H.Okuhara, H.Amano

International Conference on ReConGigurable Computing and FPGAs 2017.12

Research paper (international conference proceedings), Joint Work, Accepted

The Design and Implementation of Scalable Deep Neural Network Accelerator Core

R.Sakamoto, R.Takata, J.Isihi, M.Kondo, H.Nakamura, T.Ohkubo, T.Kojima, H.Amano

IEEE International Symposium on Embedded Multicore/Many-core Systems-on-chip 2017.09

Research paper (international conference proceedings), Joint Work, Accepted

XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NOCs

Hiroshi Nakahara, N.V.A.Doan, Ryota Yasudo, Hideharu Amano

International Symposium on Network-on-Chip 2017.09

Research paper (international conference proceedings), Joint Work, Accepted

Multi-Objective Optimization for Application Mapping and Body Bias Control on a CGRA

N.A.V.Doan, Yusuke Matsushita, Naoki Ando, Hayate Okuhara, Hideharu Amano

IEEE International Symposium on Embedded Multicore/Many-core Systems on Chip (Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017) 2018-January 143 - 150 2017.09

Research paper (international conference proceedings), Joint Work, Accepted

Body biasing can be used to control the leakage power and the performance of transistors by changing the threshold voltage after fabrication. Especially, a new process called Silicon-On-Thin BOX (SOTB) CMOS can control the balance of these two factors. When it is applied to a Coarse-Grained Reconfigurable Array (CGRA), the leakage power can be largely reduced by controlling precisely the bias with small domain size. On the other hand, the choices on bias voltages depend on the application executed on the platform, especially its mapping. In this paper, we propose to apply a multi-objective optimization for the application mapping and the body bias control on an energy efficient CGRA called CC-SOTB (Cool Mega Array Cube-SOTB). By using an NSGA-II algorithm for the mapping exploration and Integer Linear Programming (ILP) for the body bias control optimization, we show that it is possible to achieve better power consumption results than in previous works. For instance, in the case of a domain size of 2 rows by 1 column, it is possible to achieve a power reduction ratio up to 43.25%, compared to 21.09% previously, for the studied application. This is however achieved at the cost of a bigger mapping width. Nonetheless, the exploration allows to have finer analyses about both mapping and consumption. Indeed, these promising results show that optimizing the application mapping simultaneously with the body bias control can provide more interesting results, giving deeper quantitative information about trade-off possibilities.

Access to Document (DOI)

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano

International Conference on Parallel Processing 2017.08

Research paper (international conference proceedings), Joint Work, Accepted

Performance Evaluation of PEACH3: Field Programmable Gate Array Switch for Tightly Coupled Accelerators

Takahiro Kaneda, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano

International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies 2017.06

Research paper (international conference proceedings), Accepted

Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL

Hiroyuki Noda, Ryotaro Sakai, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano

Proc. of International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2017) 2017.06

Research paper (international conference proceedings), Joint Work, Accepted

Power Optimization Methodology for Ultra Low Power Microcontroller with Silicon on Thin BOX MOSFET

H.Okuhara, Y.Fujita, K.Usami, H.Amano

IEEE Trans. on VLSI Systems 25 ( 4 ) 1578 - 1582 2017.04

Research paper (scientific journal), Joint Work, Accepted

Access to Document (DOI)

NAMACHA: A software edevelopment environment for a mutli-chip convolutional network accelerator

#H <T.Ohkubo, R.Takata, R.Sakamoto, M.Kondo, H.Amano/U>

CATA2017, 2017.03

Research paper (international conference proceedings), Joint Work, Accepted

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

R.Yasudo, H.Matsutani, M.Koibuchi, H.Amano, T.Nakamura

IEEE Trans. on Computers 66 ( 4 ) 702 - 716 2017.03

Research paper (scientific journal), Joint Work, Accepted

Access to Document (DOI)

High-Bandwidth Low-Latency Approximate Interconnection Networks

　Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi,

Proc. of the 23rd IEEE International Symposium on High-Performance Computer Architecture (HPCA'17) 2017.02

Research paper (international conference proceedings), Joint Work, Accepted

Novel Chips Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface

H.Nakahara, T.Ozaki, H.Matsutani, M.Koibuchi, H.Amano

IEICE Trans. on Information and Systems E99-D ( 12 ) 2871 - 2880 2016.12

Research paper (scientific journal), Joint Work, Accepted

“Variable Pipeline Structure for Coarse Grained Reconfigurable Array CMA

N.Ando, K.Masuyama, H.Okuhara, H.Amano,

Proc. of IEEE International Conference on Field Programmable Technologies 2016.12

Research paper (international conference proceedings), Joint Work, Accepted

An Inductive-Coupling Bus with Collision Detection Scheme Using Magnetic Field Variation for 3-D Network-on-Chips

J. Kadomoto, T. Miyata, H. Amano, T. Kuroda

Proc. of ASSCC2016 2016.12

Research paper (international conference proceedings), Joint Work

LOREN: A Scalable Routing Method for Layout-conscious Random Topologies

Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proc. of the 4th International Symposium on Computing and Networking (CANDAR), 2016.11

Research paper (international conference proceedings), Joint Work

Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface

Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano

Proc. of the 4th International Symposium on Computing and Networking (CANDAR) 2016.11

Research paper (international conference proceedings), Joint Work

On-the-fly data compression/decompression mechanism with ExpEther

Hideki Shimura, Takuji Mitsuishi, Masaki Kan, Takashi Yoshikawa, Hideharu Amano,

Proc. of the 4th International Symposium on Computing and Networking (CANDAR) 2016.11

Research paper (international conference proceedings), Joint Work

Acceleration of Full-PIC simulation on a CPU-FPGA tightly coupled environment

<Ryotaro Sakai, Naru Sugimoto, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano,

Proc. of IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2016.09

Research paper (international conference proceedings)

Body Bias Grain Size Exploration for a Coarse Grained Reconfigurable Accelerator

Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano and Hideharu Amano

Proc. of the 26th The International Conference on Field-Programmable Logic and Applications (FPL), 2016.09

Research paper (international conference proceedings), Joint Work

An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications

Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura and Mitaro Namiki

IEICE Trans. on Electronics E99-C ( 8 ) 926 - 035 2016.08

Research paper (scientific journal), Joint Work, Accepted

Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-power Network-on-Chips Systems

Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, and Hideharu Amano

IEICE Trans. on Electronics E99-C ( 8 ) 909 - 917 2016.08

Accepted

Performance Evaluation of PEACH3: an FPGA switch for tightly coupled accelerators

Takahiro Kaneda, Chiharu Tsuruta, Toshihiro Hanawa and Hideharu Amano

Proc. of International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2016), 2016.06

Research paper (international conference proceedings)

ACRO: Assignment of Channels in Reverse Order to Make Arbitrary Routing Deadlock-free

Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano

15th IEEE/ACIS International Conference on Computer and Information Science(ICIS) 2016.06

Research paper (international conference proceedings)

Leveraging FDSOI through Body Bias Domain Partitioning and Bias Search

Johannes Maximilian Kuehn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel

53nd Design Automation Conference(DAC) 2016.05

Research paper (international conference proceedings)

SOTB MOSFETを用いた汎用マイクロコントローラV850の動的ボディバイアス制御の検討

AMANO HIDEHARU

情報処理学会論文誌 57 ( 2 ) 708 - 717 2016.02

Research paper (scientific journal)

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

AMANO HIDEHARU

IEEE Transactions on VLSI Systems 24 ( 2 ) 493 - 506 2016.02

ISSN 1063-8210

A Fine-grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Unit

AMANO HIDEHARU

IEICE Transactions on Electronics. E980-C ( 7 ) 559 - 568 2015.08

Research paper (scientific journal), Joint Work, Accepted

Courier: A toolchain for acceleration on Heterogeneous Platforms

AMANO HIDEHARU

IPSJ Trans. on System LSI Design Methodology 8 ( 2 ) 153 - 162 2015.08

Research paper (scientific journal), Joint Work

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOA Technology with Reverse Body Bias Assisted Sleep Mode

AMANO HIDEHARU

IEICE Trans. on Electronics E98-C ( 2 ) 153 - 162 2015.02

Research paper (scientific journal)

A toolchain for Dynamic Function Off-load on CPU-FPGA Platforms

AMANO HIDEHARU

Journal of Information Processing (IPSJ) 23 ( 2 ) 153 - 162 2015.02

Research paper (scientific journal), Joint Work, Accepted

Access to Document (DOI)

A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA

Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano

International Journal of Networking and Computing 5 ( 1 ) 239 - 251 2015.01

Research paper (scientific journal), Joint Work, Accepted

Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs

Zhang Hao, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

IPSJ Transaction on System LSI Design Methodology 7 27 - 36 2014.07

Joint Work, Accepted

Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh

T.Akamine, M.S.Abu Talip, Y.Osana, N.Fujita, H.Amano

IEICE Trans. on INF & SYST. E97 ( 5 ) 1225 - 1234 2014.05

Research paper (scientific journal), Joint Work, Accepted

Access to Document (DOI)

複数コアリンクを用いた低遅延オンチップトポロジーに関する研究

R.Kawano, I.Fujiwara, H.Matsutani, H.Amano, M.Koibuchi

電子情報通信学会論文誌　D J97-D ( 3 ) 601 - 613 2014.03

Research paper (scientific journal), Joint Work, Accepted

3D NoC with Inductive-Coupling Links for Building-Blocks SiPs

Y.Take, H.Matsutani, D.Sasaki, M.Koibuchi, T.Kuroda, H.Amano

IEEE Transactio on Computers 63 ( 3 ) 748 - 763 2014.03

Research paper (scientific journal), Joint Work, Accepted

Access to Document (DOI)

A Scalaable 3D Heterogeneous Multicore with an Inductive ThruChip Interface 3D NoC

N.Miura, Y.Koizumi, Y.Take, H.Matsutani, T.Kuroda, H.Amano, R.Sakamoto, M.Namiki, K.Usami, M.Kondo, H.Nakamura

IEEE Micro 33 ( 6 ) 27 - 36 2013.12

Research paper (scientific journal), Joint Work, Accepted

Access to Document (DOI)

Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration

M.Sofian Abu Talip, T.Akamine, M.Hatto, Y.Osana, H.Amano

International Journmal of Networking and Computing 3 ( 3 ) 289 - 306 2013.08

Research paper (scientific journal), Joint Work, Accepted

Dynamic Power Consuption Optimization for Inductive Coupling based Wireless 3D NoCs

H.Zhang, H.Matsutani, M.Koibuchi, H.Amano

IPSJ Transactions on SLDM 7 27 - 36 2013.07

Research paper (scientific journal), Joint Work, Accepted

Access to Document (DOI)

High-Speed Fully-Adaptable CRC Accelerators

A.Akagic and H.Amano

IEICE Trans. Inf. and Syst. (IEICE) E96-D ( 6 ) 2013.06

Research paper (scientific journal), Joint Work, Accepted

Fine-Grained Run-Time Power Gating though Co-Optimization of Circuit, Architecture and System

H.Nakamura and W.Wang and Y.Ohta and K.Usami and H.Amano and M.Kondo and M.Namiki

IEICE Trans. Electron. (IEICE) E96-C ( 4 ) 404-412 2013.04

Research paper (scientific journal), Joint Work

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs

H.ZHang, H.Matsutani, Y.Take, T.Kuroda, H.Amano

IEICE Trans. on Inf. and Systems. E96-D ( 12 ) 2753 - 2764 2013

Research paper (scientific journal), Joint Work, Accepted

Partial reconfiguration of flux limiter functions in MUSCL scheme using FPGA

Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano

IEICE Transactions on Information & Systems E-95D ( 10 ) 2369 - 2376 2012.10

Research paper (scientific journal), Joint Work, Accepted

超低消費電力粗粒度アクセラレータCMAのPEアレイアーキテクチャの最適化

AMANO HIDEHARU

情報処理学会論文誌：コンピューティングシステム 5 ( 5 ) 10-22 2012.10

Research paper (scientific journal), Joint Work, Accepted

VLIW型プロセッサにおけるMixed Power Gatingの研究

AMANO HIDEHARU

情報処理学会論文誌：コンピューティングシステム５ ( ５ ) 23-32 2012.10

Research paper (scientific journal), Joint Work

Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor

Takao Toi and Takumi OKAMOTO and Toru AWASHIMA and Kazutoshi WAKABAYASHI and Hideharu Amano

IEICE Trans. on Informations and Systems (IEICE) E94-D ( 12 ) 2619-2627 2011.12

Research paper (scientific journal), Joint Work, Accepted

Cool Mega-Arrays: Ultra low-power reconfigurable accelerator Chips

Nobuaki Ozaki, Yoshihiro Yasuda, Yoshihiro Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano

IEEE Micro (IEEE) 32 ( 6 ) 6-18 2011.11

Research paper (scientific journal), Joint Work, Accepted

Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano and Tsutomu Yoshinaga

IEEE Trans. on Computers (IEEE) 60 ( 6 ) 783-799 2011.06

Research paper (conference, symposium, etc.), Joint Work

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units

Zhao Lei and Daisuke Ilebuchi and Kimiyoshi Usami and Mitaro Namiki and Masaaki Kondo and Hiroshi Nakamura and Hideharu Amano

IPSJ Trans. on System LSI Design Methodology (IPSJ) 4 ( 0 ) 182-192 2011.04

Research paper (conference, symposium, etc.), Joint Work

Performace, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power Gating Routers for CMPs

Hiroki Matsutani and Michihiro Koibuchi and Daisuke Ikebuchi and Kimiyoshi Usami and Hiroshi Nakamura and Hideharu Amano

IEEE Trans. on Computer-Aided Design of Integrated Circuits and systems (IEEE) 30 ( 4 ) 520-534 2011.04

Research paper (conference, symposium, etc.), Joint Work, Accepted

Design and Implementation of Echo Instructions for an Embedded Processor

Karaduman Arda and Stubdal Iver and Hideharu Amano

IPSJ Trans. on System LSI Design Methodology (IPSJ) 4 ( 0 ) 222-231 2011.04

Research paper (conference, symposium, etc.), Joint Work

A Switch-Tagged Routing Methodology for PC Clusters with VLAN Etnernet

MICHIHIRO KOIBUCHI, TOMOHIRO OTSUKA, TOMOHIRO KUDOH, AMANO HIDEHARU

IEEE Transactions on Parallel and Distributed Systems 22 ( 2 ) 231-244 2011.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

An Analytical Network Performance Model for SIMD Processor CSX600 Interconnects

Y.Nishikawa} and {M.Koibuchi} and {M.Yoshimi} and {K.Miura} and {H.Amano}AMANO

Journal of Systems Architecture 57 ( 1 ) 146‐159 2011.01

Research paper (conference, symposium, etc.), Joint Work, Accepted

Ｄｕａｌ－Ｖｔｈセルの利用による動的リコンフィギャラブルプロセッサのリーク電力削減手法

AMANO HIDEHARU

電子情報通信学会論文誌Ｊ９４－Ｄ ( 1 ) 301‐311 2011.01

Research paper (conference, symposium, etc.), Joint Work, Accepted

A Leakage Efficient Data TLB design for Embedded Processors

Zhao Lei and Hui Xu and Daisuke Ikebuchi and Tetsuya Sunata and Mitaro Namiki and Hideharu Amano

IEICE Trans. Inf.& Syst. Ｅ９４－Ｅ ( 1 ) 51‐59 2011.01

Research paper (conference, symposium, etc.), Joint Work, Accepted

動的リコンフィギャラブルデバイスにおけるデータパスコンフィギュレーションを用いた構成情報時間削減手法の提案

AMANO HIDEHARU

電子情報通信学会論文誌Ｊ９３－Ｄ ( 12 ) 2579‐2586 2010.12

Research paper (conference, symposium, etc.), Joint Work, Accepted

ＣＭＰにおけるオンチップルータの細粒度パワーゲーティングの評価

AMANO HIDEHARU

情報処理学会論文誌：コンピューティングシステム 3 ( 3 ) 100‐112 2010.09

Research paper (conference, symposium, etc.), Joint Work, Accepted

単フリット、単サイクルルータを用いたＮｏＣ向け非最短完全適応型ルーティング

AMANO HIDEHARU

情報処理学会論文誌：コンピューティングシステム 3 ( 3 ) 88‐99 2010.09

Research paper (conference, symposium, etc.), Joint Work, Accepted

MIPS R3000プロセッサにおける細粒度動的スリープ制御の実装と評価

AMANO HIDEHARU

電子情報通信学会論文誌Ｊ９３－Ｄ ( 6 ) 920‐930 2010.06

Research paper (conference, symposium, etc.), Joint Work, Accepted

動的リコンフィギャラブルデバイスにおける構成情報配送のためのマルチキャスト手法の検討

AMANO HIDEHARU

電子情報通信学会論文誌 J92-D ( 12 ) 2185-2194 2009.12

Research paper (conference, symposium, etc.), Joint Work, Accepted

動的リコンフィギャラブルデバイスにおける電力分析と低電力化手法の検討

AMANO HIDEHARU

電子情報通信学会論文誌 (電子情報通信学会論文誌) J92-D ( 10 ) 1763-1771 2009.10

Research paper (conference, symposium, etc.), Joint Work, Accepted

パイプラインステージ統合による省電力・可変パイプラインルータに関する研究

AMANO HIDEHARU

情報処理学会論文誌コンピューティングシステム 2 ( 3 ) 71-82 2009.09

Research paper (conference, symposium, etc.), Joint Work, Accepted

低遅延オンチップネットワークのための予測ルータの評価

AMANO HIDEHARU

情報処理学会論文誌コンピューティングシステム 2 ( 3 ) 26-38 2009.09

Research paper (scientific journal), Joint Work, Accepted

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network

HIROKI MATSUTANI, MICHIHIRO KOIBUCHI, YUTAKA YAMADA, D.Frank Hsu, AMANO HIDEHARU

IEEE Transaction on Paralel and Distributed Systems (IEEE) 20 ( 8 ) 1126-1141 2009.08

Research paper (conference, symposium, etc.), Joint Work, Accepted

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs

Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, AMANO HIDEHARU

IEICE Transaction on Information and Systems (IEICE) E92-D ( 4 ) 575-583 2009.04

Research paper (conference, symposium, etc.), Joint Work, Accepted

DIMMスロット搭載型ネットワークインタフェースDIMMnet-Iとその高バンド幅通信機構BOTF

田邊、山本、濱田、中條、工藤、天野

情報処理学会論文誌HPS 43 ( 4 ) 866－878 2002.04

Research paper (scientific journal), Single Work

L-turn routing: An Adaptive Routing in Irregular Networks

M.Koibuchi, A.Funahashi, A.Jouraku, H.Amano,

International Conference on Parallel Processing 374-383 2001.09

Research paper (conference, symposium, etc.), Joint Work, Accepted

Recursive　Diagonal　Torus:　an　interconnection　network　for　massively　parallel　computers

Y．Yang，A．Funahashi，A．Jouraku，H．Nishi，H．Amano，Ｔ．Sueyoshi

IEEE Trans. on Parallel and Distributed Systems (IEEE.Trans．on　Parallel　and　Distributed　Processing) 12 ( 7 ) 701-715 2001.07

Research paper (conference, symposium, etc.), Joint Work

L-turn routing: Irregular Network におけるAdaptive　Routing

鯉渕、舟橋、上楽、天野

情報処理学会論文誌　HPS (情報処理学会論文誌HPS3) 42 ( 9 ) 119-134 2001.07

Joint Work

データ駆動型ハードウェアにおける自動ページ分割手法

柴田、高山、岩井、天野

(情報処理学会論文誌) 2001.04

適応型ルーティングにおけるOutput　Selection　Functionに関する研究

鯉渕、舟橋、上楽、天野

情報処理学会論文誌 42 ( 4 ) 704－713 2001.04

Research paper (scientific journal), Single Work, Accepted

並列計算機シミュレータの構築支援環境

若林、天野

電子情報通信学会論文誌 Vol．J84-D-I ( No．3 ) 2001.03

Joint Work

A　prototype　chip　of　multicontext　FPGA　with　DRAM　for　Virtual　Hardware

D．Kawakami，Y．Shibata，H．Amano

Proc.　Of　ASP-DAC2001 2001.01

Research paper (conference, symposium, etc.), Joint Work, Accepted

On　the　fly　sending：A　Low　latency　high　bandwidth　Message　Transfer　Mechanism

N．Tanabe　et．ａｌ．

Proc．Of　IEEE　I-SPAN2000 2000.12

Research paper (conference, symposium, etc.), Joint Work, Accepted

64Mb/s Highly Reliable switch using parallel optical interconnection　

S.Nishimura, T.Kudoh, H.Nishi，J.Yamamoto, K.Hasegawa, N.Matsubara, S.Akutsu H.Amano

(IEEE Journal of Lightwave Technology) 2000.12

Joint Work

64Gb/s　Highly　Reliable　Network　Switch　Using　Parallel　Optical　Interconnection

Nishimura　ｅｔ．ａｌ．

Journal　of　Lightwave　Technology　 Vol．18 ( No．12 ) 2000.12

Joint Work

Environment　of　Multiprocessor　Simulator　Development

M．Wakabayashi，H．Amano　

Proc．Of　IEEE　I-SPAN2000 2000.12

Research paper (conference, symposium, etc.), Joint Work, Accepted

相互結合網RDTにおけるAdaptive Routing

舟橋、上楽、天野

電子情報通信学会論文誌 Vol．J83-D-I ( No．11 ) 2000.11

Joint Work

A　Local　Area　System　Network　RHiNET-1/SW:　A　Network　for　high　performance　parallel　computing

H．Nishi，　et．ａｌ．

Proc．Of　HPDS　2000 2000.08

Research paper (conference, symposium, etc.), Joint Work, Accepted

効率良い並列処理をサポートするローカルエリア向けネットワークスイッチ

電子情報通信学会論文誌 Vol. J83-D-I ( No.8 ) 2000.02

Joint Work

A　Floating　Point　Arithmetic　Unit　for　a　Static　Scheduling　and　Compiler　oriented　multiprocessor　system　ASCA

ASP　DAC　2000 2000.01

Joint Work, Accepted

A　Torus　Assignment　for　an　Interconnection　Network　Recursive　Diagonal　Torus

IEEE　International　Symposium　on　Parallel　Architectures，Algorithms，and　Networks(ISPAN99) 1999.11

Joint Work, Accepted

RHiNET：A　network　for　high　performance　parallel　computing　using　locally　distributed　computers

Innovative　Architecture　for　future　generation　high　performance　processors　and　systems 1999.10

Joint Work, Accepted

A　network　switch　using　optical　interconnection　for　high　performance　parallel　computing　

Parallel　Interconnect　99 1999.10

Joint Work, Accepted

Adaptive　Routing　on　the　Recursive　Diagonal　Torus

The　12th　ISCA　International　Conference　on　Parallel　and　Distributed　Computing　Systems 1999.08

Joint Work, Accepted

Internal　Parallelization　of　Data-Driven　Virtual　Hardware

International　Workshop　on　Parallel　Execution　on　Reconfigurable　Hardware 1999.08

Joint Work, Accepted

Implementation　and　Evaluation　of　the　Compiler　for　WASMII,　a　Virtual　Hardware　System

International　Workshop　on　Parallel　Execution　on　Reconfigurable　Hardware 1999.08

Joint Work, Accepted

An　educational　system　of　LSI　design　with　Free-wares　for　VDEC

IEEE　International　Conference　on　Microelectronic　Systems　Education 1999.07

Joint Work, Accepted

Home　Proxy　Cacheによる分散共有メモリの高速化

情報処理学会論文誌第40巻 ( ５号 ) 1999.05

Joint Work

オンチップマルチプロセッサ用半共有型擬似連想キャッシュ

情報処理学会論文誌第40巻 ( ５号 ) 1999.05

Joint Work

DRAM混載型FPGAを用いたデータ駆動型仮想ハードウェア

情報処理学会論文誌第40巻 ( ５号 ) 1999.05

Joint Work

MBP-light：Ａ　Processor　for　Management　of　the　Distributed　Shared　Memory　on　JUMP-1

COOL　Chips　II 1999.04

Joint Work, Accepted

Performance　evaluation　of　SNAIL：A　multiprocessor　based　on　the　ＳＳＳ　architecture

Parallel　Computing,25 1999.04

Joint Work

A Routing Algorithm for Multihop WDM Ring

IEICE Trans. Inf ＆ Syst. Vol.E82?D ( No.2 ) 1999

Joint Work

ローカルメモリを持つマルチプロセッサのソフトウェア環境EULASHのプリコンパイラの評価（その他）

山本淳二、鬼頭宏幸、美辺央希、山口喜弘、天野英晴

電子情報通信学会論文誌 D-Ⅰ Vol.J81-D-Ⅰ ( No.10 ) 1998.10

Joint Work

Pruning Cacheを用いた分散共有メモリのディレクトリ構成法

西村克信、工藤知宏、天野英晴

情報処理学会論文誌第39巻 ( 6 ) 1998.06

Joint Work

超並列計算機JUMP-1における分散共有メモリ管理プロセッサMBP-light

安生、井上、佐藤、工藤、天野、平木

情報処理学会論文誌第39巻 ( 6 ) 1998.06

Joint Work

多次元構造を持つMIN

塙敏博、朱笑岩、亀井貴之、天野英晴

情報処理学会論文誌第39巻 ( 6 ) 1998.06

Joint Work

Wavelength Division Multiple Access Ring

X. Dong, T. Kudoh, H. Amano

IEICE Trans. Inf and Syst. April 1998 E81-D ( No.4 ) 1998.04

Joint Work

FPGAを用いたマルコフチェーンシミュレーションシステム

電子情報通信学会論文誌D-Ⅰ Vol.J80 ( No.10 ) 1997.10

Joint Work

The RDT router chip:a versatile router for supporting a distributed shared memory

IEICE Trans.Inf.and Syst. Vol.E80-D ( No.9 ) 1997.09

Joint Work

MINC:Multistage Interconnection Network with Cache control mechanism

IEICE Trans.Inf.and Syst. Vol.E80-D ( No.9 ) 1997.09

Joint Work

IEEE標準バスFuturebusにおけるバスアービトレーションプロトコルの公平性とオーバーヘッドの解析

電子情報通信学会論文誌D-Ⅰ Vol.J80 ( No.5 ) 1997.05

Joint Work

The MDX:A Class of networks for large scale multiprocessors

A.Murata，T.Boku，H.Amano

IEICE Trans.Inf.and Syst. Vol.E79-D ( No.8 ) 1996.08

Joint Work

Fault Torelantce of the TBSF and PBSF

A.Funahashi，T.Hanawa，H.Amano

IEICE Trans.Inf.and Syst. Vol.E79-D ( No.8 ) 1996.08

Joint Work

相互結合網RDT上での階層マルチキャストによるメモリコヒーレンス維持手法

西村克信、工藤知宏、西宏章、天野英晴

情報処理学会論文誌 1996.07

Joint Work

シングルチップマルチプロセッサのためのスヌープキャッシュの検討

寺澤卓也、井上敬介、黒澤飛斗矢、天野英晴

電子情報通信学会論文誌 1996.04

Joint Work

Message Transfer Algorithms on the Recursive Diagonal Torus

Y.Yang， H. Amano

IEICE Trans. Inf. And Syst. ， Vol.E79-D ( No.2 ) 1996.02

Joint Work

An MPLD with Data-Driven Control on a Virtual Hardware

X.Ling， H.Amano

The Journal of Supercomputing， Vol.9 ( No.3 ) 1995.10

Joint Work

Neural network parallel computing for multi-layer channel routing problems

K.Suzuki，H.Amano，Y.Takefuji

Neurocomputing，8，（1995）， 141-156 1995.08

Joint Work

多重出力可能なMINの性能評価

塙敏博，天野英晴

情報処理学会論文誌, 36-7, 1630-1639 1995.07

Joint Work

SSS型MINに基づくマルチプロセッサSNAIL

笹原正司，寺田純，大和純一，塙敏博，天野英晴

情報処理学会論文誌, 36-7, 1640-1651 1995.07

Joint Work

A performance evaluation of the multiprocessor testbet ATTEMPT-0

T.Terasawa，O.Yamamoto，T.Kudoh，H.Amano

Parallel Computing, 21, 701-730 1995.05

Joint Work

超並列計算機向き結合網:RDT

楊愚魯，天野英晴，柴村英智，末吉敏則

電子情報通信学会論文誌 J78-D-I ( No.2 ) 118-128 1995.02

Joint Work

数値計算における疎密のある物理空間に対応するマッピング:ローリングマッピング

村田淳，天野英晴

情報処理学会論文誌 Vol.35 ( No.2 ) 1994.02

Joint Work

データ駆動型制御機構付きMPLDを用いた並列処理マシンWASMIIの仮想化

情報処理学会論文誌 Vol.35 ( No.4 ) 1994

Joint Work

SSS型MINにおけるhot　spotの影響とメッセージ結合の評価

電子情報通信学会論文誌D-I　 Vol.J77 ( No．５ ) 1994

Joint Work

WASMII：データ駆動型制御機構を持つMPLD

電子情報通信学会論文誌D-I　 Vol.J77 ( No．4 ) 1994

Joint Work

An Extended Fault-Tolerant Batcher Network

Chan，C.T.and Amano，H.

International Journal of MINI & Microcomputers 1993.10

Joint Work

SSS（Simple Serial Synchronized）型マルチステージネットワーク

天野英晴，藤川義文，周洛

情報処理学会論文誌 Vol.34 ( No.5 ) 1134-1143 1993.05

Joint Work

並列システム解析モデルSTMTネット

天野英晴，その他

電子情報通信学会論文誌D-I Vol.J75-D-I ( No.8 ) 654-663 1992.08

Joint Work

A Batcher-Double-Omega Network with Combining

天野英晴，その他

IEICE Trans.Inf.& Syst. ,May Vol.E75-D ( No.3 ) 307-314 1992.05

Joint Work

問い合わせに基づく並列論理シミュレーションアルゴリズム

天野英晴，その他

電子情報学会論文誌D-I Vol.J75-D-I ( No.4 ) 221-231 1992.04

Joint Work

バス結合型並列計算機の交信用メモリの性能評価

天野英晴，その他

情報処理学会論文誌第33巻 ( 3号 ) 307-319 1992.03

Joint Work

バチャー網の故障診断と回避法

電子情報通信学会論文誌D-I　 Vol.J75 ( No．11 ) 1992

Single Work

スタンフォード大学の並列計算機研究

天野英晴

情報処理 1991.12

Research paper (scientific journal), Single Work

（SM）2:A Large Scale Multiprocessor for Sparse Matrix Computation

天野英晴，朴泰佑，工藤知宏

IEEE Trans.on Computer 1990.07

Joint Work

マルチプロセッサのための科学技術計算用並行記述言語NCC

朴泰佑，天野英晴その他

電子情報通信学会論文誌 1989.10

Joint Work

The　Compatible　Acknowledging　Ethernet

IEICE　Trans Vol．E70 ( No．10 ) 1987

Joint Work

格子状トポロジーを持つ数値計算用並列計算機の動的な故障回復法

電子通信学会論文誌D 1985.06

Joint Work

マルチリードメモリを用いた並列計算機の性能解折

電子通信学会論文誌D 1984.09

Joint Work

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