Details of a Researcher - Amano, Hideharu

Papers - Amano, Hideharu

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A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface

Nomura A., Kadomoto J., Kuroda T., Amano H.

Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017 (Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017) 2018-January 126 - 131 2018.04

One of the benefits of wireless inductive through chip interface is that it allows to build a shared bus just by placing a coil on the same location in each chip. Since providing dedicated channels for arbitration is expensive, carrier sense multiple access with collision detection (CSMA/CD) is hopeful as the bus control method. Here, a rotationpersistent collision avoidance algorithm dedicated for the wireless inter-chip bus is proposed. In the method, after the carrier sense, only a specific chip can instantly send the data, and others must wait for a random time interval. It improved the throughput of 1-persistent CSMA/CD by 33% on average.

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Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach

Carlos Torres, Hayate Okuhara, Nobuyuki Yamasaki, Hideharu Amano

IEICE Transactions on Informations and Systems (IEICE Transactions on Information and Systems) E101-D ( 4 ) 1116 - 1130 2018.04

Research paper (scientific journal), Joint Work, ISSN 09168532

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The design and implementation of scalable deep neural network accelerator cores

Sakamoto R., Takata R., Ishii J., Kondo M., Nakamura H., Ohkubo T., Kojima T., Amano H.

Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 (Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017) 2018-January 13 - 20 2018.03

Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embeddedsystems. Developing high-performance and power-efficient DNN engines becomesone of the important challenges for embedded systems. Since DNN algorithms orstructures are frequently updated, flexibility and performance scalability todeal with various types of networks are crucial requirement of the DNNaccelerator design. In this paper, we describe the architecture and LSI designof a flexible and scalable CNN accelerator called SNACC (Scalable NeuroAccelerator Core with Cubic integration) which consists of several processingcores, on-chip memory modules, and ThruChip Interface (TCI). We evaluate thescalability of SNACC with detailed simulation varying the number of cores andoff-chip memory access bandwidth. The results show that the energy efficiency of the accelerator becomes the highest in eight cores configuration with500MB/s off-chip bandwidth.

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Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology

Cortes C., Amano H., Yamasaki N.

2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings (2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings) 2017-November 1 - 6 2018.03

It is essential for any embedded systems and increasing popularity of Internet of Things (IoT) be energy efficient. Such systems tend to work intermittently and reducing leakage in the idle time is essential. Energy reduction techniques bring the system to a low power mode which also provokes transition overheads. If such overheads are not considered, the task may not be schedulable under a given deadline. To get a gain in energy savings, the idle state must be longer than a minimum required time. This time is referred as Break Even Time (BET). To properly design efficient algorithms and schedulers we must calculate and include the BET. In this paper, we present the first studies to examine the BET using accurate parameters extracted from a real chip using Silicon On Thin Box (SOTB) technology employing Body Bias Control (BB) energy saving technique. In this study, we demonstrate the BET range for SOTB microcontrollers, on the order of 0.5ms up to 1ms.

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Level-shifter free approach for multi-V<inf>dd</inf> SOTB employing adaptive Vt modulation for pMOSFET

Usami K., Kogure S., Yoshida Y., Magasaki R., Amano H.

2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017) 2018-March 1 - 3 2018.03

This paper proposes a level-shifter free (LSF) approach for multi-VDD design to employ a combination of body bias control and a superior threshold-voltage (Vt) modulation capability of SOTB (Silicon on Thin BOX) devices. We applied this approach to a microprocessor test chip with low-voltage (VDDL) and high-voltage (VDDH) domains, and fabricated it in a 65nm SOTB technology. Measurement results demonstrated that the chip correctly operates at VDDL=0.6V and VDDH=1.2V under the reverse-body-bias (RBB) of 2V for pMOS transistors in the VDDH domain while suppressing the static dc current.

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FPGA-based accelerator for losslessly quantized convolutional neural networks

Sit M., Kazami R., Amano H.

2017 International Conference on Field-Programmable Technology, ICFPT 2017 (2017 International Conference on Field-Programmable Technology, ICFPT 2017) 2018-January 295 - 298 2018.02

Convolutional Neural Networks (CNN) have been widely used for various computer vision tasks. While GPUs are the most common platform for CNN implementation, FPGAs are promising alternatives to provide better energy efficiency. Recent work demonstrates the potential of network quantization to reduce the model size and enhance computation efficiency while maintaining comparable accuracy to the full precision counterparts. Quantized CNN is especially suitable for FPGA implementation due to the presence of values with non-trivial bitwidth. In this paper, we present the design of an FPGA-based accelerator for losslessly quantized CNNs using High Level Synthesis tool. The experiment result shows that our design achieves 12.9 GOPS/Watt for quantized Alexnet on Imagnet Dataset.

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Glitch-aware variable pipeline optimization for CGRAs

Kojima T., Ando N., Okuhara H., Amano H.

2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017 (2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017) 2018-January 1 - 6 2018.02

Although some coarse grained reconfigurable arrays (CGRAs) have a function to unify multiple processing elements (PEs) to enhance the energy efficiency, it sometimes causes propagation of glitches widely resulting in the power increases. We propose a dynamic power model considering glitches and an optimization technique using it for CGRAs. The model aims to estimate the energy consumption from the switching counts of a PE array approximately. The model and optimization were applied to a real chip of the low power CGRA called the VPCMA (Variable Pipeline Cool Mega Array). Compared with the energy estimation with a post-layout simulation, the model could estimate it with more than 10000 times faster with smaller error from the results of the real chip measurement. The optimized pipeline structure using the proposed method achived better energy consumption compared to fixed pitch pipeline structures in most cases.

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Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano

International Journal of Network and Computing Vol.8 ( 1 ) 124 - 139 2018.01

Research paper (scientific journal), Joint Work, Accepted

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano

International Journal of Network and Computing Vol.8 ( 1 ) 124 - 139 2018.01

Research paper (scientific journal), Joint Work, Accepted

Deep learning on high performance FPGA switching boards: Flow-in-cloud

Musha K., Kudoh T., Amano H.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)) 10824 LNCS 43 - 54 2018

ISSN 03029743

FiC (Flow-in-Cloud)-SW is an FPGA-based switching node for an efficient AI computing system. It is equipped with a number of serial links directly connected to other nodes. Unlike other multi-FPGA systems, the circuit switching fabric with the STDM (Static Time Division Multiplexing) is implemented on the FPGA for predictable communication and cost-efficient data broadcasting. Parallel convolution modules for AlexNet are implemented on FiC-SW1 prototype boards consisting of Kintex Ultrascale FPGA, and evaluation results show that the parallel execution with 20 boards achieved 4.6 times better performance than the state of art implementation on a single Virtex 7 FPGA board.

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Towards an optimized multi FPGA architecture with STDM network: A preliminary study

Hironaka K., Doan N.A.V., Amano H.

ISSN 03029743

In this work, we propose a multi FPGA architecture with STDM network that aims to tackle compute-intensive applications such as neural networks training or pattern recognition in artificial intelligence while realizing high cost-performance and energy efficiency. To achieve this goal, optimizing different aspects of the system communication is a key challenge. In order to do this, a preliminary study on the application mapping for both the execution time and the number of slots for the STDM is carried out. An optimization based on a multi-criteria paradigm is implemented and the preliminary results show the possibility to optimize several parameters of the communication simultaneously alongside quantitative analyses of different architecture choices.

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HiRy: An Advanced Theory on Design of Deadlock-free Adaptive Routing for Arbitary Topologies

R.Kawano, R.Yasudo, H.Matsutani, M.Koibuchi, H.Amano

International Conference on Parallel and Distributed Systems 2017.12

Research paper (international conference proceedings), Joint Work, Accepted

Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accerelator

Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano

IEICE Transactions on Information and Systems E100-D ( 12 ) 2828 - 2836 2017.12

Research paper (scientific journal), Accepted

Glidge aware variable pipeline optimization for CGRAs

T.Kojima, N.Ando, H.Okuhara, H.Amano

International Conference on ReConGigurable Computing and FPGAs 2017.12

Research paper (international conference proceedings), Joint Work, Accepted

The Design and Implementation of Scalable Deep Neural Network Accelerator Core

R.Sakamoto, R.Takata, J.Isihi, M.Kondo, H.Nakamura, T.Ohkubo, T.Kojima, H.Amano

IEEE International Symposium on Embedded Multicore/Many-core Systems-on-chip 2017.09

Research paper (international conference proceedings), Joint Work, Accepted

XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NOCs

Hiroshi Nakahara, N.V.A.Doan, Ryota Yasudo, Hideharu Amano

International Symposium on Network-on-Chip 2017.09

Research paper (international conference proceedings), Joint Work, Accepted

Multi-Objective Optimization for Application Mapping and Body Bias Control on a CGRA

N.A.V.Doan, Yusuke Matsushita, Naoki Ando, Hayate Okuhara, Hideharu Amano

IEEE International Symposium on Embedded Multicore/Many-core Systems on Chip (Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017) 2018-January 143 - 150 2017.09

Research paper (international conference proceedings), Joint Work, Accepted

Body biasing can be used to control the leakage power and the performance of transistors by changing the threshold voltage after fabrication. Especially, a new process called Silicon-On-Thin BOX (SOTB) CMOS can control the balance of these two factors. When it is applied to a Coarse-Grained Reconfigurable Array (CGRA), the leakage power can be largely reduced by controlling precisely the bias with small domain size. On the other hand, the choices on bias voltages depend on the application executed on the platform, especially its mapping. In this paper, we propose to apply a multi-objective optimization for the application mapping and the body bias control on an energy efficient CGRA called CC-SOTB (Cool Mega Array Cube-SOTB). By using an NSGA-II algorithm for the mapping exploration and Integer Linear Programming (ILP) for the body bias control optimization, we show that it is possible to achieve better power consumption results than in previous works. For instance, in the case of a domain size of 2 rows by 1 column, it is possible to achieve a power reduction ratio up to 43.25%, compared to 21.09% previously, for the studied application. This is however achieved at the cost of a bigger mapping width. Nonetheless, the exploration allows to have finer analyses about both mapping and consumption. Indeed, these promising results show that optimizing the application mapping simultaneously with the body bias control can provide more interesting results, giving deeper quantitative information about trade-off possibilities.

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Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano

International Conference on Parallel Processing 2017.08

Research paper (international conference proceedings), Joint Work, Accepted

Performance Evaluation of PEACH3: Field Programmable Gate Array Switch for Tightly Coupled Accelerators

Takahiro Kaneda, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano

International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies 2017.06

Research paper (international conference proceedings), Accepted

Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL

Hiroyuki Noda, Ryotaro Sakai, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano

Proc. of International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2017) 2017.06

Research paper (international conference proceedings), Joint Work, Accepted

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