Details of a Researcher - Amano, Hideharu

Papers - Amano, Hideharu

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AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Ahmed A.B., Fujiki D., Matsutani H., Koibuchi M., Amano H.

2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018 (2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018) 2018.10

Various parallel applications, such as numerical convergent computation and multimedia processing, have intrinsic tolerance to inaccuracies that allow soft errors, i.e. bit flips, on a chip. However, existing Network-on-Chips (NoCs) guarantee error-free data transfer; thus, encountering limits to reduce the power consumption. In this context, we propose an approximate dual-voltage NoC, called AxNoC. An AxNoC router uses a per-flit look-ahead power management so that headers and important-data flits are perfectly transferred at a high voltage while the remaining flits may incur bit flips by decreasing the supply voltage. An AxNoC router isolates the critical path when the supply voltage is low since such a critical path is enabled only at high voltage. The critical path isolation enables low-voltage operation to work at the same operating frequency at high voltage. An AxNoC router was implemented using a 28nm process and the evaluation results illustrate its efficiency to reduce the power consumption reaching up to 43% while incurring a small area overhead that does not exceed 6.2%. We also demonstrate that AxNoC exhibits an acceptable accuracy illustrated in a sufficiently small geomean of error.

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Body Bias Control for Renewable Energy Source with a High Inner Resistance

Azegami K., Okuhara H., Amano H.

IEEE Transactions on Multi-Scale Computing Systems (IEEE Transactions on Multi-Scale Computing Systems) 4 ( 4 ) 605 - 612 2018.10

Sensor nodes used in Internet of Things (IoT) are required to work an extremely long time without replacing the battery. Natural renewable energy such as a solar battery is a hopeful candidate for such nodes. Here, a power model for operating an Silicon on Insulator (SOI) device with a solar battery including a large inner resistance is proposed, and applied to a micro-controller V850E-star and an accelerator CMA-SOTB2. Unlike the ideal case, the maximum operational frequency was achieved with reverse biasing by suppressing the leakage current which decreases the supply voltage. Under the room light with a large inner resistance, the strong reverse bias is effective, while a relatively weak reverse bias is advantageous under the bright light. The proposed model is appeared to be useful to estimate the appropriate body bias voltage both for V850E-star and CMA-SOTB2. In the V850E-star, the estimated operational frequencies were different from the real chip, while they were relatively matched when CMA-SOTB2 was used under the low illuminance.

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Performance Prediction for Large-Scale Heterogeneous Platforms

Yasudo R., Varbanescu A., Coutinho J., Luk W., Amano H.

Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018 (Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018) 2018.09

This paper presents an approach for analysing, modelling and predicting application performance of large-scale heterogeneous platforms. Our approach combines analytical and statistical modelling techniques, and aims to: (1) identify and characterise code regions that are the most promising candidates to benefit from acceleration; (2) provide statistical models that predict application behaviour for unobserved inputs; and (3) predict performance gain with different system architectures.

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Accelerator-in-Switch: a framework for tightly couple switching hub and an accelerator with FPGA

Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano

International Conference on Filed Programmable Logic and Applications 2018.09

Research paper (international conference proceedings), Joint Work, Accepted

Proxy responses by FPGA-based switch for MapReduce stragglers

Mitsuzuka K., Koibuchi M., Amano H., Matsutani H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E101D ( 9 ) 2258 - 2268 2018.09

ISSN 09168532

In parallel processing applications, a few worker nodes called "stragglers", which execute their tasks significantly slower than other tasks, increase the execution time of the job. In this paper, we propose a network switch based straggler handling system to mitigate the burden of the compute nodes. We also propose how to offload detecting stragglers and computing their results in the network switch with no additional communications between worker nodes. We introduce some approximate techniques for the proxy computation and response at the switch; thus our switch is called "ApproxSW." As a result of a simulation experiment, the proposed approximation based on task similarity achieves the best accuracy in terms of quality of generated Map outputs. We also analyze how to suppress unnecessary proxy computation by the ApproxSW. We implement ApproxSW on NetFPGA-SUME board that has four 10Gbit Ethernet (10GbE) interfaces and a Virtex-7 FPGA. Experimental results shows that the ApproxSW functions do not degrade the original 10GbE switch performance.

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Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU

Naoki Nishikawa, Hideharu Amano, Keisuke Iwai

International Conference on Network and System Security 2018.08

Research paper (international conference proceedings), Joint Work, Accepted

Optimization of Body Biasing for Variable Pipelined Coarse Grained Reconfigurable Architecture

Takuya Kojima, Naoki Ando, Anh Vu Doan, Hideharu Amano

IEICE Transactions on Information and Systems E10－D ( 6 ) 2018.08

Research paper (scientific journal), Joint Work, Accepted

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI systems

Okuhara Hayate, Ben Ahmed Akram, Hideharu Amano

IEEE Transactions on Circuits and Systems I: Regular Papers (IEEE Transactions on Circuits and Systems I: Regular Papers) 65 ( 10 ) 3241 - 3254 2018.08

Research paper (scientific journal), Joint Work, Accepted, ISSN 15498328

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Asymmetric Body Bias Control with Low-Power FD-SOI Technologies: Modeling and Power Optimization

Hayate Okuhara, A.Ben Arhmed , J.M.Muehn, Hideharu Amano

IEEE Transactions on VLSI Systems (IEEE Transactions on Very Large Scale Integration (VLSI) Systems) 26 ( 7 ) 1254 - 1267 2018.08

Research paper (scientific journal), Joint Work, ISSN 10638210

Body bias control is a fundamental technique widely used to provide an efficient tradeoff between leakage power and performance in ultralow-power systems. Therefore, a lot of research about power optimization which provides optimal power supply and body bias voltages has been carried out. However, considering the actual voltage sources, the conventional approaches suffer from limited performance/power control granularity and may lead to degradation in terms of the energy efficiency. Therefore, in this paper, a power optimization method that improves the performance/power control granularity is proposed and evaluated with real processor chips. In the proposed optimization, the body biases for nMOSFET and pMOSFET are controlled independently, while the conventional methods control them uniformly. This increases the number of possible voltage combinations and allows finer target frequency selection leading to lower power consumption than the conventional methods at the cost of the optimization complexity. In order to ease this complexity, the proposed optimization is based on simple power and delay models. The model-based optimization does not require brute force search in the phase of real chip testing; thus, the testing time and cost can be significantly reduced. Since the coefficients of the models are extracted with real chip measurements, the error of the model can be suppressed to a few percent in average. The proposed approach is validated by real chips implemented with a 65-nm fully depleted silicon on insulator technology. The evaluation results show that the proposed optimization is an efficient mean of power reduction for a leakage current dominant chip. In fact, when compared with the conventional method, the proposed approach achieves 9.617% of average power reduction reaching up to 22.77% in the case of the V850 microcontroller.

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Superpixel accelerator for computer vision applications on arria 10 SoC

Akagic A., Buza E., Turcinhodzic R., Haseljic H., Hiroyuki N., Amano H.

Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018 (Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018) 55 - 60 2018.07

Superpixel segmentation is a very popular image segmentation technique used in various computer vision tasks. Recently, a number of superpixel algorithms have been proposed in literature. One such algorithm is considered as the-state-of-the-art in superpixel segmentation: Simple Linear Iterative Clustering or SLIC. However, its original implementation has a long execution time on high performance processors designed within the common mobile and enterprise applications, as well on high-end processors such as Intel Xeon. Overall, the execution time for single-threaded implementation is considered critical for real-time or near real-time applications. In this paper, we explore the possibility of accelerating parts of the SLIC image segmentation critical for performance, by designing the image segmentation accelerator for Intel's Arria 10 SoC. We propose a novel architecture to enable hardware acceleration by addressing the problem of hardware/software partitioning to minimize the overall program latency.

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Real chip evaluation of a low power CGRA with optimized application mapping

Kojima T., Ando N., Matshushita Y., Okuhara H., Doan N.A.V., Amano H.

ACM International Conference Proceeding Series (ACM International Conference Proceeding Series) 2018.06

Even though many optimization methods for CGRAs (Coarse-Grained Reconfigurable Architectures) have been proposed, aggressive power optimization still remains a complex problem to be solved. Moreover, the developments of these methods have mainly been proven on the basis of simulations. Therefore, the questions remains whether they can be applied for a real chip. Here, we consider a real implemented low power CGRA called CCSOTB2, and explore the possibility of the power reduction for this design. This paper proposes to use a metaheuristic method to optimize the power while considering all configurable factors of the CGRA, especially the mapping of an application. This methodology can generate mappings with their related pipeline structure and body bias control automatically. Optimized configurations to use on the real chip are obtained with this methodology and allow to measure the power consumption. The experimental results show a power reduction of 14.2% in average, when compared to a previously-used mapping method which cannot consider body bias and pipeline structure. In addition, the proposed method enables users to select a mapping from various solutions depending on performance requirement and trade-off possibilities (e.g. throughput vs power consumption).

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Design automation methodology of a critical path monitor for adaptive voltage controls

Kazami R., Okuhara H., Amano H.

21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings (21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings) 1 - 3 2018.06

The development of recent CMOS technologies such as Fully Depleted Silicon on Insulator (FD-SOI) allows VLSI systems to operate with lower power than the conventional bulk transistors [1, 2]. Thanks to its high degree of noise immunity, low power supply voltages (VDD) can be applied to the FD-SOI devices. Also, since the effect of body biasing is further endorsed in such devices, adaptive voltage control for both power supply voltage and body bias voltages (VBN for nMOS and VBP for pMOS) can be aggressively used.

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低電力再構成アクセラレータの実装と評価

増山滉一郎、藤田悠、奥原颯、天野英晴

電子情報通信学会論文誌 2018.06

Accepted

Optimization of body biasing for variable pipelined coarse-grained reconfigurable architectures

Kojima T., Ando N., Okuhara H., Doan N.A.V., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E101D ( 6 ) 1532 - 1540 2018.06

ISSN 09168532

Variable Pipeline Cool Mega Array (VPCMA) is a low power Coarse Grained Reconfigurable Architecture (CGRA) based on the concept of CMA (Cool Mega Array). It provides a pipeline structure in the PE array that can be configured so as to fit target algorithms and required performance. Also, VPCMA uses the Silicon On Thin Buried oxide (SOTB) technology, a type of Fully Depleted Silicon On Insulator (FDSOI), so it is possible to control its body bias voltage to provide a balance between performance and leakage power. In this paper, we study the optimization of the VPCMA body bias while considering simultaneously its variable pipeline structure. Through evaluations, we can observe that it is possible to achieve an average reduction of energy consumption, for the studied applications, of 17.75% and 10.49% when compared to respectively the zero bias (without body bias control) and the uniform (control of the whole PE array) cases, while respecting performance constraints. Besides, it is observed that, with appropriate body bias control, it is possible to extend the possible performance, hence enabling broader trade-off analyzes between consumption and performance. Considering the dynamic power as well as the static power, more appropriate pipeline structure and body bias voltage can be obtained. In addition, when the control of VDD is integrated, higher performance can be achieved with a steady increase of the power. These promising results show that applying an adequate optimization technique for the body bias control while simultaneously considering pipeline structures can not only enable further power reduction than previous methods, but also allow more trade-off analysis possibilities.

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An inductive-coupling link for 3-D Network-on-Chips

Kadomoto J., Amano H., Kuroda T.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 (Proceedings - International SoC Design Conference 2017, ISOCC 2017) 150 - 151 2018.05

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Building block operating system for 3D stacked computer systems with inductive coupling interconnect

Hamada S., Koshiba A., Namiki M., Amano H.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 (Proceedings - International SoC Design Conference 2017, ISOCC 2017) 157 - 158 2018.05

This paper describes the software system for the building block computing systems. The programs on the system are executed by the building block OS that manages configuration information of the 3D stacked chips and virtualizes the accelerators as the OpenCL functions. In addition, the OS controls the power supply of the chips implemented with SOTB (Silicon on Thin Box). This paper introduces the basic concepts and functions of the software systems for the building block computing systems.

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Building block multi-chip systems using inductive coupling through chip interface

Amano H., Kuroda T., Nakamura H., Usami K., Kondo M., Matsutani H., Namiki M.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 (Proceedings - International SoC Design Conference 2017, ISOCC 2017) 152 - 154 2018.05

A building block computing system is consisting of multiple chips connecting with inductive coupling wireless through chip interconnect. Like building Lego blocks, various types of systems can be built by stacking different types of chips. In order to develop such systems, several techniques are investigated in the project: that is, inductive coupling wireless through chip interface, low power circuit technologies, autonomous interconnection network architectures, thermal dissipation and building block operating system. Here, the overview of the project and a prototype system are introduced.

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Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yoshida Y., Usami K., Amano H.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 (Proceedings - International SoC Design Conference 2017, ISOCC 2017) 148 - 149 2018.05

Standard Cell based Memory (SCM) is drawing attention as a technique to use the standard digital design flow to realize embedded memory macros. One of the strong points of SCM is that it correctly operates at such low voltage that SRAM macros provided by vendors usually do not work. This paper describes a design of energy-efficient SCM using Silicon-on-Thin-BOX (SOTB). We present automatic layout methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Results from simulations and chip measurements have demonstrated effectiveness of this approach.

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Scalable deep neural network accelerator cores with cubic integration using through chip interface

Sakamoto R., Takata R., Ishii J., Kondo M., Nakamura H., Ohkubo T., Kojima T., Amano H.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 (Proceedings - International SoC Design Conference 2017, ISOCC 2017) 155 - 156 2018.05

Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embedded systems. Developing high-performance and power-efficient DNN engines becomes one of the important challenges for embedded systems. Since DNN algorithms or structures are frequently updated, flexibility and performance scalability to deal with various types of networks are crucial requirement of the DNN accelerator design. In this paper, we describe the architecture and LSI design of a flexible and scalable CNN accelerator called SNACC (Scalable Neuro Accelerator Core with Cubic integration) which consists of several processing cores, on-chip memory modules, and ThruChip Interface (TCI).

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HiRy: An advanced theory on design of deadlock-free adaptive routing for arbitrary topologies

Kawano R., Yasudo R., Matsutani H., Koibuchi M., Amano H.

Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS (Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS) 2017-December 664 - 673 2018.05

ISSN 15219097

Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve the performance of parallel application. However, these networks usually suffer from deadlocks in routing packets when using a naive minimal path routing algorithm. To solve this problem, we focus attention on a lately proposed theory that generalizes the turn model to maintain the network performance with deadlock-freedom. The theorems remain a challenge of applying themselves to arbitrary topologies including fully irregular networks. In this paper, we advance the theorems to completely general ones. To apply the idea of the turn model to arbitrary topologies, we introduce a concept of regions that define continuous directions of channels on an n-dimensional space. Moreover, we provide a feasible implementation of a deadlock-free routing method based on our advanced theorem. To reduce the latency and the number of required Virtual Channels (VCs) with this method, a heuristic approach is introduced to reduce the number of prohibited turns between channels. Experimental results show that the routing method based on our proposed theorem can improve the network throughput by up to 138 % compared to a conventional deterministic minimal routing method. Moreover, it can reduce the latency by up to 2.9 % compared to another fully adaptive routing method.

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