Papers - Amano, Hideharu
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Courier: A toolchain for acceleration on Heterogeneous Platforms
AMANO HIDEHARU
IPSJ Trans. on System LSI Design Methodology 8 ( 2 ) 153 - 162 2015.08
Research paper (scientific journal), Joint Work
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A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOA Technology with Reverse Body Bias Assisted Sleep Mode
AMANO HIDEHARU
IEICE Trans. on Electronics E98-C ( 2 ) 153 - 162 2015.02
Research paper (scientific journal)
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A toolchain for Dynamic Function Off-load on CPU-FPGA Platforms
AMANO HIDEHARU
Journal of Information Processing (IPSJ) 23 ( 2 ) 153 - 162 2015.02
Research paper (scientific journal), Joint Work, Accepted
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A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA
Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano
International Journal of Networking and Computing 5 ( 1 ) 239 - 251 2015.01
Research paper (scientific journal), Joint Work, Accepted
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Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs
Zhang Hao, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
IPSJ Transaction on System LSI Design Methodology 7 27 - 36 2014.07
Joint Work, Accepted
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Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh
T.Akamine, M.S.Abu Talip, Y.Osana, N.Fujita, H.Amano
IEICE Trans. on INF & SYST. E97 ( 5 ) 1225 - 1234 2014.05
Research paper (scientific journal), Joint Work, Accepted
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複数コアリンクを用いた低遅延オンチップトポロジーに関する研究
R.Kawano, I.Fujiwara, H.Matsutani, H.Amano, M.Koibuchi
電子情報通信学会論文誌 D J97-D ( 3 ) 601 - 613 2014.03
Research paper (scientific journal), Joint Work, Accepted
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3D NoC with Inductive-Coupling Links for Building-Blocks SiPs
Y.Take, H.Matsutani, D.Sasaki, M.Koibuchi, T.Kuroda, H.Amano
IEEE Transactio on Computers 63 ( 3 ) 748 - 763 2014.03
Research paper (scientific journal), Joint Work, Accepted
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A Scalaable 3D Heterogeneous Multicore with an Inductive ThruChip Interface 3D NoC
N.Miura, Y.Koizumi, Y.Take, H.Matsutani, T.Kuroda, H.Amano, R.Sakamoto, M.Namiki, K.Usami, M.Kondo, H.Nakamura
IEEE Micro 33 ( 6 ) 27 - 36 2013.12
Research paper (scientific journal), Joint Work, Accepted
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Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration
M.Sofian Abu Talip, T.Akamine, M.Hatto, Y.Osana, H.Amano
International Journmal of Networking and Computing 3 ( 3 ) 289 - 306 2013.08
Research paper (scientific journal), Joint Work, Accepted
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Dynamic Power Consuption Optimization for Inductive Coupling based Wireless 3D NoCs
H.Zhang, H.Matsutani, M.Koibuchi, H.Amano
IPSJ Transactions on SLDM 7 27 - 36 2013.07
Research paper (scientific journal), Joint Work, Accepted
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High-Speed Fully-Adaptable CRC Accelerators
A.Akagic and H.Amano
IEICE Trans. Inf. and Syst. (IEICE) E96-D ( 6 ) 2013.06
Research paper (scientific journal), Joint Work, Accepted
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Fine-Grained Run-Time Power Gating though Co-Optimization of Circuit, Architecture and System
H.Nakamura and W.Wang and Y.Ohta and K.Usami and H.Amano and M.Kondo and M.Namiki
IEICE Trans. Electron. (IEICE) E96-C ( 4 ) 404-412 2013.04
Research paper (scientific journal), Joint Work
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Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs
H.ZHang, H.Matsutani, Y.Take, T.Kuroda, H.Amano
IEICE Trans. on Inf. and Systems. E96-D ( 12 ) 2753 - 2764 2013
Research paper (scientific journal), Joint Work, Accepted
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Partial reconfiguration of flux limiter functions in MUSCL scheme using FPGA
Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
IEICE Transactions on Information & Systems E-95D ( 10 ) 2369 - 2376 2012.10
Research paper (scientific journal), Joint Work, Accepted
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超低消費電力粗粒度アクセラレータCMAのPEアレイアーキテクチャの最適化
AMANO HIDEHARU
情報処理学会論文誌：コンピューティングシステム 5 ( 5 ) 10-22 2012.10
Research paper (scientific journal), Joint Work, Accepted
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VLIW型プロセッサにおけるMixed Power Gatingの研究
AMANO HIDEHARU
情報処理学会論文誌：コンピューティングシステム ５ ( ５ ) 23-32 2012.10
Research paper (scientific journal), Joint Work
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Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor
Takao Toi and Takumi OKAMOTO and Toru AWASHIMA and Kazutoshi WAKABAYASHI and Hideharu Amano
IEICE Trans. on Informations and Systems (IEICE) E94-D ( 12 ) 2619-2627 2011.12
Research paper (scientific journal), Joint Work, Accepted
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Cool Mega-Arrays: Ultra low-power reconfigurable accelerator Chips
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshihiro Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano
IEEE Micro (IEEE) 32 ( 6 ) 6-18 2011.11
Research paper (scientific journal), Joint Work, Accepted
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Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors
Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano and Tsutomu Yoshinaga
IEEE Trans. on Computers (IEEE) 60 ( 6 ) 783-799 2011.06
Research paper (conference, symposium, etc.), Joint Work