研究発表 - 多田　宗弘

Low Temperature Boron Activation in Amorphous Germanium for Three Dimensional Integrated Circuits (3D-ICs) using Ni-induced Crystallization

J. H. Park, M. Tada, H. Y. Yu, D. Kuzum, Y. Na and K. Saraswat

Pacific Rim Meeting on Electrochemical and Solid-State Science (PRiME) 2008. (Hawaii, USA)., 

2008年10月

2008 International Conference on Solid State Devices and Materials, (Tsukuba, Japan), pp. 720-721.

M. Tada, N. Inoue, J. Kawahara, H. Yamamoto, F. Ito, T. Fukai, M. Ueki, S. Miyake, T. Takeuchi, S. Saito, M. Tagami, N. Furutake, K. Hijioka, T. Ito, Y. Shibue, T. Senou, R. Ikeda, N. Okada, and Y. Hayashi

2008 International Conference on Solid State Devices and Materials, (Tsukuba, Japan), pp. 720-721., 

2008年09月

Low Temperature Processes using Ni-induced Crystallization Technique for Monolithic Three Dimensional Integration

J. H. Park, M. Tada, H. Peng, and K. C. Saraswat

2008 International Conference on Solid State Devices and Materials, (Tsukuba, Japan), pp. 58-59., 

2008年09月

Low Temperature Single Crystal Germanium Growth on Amorphous Substrate Using Nano-patterning Technique and Metal(Au)-induced Lateral Crystallization (M(Au)ILC)

J. H. Park, P. Kapur, H. Peng, M. Tada, H. Y. Yu, and K. C. Saraswat,

Material Research Society (MRS) Spring meeting., 

2008年03月

Cost-effective and High　Performance Cu Interconnects (keff=2.75) with Continuous SiOCH Stack Incorporating a Low-k Barrier Cap (k=3.1)

M. Ueki, H. Yamamoto, F. Ito, J. Kawahara, M. Tada, T. Takeuchi, S. Saito, N. Fururake, T. Onodera, and Y. Hayashi

2007 IEEE International Electron Devices Meeting (IEDM), (Washington DC, USA), pp. 973-976., 

2007年12月

45nm-node interconnects with porous SiOCH-stacks, tolerant of low-cost packaging applications

Inoue, N. and Tagami, M. and Itoh, F. and Yamamoto, H. and Takeuchi, T. and Saito, S. and Furutake, N. and Ueki, M. and Tada, M. and Suzuki, T. and Hayashi, Y.

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers, 

2007年06月

, 

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

　概要を見る

The 45nm-node interconnect with porous SiOCH-stacks of keff=2.9 is confirmed to have the practical reliability in PGBA and QFP. Adhesion strength of the via-ILD to the lower SiCN capping layer significantly impacts on the wire-bond reliability, but spreading the contact area of the bonding-wire within the fine-pitched bonding-pad suppresses the bonding failures in the low-k stack structures, irrespective of additional process of low-k curing or not. No failure was detected during reliability tests in PBGA package as well as QFP, confirming the practicality of the low keff interconnects for 45nm-node ULSIs. © 2007 IEEE.

• Access to Document (DOI)

Highly-oriented PVD ruthenium liner for low-resistance direct-plated Cu interconnects

Abe, M. and Ueki, M. and Tada, M. and Onodera, T. and Furutake, N. and Shimura, K. and Saito, S. and Hayashi, Y.

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers, 

2007年06月

　概要を見る

Low-resistance Cu damascene interconnects have been developed with highly oriented PVD-Ru/TaN liner using a direct-plated Cu process. Texture of the direct-plated Cu on the Ru/TaN is strongly correlated with Ru(002) orientation, enriching Cu(111) texture comparable with a conventional plated-Cu film on seed-Cu/Ta/TaN. The resistivity of 0.2μm-wide direct-plated Cu lines with the highly (002)-oriented Ru/TaN liner at 20K is 12.4% lower than that of conventional Cu lines with Ta/TaN liner, meaning that the reduction of the resistivity in Cu lines with Ru liner at RT was achieved by smaller interface scattering besides the lower bulk resistivity of Ru than Ta. The orientation control of Ru liner is a key factor for the low-resistance Cu interconnects needed for scaled-down ULSI interconnects. © 2007 IEEE.

• Access to Document (DOI)

Plasma co-polymerization technology with molecular-level structure tightening in "in-situ" SiOCH stacks for 32nm-node Cu interconnects

Tada, M. and Yamamoto, H. and Ito, F. and Narihiro, M. and Ueki, M. and Inoue, N. and Abe, M. and Saito, S. and Takeuchi, T. and Furutake, N. and Onodera, T. and Kawahara, J. and Arai, K. and Kasama, Y. and Taiji, T. and Tohara, M. and Sekine, M. and Hayashi, Y.

Technical Digest - International Electron Devices Meeting, IEDM, 

2006年12月

　概要を見る

A novel plasma co-polymerization technology, using flexibly-mixed molecular gas of chain-type vinyl-siloxane and 6-membered ring-type one, has been developed for new Seamless Low-k SiOCH Stacks (SEALS). An ultimate high-modulus silica-amorphous-carbon-composite (SACC)-SiOCH film with 24.8GPa was realized by 100%-injection of the chain-type siloxane, adapting to the hard-mask on molecular-pore-stack (MPS) SiOCH film (k=2.45, 3.0GPa) from 100%-injection of the ring-type siloxane. For the via-dielectrics was utilized a new co-polymerized (CP) SiOCH film (k=2.8, 12.6GPa) from these gas mixture to enhance the mechanical strength. The in-situ sequential deposition of three kinds of films without air-break accomplished excellent adhesion, high quality interface and low O2 ashing damage. The fully-scaled-down, 32nm-node Cu interconnects achieved 83fF/mm (single-load) in 100nm-pitched Cu lines with the new co-polymerized SEALS.

• Access to Document (DOI)

Nano-Structural Control of Molecular-Pore Stacked (MPS) SiOCH Films Using Plasma Copolymerization Reaction

H. Yamamoto, F. Ito, M. Tada, T. Takeuchi, N. Furutake, and Y. Hayashi

Material Research Society (MRS) 2006 Fall Meeting., 

2006年11月

A Metallurgical Prescription for Electromigration (EM) Reliability Improvement in Scaled-down, Cu Dual Damascene Interconnects

M. Tada, M. Abe, H. Ohtake, N. Furutake, T. Tonegawa, K. Motoyama, M. Tohara, F. Ito, M. Ueki, T. Takeuchi, S. Saito, K. Fujii, M. Sekine, and Y. Hayashi

2006 International Interconnect Technology Conference, (Burlingame, USA), pp. 89-91., 

2006年06月

High-performance Cu-interconnects with Novel Seamless Low-k SiOCH Stacks (SEALS) Featured by Compositional Modulation Process for 45nm-Node ULSI Devices

M. Tagami, H. Ohtake, M. Tada, M. Ueki, F. Ito, T. Taiji, Y. Kasama, T. Iwamoto, H. Wakabayashi, T. Fukai, K. Arai, S. Saito, H. Yamamoto, M. Abe, M. Narihiro, N. Furutake, T. Onodera, T. Takeuchi, Y. Tsuchiya, N. Oda, M. Sekine, M. Hane, and Y. Hayashi

2006 Symposium on VLSI Technology (VLSI), (Hawaii, USA), pp. 108-109., 

2006年06月

A robust 45 nm-node, dual damascene interconnects with high quality Cu/barrier interface by a novel oxygen absorption process

Abe, M. and Tada, M. and Ohtake, H. and Furutake, N. and Narihiro, M. and Arai, K. and Takeuchi, T. and Saito, S. and Taiji, T. and Motoyama, K. and Kasama, Y. and Arita, K. and Ito, F. and Yamamoto, H. and Tagami, M. and Tonegawa, T. and Tsuchiya, Y. and Fujii, K. and Oda, N. and Sekine, M. and Hayashi, Y.

Technical Digest - International Electron Devices Meeting, IEDM, 

2005年12月

　概要を見る

By a novel oxygen absorption process, low oxygen-content Cu-alloy is implemented for fully-scaled-down, 45 nm-node dual damascene interconnects (DDIs) with 140 nm-pitched lines and 70 nmø-vias. In this process, a very thin metal film as an oxygen absorber, which has larger negative change in the standard Gibbs free energy of oxidation than a barrier metal, is put on a natural oxide at a surface of electro-plated, Cu film. The oxygen atoms diffuse to the oxygen absorber, not to the barrier metal under the Cu film, achieving high quality Cu/barrier interface after annealing. Combining the oxygen absorption process with Cu-alloy process, 45 nm-node DDI in molecular-pore-stacking (MPS) SiOCH film is successfully obtained with high endurances for SIV, EM and TDDB. © 2005 IEEE.

• Access to Document (DOI)

Via-Profile Controlled, Porous Low-k/Cu DDIs with High Thermal Stability

H. Ohtake, S. Saito, M. Tagami, M. Tada, M. Abe, N. Furutake, and Y. Hayashi

2005 International Conference on Solid State Devices and Materials, (Hyogo, Japan), pp. 300-301., 

2005年09月

Feasibility Study of a Novel Molecular-Pore-Stacking (MPS), SiOCH Film in Fully-scale-down, 45nm-node Cu Damascene Interconnects

M. Tada, H. Ohtake, M. Narihiro, F. Ito, T. Taiji, M. Tohara, K. Motoyama, Y. Kasama, M. Tagami, M. Abe, T. Takeuchi, K. Arai, S. Saito, N. Furutake, T. Onodera, J. Kawahara, K. Kinoshita, N. Hata, T. Kikkawa, Y. Tsuchiya, K. Fujii, N. Oda, M. Sekine, and Y. Hayashi

2005 Symposium on VLSI Technology (VLSI), (Kyoto, Japan), pp. 18-19., 

2005年06月

Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs

Ueki, M. and Narihiro, M. and Ohtake, H. and Tagami, M. and Tada, M. and Ito, F. and Harada, Y. and Abe, M. and Inoue, N. and Arai, K. and Takeuchi, T. and Saito, S. and Onodera, T. and Furutake, N. and Hiroi, M. and Sekine, M. and Hayashi, Y.

Digest of Technical Papers - Symposium on VLSI Technology, 

2004年06月

　概要を見る

Fully-scaled-down, 65nm-node Cu dual damascene interconnects (DDIs) with 180nm/200nm-pitched lines and 100nmφ-vias have been developed in full porous-SiOCH films (k=2.5). Two new techniques are introduced such as (1) a low thermal-budget process for securing the DDI via-yield without the Cu agglomeration, and (2) a "DD pore seal" covering all the side walls of the line-trenches and the vias for improving the dielectric reliability. The full porous-SiOCH DDI with the thin Ta/TaN barrier improves the overall RC product by 24% against the porous-on-rigid, hybrid single damascene interconnects (SDIs). The cost-effective, DDIs with keff ∼3.0 is applicable especially for the 65nm-node, low-power ASICs.

• Access to Document (DOI)

Novel molecular-structure design for PECVD porous SiOCH films toward 45nm-node, ASICs with k=2.3

Hayashi, Y. and Itoh, F. and Harada, Y. and Takeuchi, T. and Tada, M. and Tagami, M. and Ohtake, H. and Hijioka, K. and Saito, S. and Onodera, T. and Hara, D. and Tokudome, K.

Proceedings of the IEEE 2004 International Interconnect Technology Conference, 

2004年

　概要を見る

A porous SiOCH film with k=2.3 is developed by a new concept PECVD, in which pore-involved molecules are piled up together to deposit a "molecular-pore stacked, SiOCH (MPS)" film. The pore size and the density of the film are controlled by designing the pore size and the steric-hindrance side-chains of the source molecules. A newly synthesized, 6-member ring-type, organo-siloxane with the side-chains of large steric-hindrance hydrocarbons realizes the MPS film with k=2.3. The basic feasibility of the MPS film is confirmed through the integration into Cu damascene interconnects. The MPS film is a strong candidate for the low-k, inter-metal-dielectrics in 45nm-node, ASICs.

• Access to Document (DOI)

A 65nm-node, Cu Interconnect Technology Using Porous Sioch Film (k=2.5) Covered with Ultra-Thin, Low-k Pore Seal (k=2.7)

Tada, M. and Harada, Y. and Tamura, T. and Inoue, N. and Ito, F. and Yoshiki, M. and Ohtake, H. and Narihiro, M. and Tagami, M. and Ueki, M. and Hijioka, K. and Abe, M. and Takeuchi, T. and Saito, S. and Onodera, T. and Furutake, N. and Arai, K. and Fujii, K. and Hayashi, Y.

Technical Digest - International Electron Devices Meeting, 

2003年12月

　概要を見る

A highly reliable, 65nm-node Cu interconnect technology has been developed with 180nm/200nm-pitched lines connected through φ100nm-vias. A porous SiOCH film (k=2.5) with sub-nanometer pores is introduced for the inter-metal dielectrics (IMD) on a non-porous, rigid SiOCH film (k=2.9) for the via-intra-line dielectrics (via-ILD). A key breakthrough is a special pore-seal technique, in which the trench-etched surface of the porous SiOCH is covered with an ultra-thin, low-k organic silica film (k=2.7), thus improving the line-to-line TDDB reliability of the narrow-pitched Cu lines. The fully-scaled-down, 65nm-node Cu interconnects with the porous-on-rigid SiOCH hybrid structure achieve excellent performance and reliability.

Highly thermal-stable, plasma-polymerized BCB polymer film

Kawahara, J. and Nakano, A. and Kinoshita, K. and Harada, Y. and Tagami, M. and Tada, M. and Hayashi, Y.

Plasma Sources Science and Technology, 

2003年11月

　概要を見る

A new plasma-enhanced organic monomer-vapour polymerization (plasma polymerization) method has been developed. It was used to make a divinyl siloxane bis-benzocyclobutene (DVS-BCB) polymer film for Cu dual-damascene interconnects that had high thermal stability and a low dielectric constant, k = 2.6. The method consists of the vaporization of organic monomers, transportation of monomers in the gas phase, and polymerization by plasma to make the polymer film. The method eliminates polymer oxidation of DVS-BCB during the polymerization in high vacuum, which improves the film's thermal stability. The thermal stability of plasma-polymerized BCB (p-BCB) exceeded 400°C because of the higher deposition temperature, and the film had a high resistance to Cu diffusion at 400°C annealing. The narrow-pitched Cu/BCB damascene lines showed a 35% reduction in line capacitance compared with Cu/SiO 2 ones. The p-BCB is shown to be a strong candidate for Cu/low-k interconnects.

• Access to Document (DOI)

Improvement of TDDB reliability in Cu damascene interconnect by using united hard-mask and Cap (UHC) structure

Tada, M. and Harada, Y. and Ohtake, H. and Saito, S. and Onodera, T. and Hayashi, Y.

Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003, 

2003年

　概要を見る

Reliably of Cu damascene interconnects (DDIs) using United Hard-mask and Cap (UHC) structure, which involves the same material for both Hard-mask and Cap layers is investigated. Line-to-line insulating reliabilities such as a leakage current, TZDB and TDDB are greatly improved by using the UHC structure even without any barrier metal layers, indicating that the interline leakage path is not in a bulk of the low-k dielectric but the interface between the Cap and the CMP-damaged Hard-mask. This new Cu dual damascene interconnect with UHC provides the interconnect reliability of future ULSIs with ultra-thin barrier metals toward a barrier-metal-free structure.

• Access to Document (DOI)

Cu dual damascene interconnects with in-situ fluorinated carbon-nitride (FCN: -C=N(F)-) barrier layers in low-k organic film

Ohtake, H. and Saito, S. and Tada, M. and Harada, Y. and Onodera, T. and Hayashi, Y.

Technical Digest - International Electron Devices Meeting, 

2002年12月

　概要を見る

The highly reliable low-k/Cu dual damascene interconnects (DDI) with in-situ fluorinated carbon-nitride (FCN) barrier was successfully obtained in an organosiloxane film. Using CxFy/N2-base plasma, the DDI etching is achieved by sidewall- deposited flurorocarbon polymers. In addition, the etched-surface is covered with the FCN barrier, which suppresses the Cu diffusion.