研究発表 - 多田　宗弘

BEOL Interconnects for 2nm Technology Node and Beyond

Gaurav Thareja

[国際会議]  IEEE/JSAP 2025 Symposium on VLSI Technology and Circuits (VLSI) （Kyoto） , 

2025年06月

200nm-pitched,Superconducting Nb Interconnects for Cryo-CMOS Applications

N.Iguchi,H.Numata,M.Tanaka,K.Okamoto,T.Tanaka,K.Uchida,H.Ishikuro,T.Sakamoto,and M.Tada,

International Interconnect Technology Conference(IITC)2024,San Jose,United States, 

2024年06月

Gate-Length Dependent Variability of nMOSFET at Cryogenic Temperatures

Toshitsugu Sakamoto, Makoto Miyamura, Kazunori Funahashi, Munehiro Tada, Ken Uchida, Hiroki Ishikuro

International Conference on Solid State Device and Materials (SSDM) F-1-01, (Nagoya, Japan)., 

2023年09月

A 0.11pJ/bit Read Energy Embedded NanoBridge NVM and its Integration in a 28nm 32-bit RISC-V MCU

Xu Bai, Ryusuke Nebashi, Makoto Miyamura, Kazunori Funahashi, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Toshitsugu Sakamoto, Munehiro Tada

International Conference on Solid State Device and Materials (SSDM) K-2-01, (Nagoya, Japan)., 

2023年09月

NanoBridge use case for FPGA

Munehiro Tada　(Invited)

DARPA MEC Back-End of Line (BEOL) Integration of Active Devices Workshop, Institute for Defense Analyses (IDA) (Alexandria, USA)., 

2023年05月

Stochastic Modeling of Cryogenic and Room Temperature Operation of ReRAM

T. Tanaka, K. Okamoto, M. Tada, K. Uchida

35th International Microprocess and Nanotechnology Conference, (Tokushima, Japan)., 

2022年11月

NanoBridge Technology for Space Applications

Munehiro Tada

JAXA 35th Microelectronics Workshop (MEWS35) (Tsukuba, Japan)., 

2022年10月

Challenge and Opportunity of Low-power Nonvolatile FPGA using NanoBridge for Cryogenic Quantum Controller

Munehiro Tada　(Invited)

International Conference on Solid State Device and Materials (SSDM) G-4-02, (Chiba, Japan)., 

2022年09月

Cryogenic FPGA

Munehiro Tada　(Invited)

Next Generation Quantum Computing, Online + Onsite (Kanagawa, Japan)., 

2022年08月

In Situ Monitoring Technique of Self-Heating in Bulk MOSFETs at Cryogenic Temperatures using Subthreshold Current

Ichikawa, M. and Tanaka, T. and Uchida, K. and Miyao, T. and Tada, M. and Ishikuro, H.

2022 IEEE Latin America Electron Devices Conference, LAEDC 2022, 

2022年07月

　概要を見る

This work proposes an evaluation technique of self-heating (SH) in a 65-nm bulk CMOS transistor at cryogenic temperature (4.2K). For the in-situ monitoring of self-heating in cryo-CMOS circuits, transient response of the subthreshold drain current is used, which makes it possible to estimate the temperature at on-state of MOSFETs. The relation between the temperature increase by self-heating and power consumption of MOSFET has been experimentally obtained, which will help a design of high performance cryo-CMOS circuits for quantum computer application.

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Enhanced Drain Current in Transient Mode due to Long Ionization Time of Shallow Impurities at 4 K in 65-nm bulk Cryo CMOS Transistors

Tomohisa Miyao, Takahisa Tanaka, Itsuki Imanishi, Masayuki Ichikawa, Shuya Nakagawa, Hiroki Ishikuro, Toshitsugu Sakamoto, Munehiro Tada, and Ken Uchida

2022 Device Research Conference (DRC), (Columbus, USA), pp. 1-2., 

2022年06月

Cryogenic CMOS Performance Analysis Including BEOL Characteristics at 4K for Quantum Controller Application

K. Okamoto, T. Tanaka, M. Miyamura, H. Ishikuro, K. Uchida, T. Sakamoto, and M. Tada

2022 IEEE International Interconnect Technology Conference (IITC), (San Jose, USA), pp. 139-141., 

2022年06月

NanoBridge Technology for Embedded Novolatile Memory Application

Tada, M.

2022 IEEE International Memory Workshop, IMW 2022 - Proceedings, 

2022年05月

, 

IEEE

　概要を見る

NanoBridge (NB) is a kind of electrochemical resistive-change device using Cu ion migration from Cu interconnects into electrolyte. NBs are integrated by only two additional masks in a standard Cu-BEOL without scarifying CMOS performance. The newly developed split Cu electrode enables the lower set voltage (2.2V) and superior retention, which have been demonstrated in a 28 nm-node. High density embedded nonvolatile NB memory macro in a 65nm technology is successfully developed with P E=30 ns 30 ns programming based on the highly reliable and low-cost manufacturable NB technology. High yield is achieved with satisfying 30ns read, and more than 10 years retention at 150°C. NB properties can be systematically adjusted by tailoring the NB stack, achieving to broaden NB applications.

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NanoBridge Technology for Novoaltile FPGA and Memory Applications : (Invited)

Tada, M.

IEEE International Reliability Physics Symposium Proceedings, 

2022年03月

, 

IEEE International Reliability Physics Symposium Proceedings

　概要を見る

A recent progress of NanoBridge (NB) technology is reviewed in terms of nonvolatile field-programmable gate array (FPGA) and memory (NVM) applications. The NB is a kind type of electrochemical resistive-change device using migration of Cu, in which a thickness of Cu bridge can be controlled by a programming current and an appropriate ON-conductance is programmed for depending on the applications. For a routing switch in the FPGA, two NBs are connected in series and each conductance is tuned to 0.8mS to transfer signals, in which the NBFPGA realizes 78% area and 80% power reductions compared with a conventional SRAM-FPGA. For the NVM application, that is tuned to 0.2mS, which has 150oC 20years retention with 30% degradation of the conductance, which is potentially applicable for automobile/AIoT applications.

• Access to Document (DOI)

Low-power and Radiation-tolerant FPGA with NanoBridge Technology

Munehiro Tada　(Invited)

The 27th Session of the Asia-Pacific Regional Space Agency Forum (APRSAF-27) ., 

2021年12月

Cryogenic Operation of NanoBridge at 4K for Controlling Qubit

K. Okamoto, T. Tanaka, M. Miyamura, H. Ishikuro, K. Uchida, T. Sakamoto, M. Tada

2021 International Conference on Solid State Devices and Materials (SSDM), B-5-08, Online Conference., 

2021年09月

NanoBridge Applications Technology for Low-power Rad-hard AIoT Applications

Munehiro Tada　(Invited)

2021 IEEE　International Interconnect Technology Conference（IITC）, Workshop (Kyoto, Japan)., 

2021年07月

28nm Atom-Switch FPGA: Static Timing Analysis and Evaluation

Xu Bai, Ryusuke Nebashi, Makoto Miyamura, Naoki Banno, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Tadahiko Sugibayashi, Toshitsugu Sakamoto1 and Munehiro Tada

2021 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD 2021) A6-4　(on-line)., 

2020年08月

ON-state retention of Atom Switch eNVM for IoT/AI Inference Solution

Okamoto, K. and Nebashi, R. and Banno, N. and Bai, X. and Numata, H. and Iguchi, N. and Miyamura, M. and Hada, H. and Funahashi, K. and Sugibayashi, T. and Sakamoto, T. and Tada, M.

IEEE International Reliability Physics Symposium Proceedings, 

2020年04月

, 

IEEE

　概要を見る

An ON-state retention of a 40nm-node atom switch embedded nonvolatile memory (eNVM) has been carefully investigated for IoT/AI inference solution. Based on ON-conductance (Gon) tuning model of atom switch, one order of magnitude lower programming power is achieved while keeping the same Gon. Smaller ON-state retention dependences on temperature (Ea = 0.2eV) and time (n = 0.11) are experimentally clarified and the lifetime is predicted to be more than 10 years at 150°C under +20% shift criteria of Gon.

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Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications

M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, T. Sugibayashi

2020 IEEE International Solid- State Circuits Conference - (ISSCC), (San Francisco, USA), pp. 502-504., 

2020年02月

A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS

Nebashi, R. and Banno, N. and Miyamura, M. and Bai, X. and Funahashi, K. and Okamoto, K. and Iguchi, N. and Numata, H. and Sugibayashi, T. and Sakamoto, T. and Tada, M.

Proceedings - 30th International Conference on Field-Programmable Logic and Applications, FPL 2020, 

2020年

, 

Proceedings - 30th International Conference on Field-Programmable Logic and Applications, FPL 2020

　概要を見る

A nonvolatile FPGA using atom-switch crossbars is implemented in a 28nm CMOS. The depopulated atom-switch crossbar with double-gate layout achieves 75% area saving. The routability degradation due to the depopulation is mitigated by a modified routing architecture of mixed segment lengths with thinning out connection block populations. To our knowledge, the novel FPGA provides the largest logic capacity of 171k lookup-table (LUT) among 3D-FPGAs based on monolithically integrated nonvolatile switch and memory. The operating frequency and dynamic power are significantly improved as compared to conventional atom-switch FPGAs.

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1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy

Bai, X. and Banno, N. and Miyamura, M. and Nebashi, R. and Okamoto, K. and Numata, H. and Iguchi, N. and Hashimoto, M. and Sugibayashi, T. and Sakamoto, T. and Tada, M.

Digest of Technical Papers - Symposium on VLSI Technology, 

2020年

, 

Digest of Technical Papers - Symposium on VLSI Technology

　概要を見る

1.5x energy-efficient and 1.4x operation-speed, nonvolatile via-switch (VS) FPGA with atom switch and a-Si/SiN/a-Si varistor is demonstrated in a 65nm-node for various basic applications. For rapid and low-cost migration from VS-FPGA to ASIC, 'hard-via' to replace VS with 'ON', named VS-copy (VSC), is newly proposed. The VSC-ASIC is fabricated by sharing all the photo masks with VS-FPGA excepting one via mask revise and three VS masks skip, realizing an exact design copy with minimum NRE cost and TAT. The VS-FPGA equipped with the VSC gives energy-efficient edge device, e.g., for up-to-date AI inference algorithms, covering a wide range of chip volume with extremely low cost.

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Opportunities and Challenges of Atom Switch for Next AI Hardware

Munehiro Tada　Toshitsugu Sakamoto and Makoto Miyamura (Invited)

2019 International Conference on Solid State Device and Materials, (Nagoya, Japan) pp. 409-410., 

2019年09月

3x Improved Set-voltage Variability of Atom Switch with Split-electrode for Very Large Scale Integration

N. Banno, K. Okamoto, H. Numata, N. Iguchi, M. Miyamura, R. Nebashi, X. Bai, H. Hada, T. Sugibayashi, T. Sakamoto, and M. Tada

2019 International Conference on Solid State Device and Materials, (Nagoya, Japan), pp. 351-352., 

2019年09月

Characterization of chalcogenide selectors for crossbar switch used in nonvolatile FPGA

Numata, H. and Banno, N. and Okamoto, K. and Iguchi, N. and Hada, H. and Hashimoto, M. and Sugibayashi, T. and Sakamoto, T. and Tada, M.

2019 Silicon Nanoelectronics Workshop, SNW 2019, 

2019年

　概要を見る

Sputter deposited GexSe1-x films are characterized, prior to device fabrication for a selector. A Se-rich film has GeSe4/2 tetrahedral structure and higher crystallization temperature than Ge-rich films. Printed Ag-paste electrodes are used for I-V measurement and an amorphous Se-rich GexSe1-x film shows the good switching property for the selector with an on/off ratio of 4.8 × 104.

• Access to Document (DOI)

Single Event Effects Induced on Atom Switch based Field Programmable Gate Array

K. Takeuchi, T. Sakamoto, M. Tada, A. Takeyama, T. Oshima, S. Kuboyama and H. Shindo

Conference on Radiation and Its Effects on Components and Systems (RADECS) (Gothenburg, Sweden)., 

2018年09月

Atom-Switch-based FPGA with Optimized Driving Capability Buffer

X. Bai, M. Miyamura, Y. Tsuji, R. Nebashi, A. Morioka, N. Banno, K. Okamoto, H. Numata, H. Hada, T. Sugibayashi, T. Sakamoto and M. Tada

2018 International Conference on Solid State Devices and Materials, (Tokyo, Japan), pp. 121-122., 

2018年09月

Atom switch with improved cycle endurance using field enhancement for nonvolatile SoC

T. Sakamoto, Y. Tsuji, X. Bai, M. Miyamura, A. Morioka, R. Nebashi, N. Banno, K. Okamoto, N. Iguchi H. Hada, T. Sugibayashi and M. Tada

2018 IEEE International Memory Workshop (IMW), (Kyoto, Japan), pp. 1-4., 

2018年05月

High-density and fault-tolerant Cu atom switch technology toward 28nm-node nonvolatile programmable logic

Nebashi, R. and Banno, N. and Miyamura, M. and Tsuji, Y. and Morioka, A. and Bai, X. and Okamoto, K. and Iguchi, N. and Numata, H. and Hada, H. and Sugibayashi, T. and Sakamoto, T. and Tada, M.

Digest of Technical Papers - Symposium on VLSI Technology, 

2018年

　概要を見る

Key device/circuit technologies for realizing a 28nm-node atom switch programmable logic (AS-PL) have been developed. An advanced polymer solid-electrolyte (PSE) reduces set voltage down to 1.6 V while ensuring ON-state and OFF-state reliabilities under current and voltage stress at 125°C. A fine-grain redundancy in a cross-bar array also contributes to reduce supply voltage by 6%. A routing-based wear leveling improves programming cycles by nine times. The developed technologies allow us to design the 28nm-node AS-PL with a 32% higher performance and 11% lower power.

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Smart Interconnect Technology using Cu Atom Switch for Next Wave of Computing

Munehiro Tada　(Invited)

2017 International Interconnect Technology Conference (IITC), 12.1 (Hsinchu, Taiwan)., 

2017年05月

A low-power Cu atom switch programmable logic fabricated in a 40nm-node CMOS technology

Bai, X. and Sakamoto, T. and Tada, M. and Miyamura, M. and Tsuji, Y. and Morioka, A. and Nebashi, R. and Banno, N. and Okamoto, K. and Iguchi, N. and Hada, H. and Sugibayashi, T.

Digest of Technical Papers - Symposium on VLSI Technology, 

2017年

　概要を見る

For the first time, a 40nm-node, 2x logic density, 3.8x operation speed, and 3x power efficient, nonvolatile programmable logic (NPL) is demonstrated by using Cu atom switch for configuration switches. The switching characteristics of the atom switch are kept in scaling down to 64/32nm device area, and an improved PSE reduces set voltage while keeping low leakage current, enabling core transistors to select the atom switches. The developed 40nm NPL is a strong candidate for the next wave of energy-efficient computing.

• Access to Document (DOI)

50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic

N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi

2016 IEEE International Electron Devices Meeting (IEDM), (San Francisco, USA) pp. 424-427., 

2016年12月

Programmable SpaceWire interface with atom switch

H. Hihara, N. Tamagawa, T. Imamura, H. Sugaya, T. Sugibayashi, M. Miyamura, T. Sakamoto, M. Tada, H. Hada, K. Wakabayashi, A. Iwasaki

2016 International SpaceWire Conference (SpaceWire), Yokohama, Japan, pp. 1-4., 

2016年10月

A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch

Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama and Masanori Hashimoto

2016 26th International Conference on Field Programmable Logic and Applications (FPL), (Lausanne, Switzerland), pp. 1-4., 

2016年08月

A 2x Logic Density Programmable Logic Array using Atom Switch Fully Implemented with Logic Transistors at 40nm‐node and beyond

Y. Tsuji, X. Bai, A. Morioka, M. Miyamura, R. Nebashi, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, H. Hada and T. Sugibayashi

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), (Honolulu, USA), pp. 1-2., 

2016年06月

Highly-dense Mixed Grained Reconfigurable Architecture with Via-switch

Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama and Masanori Hashimoto

Design Automation Conference (DAC), (Austin, USA), WORK-IN-PROGRESS POSTER SESSION 100.12., 

2016年06月

Robust Cu Atom Switch with over-400°C thermally tolerant Polymer-solid Electrolyte (TT-PSE) for Nonvolatile Programmable Logic

K. Okamoto, M. Tada, N. Banno, N. Iguchi, H. Hada, T. Sakamoto, M. Miyamura, Y. Tsuji, R. Nebashi, A. Morioka, X. Bai, T. Sugibayashi

2016 Symposium on VLSI Technology (VLSI), (Hawaii, USA), p124-125., 

2016年06月

Highly-dense Mixed Grained Reconfigurable Architecture with Via-switch

Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama and Masanori Hashimoto

ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, (Santa Rosa, USA), pp.32-35., 

2016年03月

A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch

Hotate, J. and Kishimoto, T. and Higashi, T. and Ochi, H. and Doi, R. and Tada, M. and Sugibayashi, T. and Wakabayashi, K. and Onodera, H. and Mitsuyama, Y. and Hashimoto, M.

FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications, 

2016年

, 

IEEE

　概要を見る

This paper proposes a highly-dense reconfigurable architecture that introduces via-switch device, which is a kind of resistive RAM and is used in crossbar switches. Since via-switch is implemented in BEOL layers only, the FEOL layer under the crossbar can be fully exploited for highly-dense logic blocks. The proposed architecture uses the FEOL layer for fine-grained look-up tables and coarse-grained arithmetic/memory units for better performance and highly wide applications. In a case study of application mapping, the proposed architecture reduces array area by 76% thanks to mixed grained logic structure and overlay bidirectional interconnection. Thanks to 18F2 footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by 26× and the delay and energy in the interconnection are reduced by 90% and 93% at 0.5V operation.

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Novel processor architecture for onboard infrared sensors

Hihara, H. and Iwasaki, A. and Tamagawa, N. and Kuribayashi, M. and Hashimoto, M. and Mitsuyama, Y. and Ochi, H. and Onodera, H. and Kanbara, H. and Wakabayashi, K. and Tada, M.

Proceedings of SPIE - The International Society for Optical Engineering, 

2016年

, 

SPIE-INT SOC OPTICAL ENGINEERING

　概要を見る

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

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A Novel Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs

N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi

2015 IEEE International Electron Devices Meeting (IEDM), (Washington DC, USA), pp.32-35., 

2015年12月

Area-Efficient Non-volatile Carry Chain Based on Pass-Transistor/Atom-Switch Hybrid Logic

Xu Bai, Yukihide Tsuji, Ayuka Morioka, Makoto Miyamura, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada

2015 International Conference on Solid State Devices and Materials, (Sapporo, Japan), pp. 1176-1177., 

2015年09月

Sub-μW Standby Power, <18 μW/DMIPS@25MHz MCU with Embedded Atom-Switch Programmable Logic and ROM

Y. Tsuji, X. Bai, M. Miyamura, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, N. Sugii and H. Hada

2015 Symposium on VLSI Technology, (Kyoto, Japan), pp. T86-T87., 

2015年06月

0.39-V, 18.26-μW/MHz SOTB CMOS Microcontroller with Embedded Atom-Switch ROM

T. Sakamoto, Y. Tsuji, M. Tada, H. Makiyama, T. Hasegawa, Y. Yamamoto, S. Okanishi, K. Maekawa, N. Banno, M. Miyamura, K. Okamoto, N. Iguchi, Y. Ogasahara, H. Oda, S. Kamohara, Y. Yamagata, N. Sugii, and H. Hada

2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII), (Yokohama, Japan), pp. 1-3., 

2015年04月

Innovation of BEOL Devices for Energy Efficient Computing

M. Tada　(Invited)

MRS 2015 Spring Meeting, BB7.01 (2015 San Francisco, USA)., 

2015年04月

0.5-V Highly Power-efficient Programmable Logic using Nonvolatile Configuration Switch in BEOL 共著 2015年2月 FPGA conference 2015, pp. 236-239. M. Miyamura, T. Sakamoto, Y. Tsuji, M. Tada, N. Banno, K. Okamoto, N. Iguchi and H. Hada

M. Miyamura, T. Sakamoto, Y. Tsuji, M. Tada, N. Banno, K. Okamoto, N. Iguchi and H. Hada

FPGA conference 2015, pp. 236-239., 

2015年02月

Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics

X. Bai, Y. Tsuji, A. Morioka, M. Miyamura, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi and H. Hada

FPGA conference 2015, pp. 269., 

2015年02月

Logic Compatible Process technology for Embedded Atom Switches in CMOS

K. Okamoto, M. Tada, N. Banno, N. Iguchi, T. Sakamoto, and H. Hada

Advanced Metallization Conference　(ADMETA) plus, 6-2., 

2014年10月

Mechanism of OFF-State Lifetime Improvement in Complementary Atom Switch

N. Banno, M. Tada, T. Sakamoto, M. Miyamura, K. Okamoto, N. Iguchi, T. Nohisa, and H. Hada

2014 International Conference on Solid State Devices and Materials (SSDM), pp. 428-429, (Tsukuba, Japan), 

2014年09月

A Fast and Low-Voltage Cu Complementary-Atom-Switch 1Mb Array with High-Temperature Retention 共著 2014年6月 2014 Symposium on VLSI Technology (VLSI), (Hawaii, USA), p250-251. N. Banno, M. Tada, T. Sakamoto, M. Miyamura, K. Okamoto, N. Iguchi, T. Nohisa, and H. Hada

N. Banno, M. Tada, T. Sakamoto, M. Miyamura, K. Okamoto, N. Iguchi, T. Nohisa, and H. Hada

2014 Symposium on VLSI Technology (VLSI), (Hawaii, USA), p250-251., 

2014年06月

Atom Switch Technology for Low-Power Nonvolatile Logic Application

M. Tada, T. Sakamoto, M. Miyamura, N. Banno, K. Okamoto, and H. Hada　(Invited)

225th ECS spring meeting., 

2014年05月

BEOL Device Technologies for Energy Efficient Computing

M. Tada　(Invited)

2014 International Conference on Electronics Packaging (ICEP), (Toyama, Japan), FA2-2., 

2014年04月

Low-power Programmable-logic Cell Arrays using Nonvolatile Complementary Atom Switch

M. Miyamura, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, and H. Hada

15th International Symposium on Quality Electronic Design　(ISQED), (Santa Clara, USA), 3C-3, pp. 330-334., 

2014年03月

Utility of high on-off ratio, high off resistance rewritable device to EEPROM for ultra-low voltage operation of steep subthreshold slope FETs

Ogasahara, Y. and Ma, C. and Hioki, M. and Nakagawa, T. and Sekigawa, T. and Tsutsumi, T. and Koike, H. and Tada, M. and Sakamoto, T.

2014 IEEE 6th International Memory Workshop, IMW 2014, 

2014年

, 

IEEE

　概要を見る

This paper proposes the utility of the solid-electrode nanometer switch device called atom switch for ultra-low voltage EEPROM of near- or sub-60mV/dec. steep subthreshold slope transistors. We adopt combination of a simple inverter-sensing read circuit and the atom switch device. This circuit does not include sense amplifiers and not limited by operation limit of analog circuits. High on-off ratio and off resistance enable low-voltage operation with a simple inverter-sensing structure. We fabricated a TEG wafer in a 65nm process, and obtained measurement results of circuit operation in 350mV including the level shifter of memory cell selector driver and in 150mV with the read circuit only. © 2014 IEEE.

• Access to Document (DOI)

Opportunities and Challenges of Atom Switch for Low-power Programmable Logic 共著 2013年10月 224th ECS fall meeting. M. Tada, T. Sakamoto, and H. Hada　(Invited)

M. Tada, T. Sakamoto, and H. Hada　(Invited)

224th ECS fall meeting., 

2013年10月

Impact of overshoot current on SET operation of Atom Switch

T. Sakamoto, M. Tada, M. Miyamura, N. Banno, K. Okamoto, N. Iguchi, and H. Hada

2013 International Conference on Solid State Devices and Materials, (Fukuoka, Japan) pp.536-537., 

2013年09月

Bidirectional TaO-Diode-selected, Complementary Atom Switch (DCAS) for Area-efficient, Nonvolatile Crossbar Switch Block

K. Okamoto, M. Tada, N. Banno, T. Sakamoto, M. Miyamura, N. Iguchi, T. Nohisa, and H. Hada

2013 Symposium on VLSI Technology (VLSI), (Kyoto, Japan), T242-T243., 

2013年06月

Nonvolatile Programmable Logic Array Using Complementary Atom Switch

T. Sakamoto, M. Miyamura M. Tada, and H. Hada

MRS 2013 Spring Meeting, (San Francisco, USA), DD4.01., 

2013年04月

First Demonstration of Logic Mapping on Nonvolatile Programmable Cell Using Complementary Atom Switch

M. Miyamura, M. Tada, T. Sakamoto, N. Banno, K. Okamoto, N. Iguchi, and H. Hada

2012 International Electron Devices Meeting (IEDM), (San Francisco, USA), pp. 247-250., 

2012年12月

Compact Atom Switch integrated in 65nm-node BEOL

K. Okamoto, M. Tada, T. Sakamoto, N. Banno, N. Iguchi, T. Nohisa, and H. Hada

Material Research Society (MRS) 2012 Fall Meeting., 

2012年11月

Programmable Cell Array using Rewritable Atom Switch

M. Miyamura, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, and H. Hada

Pacific Rim Meeting on Electrochemical and Solid-State Science (PRiME) 2012 (Hawaii, USA)., 

2012年10月

Atom switch technology for low-power programmable logic

M. Tada　(Invited)

2nd International Resistive-RAM Workshop at Stanford. , 

2012年10月

Improved off-state reliability of nonvolatile resistive switch with low programming voltage

Tada, M. and Sakamoto, T. and Miyamura, M. and Banno, N. and Okamoto, K. and Iguchi, N. and Hada, H.

IEEE Transactions on Electron Devices, 

2012年09月

, 

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

　概要を見る

A complementary atom switch (CAS) is proposed to realize low programming voltage and high off-state reliability for crossbar switch application. Two atom switches with bipolar operation are connected in series with opposite direction, in which the two atom switches work as a single element. The two off-state atom switches in the CAS complementarily divide voltage stress, greatly enlarging the off-state lifetime. The CAS is embedded in Cu BEOL on a 65-nm-node CMOS platform without degrading the CMOS and interconnect performances. The CAS using two atom switches is one of the candidates for realizing energy-efficient nonvolatile programmable switches. © 2012 IEEE.

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Ultra-Low Power Devices by Taking Advantages of Atom Switches with Polymer Solid-electrolyte

H. Hada, T. Sakamoto, M. Tada, N. Banno, M. Miyamura, K. Okamoto, N. Iguchi and T. Nohisa　(Invited)

International Conference on Solid State Devices and Materials, (Kyoto, Japan), pp.608-609., 

2012年09月

Nonvolatile 32x32 Crossbar Atom Switch Block Integrated on a 65-nm CMOS Platform

N. Banno, M. Tada, T. Sakamoto, K. Okamoto, M. Miyamura, N. Iguchi, T. Nohisa, and H. Hada

2012 Symposium on VLSI Technology (VLSI), (Hawaii, USA), pp. 39-40., 

2012年06月

Complementary Atom Switch (CAS) with Low Programming Voltage Embedded in Cu BEOL for Nonvolatile Programmable Logic

M. Tada, T. Sakamoto, M. Miyamura, N. Banno, K. Okamoto, N. Iguchi, and H. Hada　

The Eighth International Nanotechnology Conference on Communication and Cooperation, (Tsukuba, Japan), T11. , 

2012年05月

Conducting Mechanism Analysis of Atom Switch Devices using Polymer Solid-electrolyte

K. Okamoto, M. Tada, T. Sakamoto, M. Miyamura, N. Banno, N. Iguchi, and H. Hada

The Eighth International Nanotechnology Conference on Communication and Cooperation, (Tsukuba, Japan)., 

2012年05月

Improved reliability and switching performance of atom switch by using ternary Cu-alloy and RuTa electrodes

Tada, M. and Sakamoto, T. and Banno, N. and Okamoto, K. and Miyamura, M. and Iguchi, N. and Hada, H.

Technical Digest - International Electron Devices Meeting, IEDM, 

2012年

　概要を見る

For the first time, Cu(AlTi)-alloy active-electrode coupled with RuTa inert-electrode is proposed to improve the reliability of nonvolatile Cu atom switch. The remarkably high rupture temperature (Tr >400 oC) of the nanometer-scale Cu bridge with the high thermal resistance (Rth) is realized by the Cu-alloy without increasing programming current. The anti-Cu diffusive, RuTa-alloy improves the retention of the ON-state at 150oC and endurance to >104 cycles. The metallurgical prescription is a key to improve the reliability and switching performance of the conducting bridge. © 2012 IEEE.

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Conducting Mechanism of Atom Switch with Polymer Solid-electrolyte

K. Okamoto, M. Tada, T. Sakamoto, M. Miyamura, N. Banno, N. Iguchi, and H. Hada

2011 International Electron Devices Meeting (IEDM), (Washington DC, USA), pp. 279-282., 

2011年12月

Highly Reliable, Complementary Atom Switch (CAS) with Low Programming Voltage Embedded in Cu BEOL for Nonvolatile Programmable Logic

M. Tada, T. Sakamoto, M. Miyamura, N. Banno, K. Okamoto, N. Iguchi, T. Nohisa, and H. Hada

2011 International Electron Devices Meeting (IEDM), (Washington DC, USA), pp. 689-692., 

2011年12月

NanoBridge Technology for Nonvolatile Programmable Logic

M. Tada　（Invited）

New Non-volatile Memory Workshop (Hsinchu, Taiwan). , 

2011年11月

Programmable Cell Array Using Rewritable Solid-Electrolyte Switch Integrated in 90nm CMOS

M. Miyamura, S. Nakaya, M. Tada, K. Okamoto, T. Sakamoto, N. Banno, S. Ishida, K. Ito, H. Hada, N. Sakimura, T. Sugibayashi, M. Motomura

2011 IEEE International Solid-State Circuits Conference (ISSCC), (San Francisco, USA), pp.228-229.2月, 

2011年02月

High OFF/ON-resistive NiO ReRAM using Post-Plasma-Oxidation (PPO) process

K. Okamoto, M. Tada, K. Ito, Y. Saito, S. Ishida and H. Hada

2010 International Conference on Solid State Devices and Materials, (Tokyo, Japan), pp.1110-1111., 

2010年09月

A new approach for improving operating margin of unipolar ReRAM using local minimum of reset voltage

Sakotsubo, Y. and Terai, M. and Kotsuji, S. and Saito, Y. and Tada, M. and Yabe, Y. and Hada, H.

Digest of Technical Papers - Symposium on VLSI Technology, 

2010年

　概要を見る

We propose a new approach for improving the operating margin of Ta 2O5/plasma oxidized TiO2 stacked unipolar ReRAM. It was found that the reset voltage (switching from low resistance state to high resistance state) can be minimized by using local minimum against the resistance of the low resistance state. In addition, weakening the plasma oxidation condition reduced the power consumption and the variation of reset voltage. Excellent operating margin and more than 105 switching cycle times was successfully demonstrated using the integrated device. © 2010 IEEE.

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Reliable solid-electrolyte crossbar switch for programmable logic device

Banno, N. and Sakamoto, T. and Tada, M. and Miyamura, M. and Yabe, Y. and Saito, Y. and Ishida, S. and Okamoto, K. and Hada, H. and Kasai, N. and Iguchi, N. and Aono, M.

Digest of Technical Papers - Symposium on VLSI Technology, 

2010年

　概要を見る

Solid-electrolyte crossbar switch (namely NanoBridge) with low programming current of 420μA and highly reliable ON state against pulsed-alternating current (AC) stress is demonstrated under practical operating conditions of a programmable logic device (PLD). The ON-state duration under a pulsed-AC stress is achieved >10 years at 150°C. The high reliability under AC originates from the fact that the stress induced by Cu+ ion migration at a negative bias is recovered by a positive bias. NanoBridge is applicable in a scaleddown, nonvolatile PLD for hp28 and beyond. © 2010 IEEE.

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Polymer Solid-Electrolyte (PSE) switch embedded in 90nm CMOS with forming-free and 10nsec programming for low power, Nonvolatile Programmable Logic (NPL)

Tada, M. and Sakamoto, T. and Okamoto, K. and Miyamura, M. and Banno, N. and Katoh, Y. and Ishida, S. and Iguchi, N. and Sakimura, N. and Hada, H.

Technical Digest - International Electron Devices Meeting, IEDM, 

2010年

　概要を見る

A novel polymer solid-electrolyte (PSE) switch, NanoBridge, featuring forming-free programming and an extremely high OFF/ON resistance ratio of 105 has been embedded in a 90nm-node CMOS by a fully logic-compatible process. Fast programming of 10nsec is also achieved in a 50nmφ 1k-bit-cell array by introducing the PSE, enabling a short and parallel programming. The OFF-state T50 lifetime at 125°C is extrapolated to be more than 10 years. The developed switch is a strong candidate for realizing a low-power and low-cost nonvolatile programmable logic (NPL). ©2010 IEEE.

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Fully Low Temperature (350oC) Processed Si PMOSFET with Poly-Ge Gate, Radical Oxidation of Gate-Oxide and Schottky Source/Drain for Monolithic 3D-ICs

M. Tada, J. H. Park, D. Kuzum, G. Thareja, Y. Nishi, and K. C. Saraswat

Material Research Society (MRS) 2009 Spring Meeting., 

2009年04月

Highly scalable nonvolatile TiOx/TaSiOy solid-electrolyte crossbar switch integrated in local interconnect for low power reconfigurable logic

Tada, M. and Sakamoto, T. and Tsuji, Y. and Banno, N. and Saito, Y. and Yabe, Y. and Ishida, S. and Terai, M. and Kotsuji, S. and Iguchi, N. and Aono, M. and Hada, H. and Kasai, N.

Technical Digest - International Electron Devices Meeting, IEDM, 

2009年

　概要を見る

A fully logic-compatible, nonvolatile crossbar switch using a novel dual-layer TiOx/TaSiOy solid-electrolyte, "NanoBridge", has been developed for the first time, which is scalable to 50 nm and beyond and keeps the extremely low ON-resistance of <100 Ω A key breakthrough is the dual-layer solid-electrolyte, in which TiOx works as an oxygen absorber as well as a superior ionic conductor, thus improving the yield, ON/OFF resistance ratio (>106) and cycling endurance (>103). The highly scalable 4 × 4 crossbar switch composed of NanoBridge integrated in a local Cu interconnect of a standard CMOS is successfully configured without select transistors. The nonvolatile solid-electrolyte, crossbar switch is a promising switch element for low power and low cost reconfigurable logic. © 2009 IEEE.

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Nonvolatile solid-electrolyte switch embedded into Cu interconnect

Sakamoto, T. and Tada, M. and Banno, N. and Tsuji, Y. and Saitoh, Y. and Yabe, Y. and Hada, H. and Iguchi, N. and Aono, M.

Digest of Technical Papers - Symposium on VLSI Technology, 

2009年

　概要を見る

A solid-electrolyte switch ("NanoBridge") has been successfully embedded into a 0.13-μm-node dual-damascene Cu interconnect using a highly reliable bilayer solidelectrolyte (TaSiO/Ta2O5) and a thin oxidation barrier, resulting in an excellent ON/OFF ratio (< 109) at a low ON resistance of 50Ω. The newly developed bilayer solid-electrolyte has improved the thermal stability during the BEOL process as well as improved electrical breakdown. The CMOS compatible NanoBridge is a promising switch to achieve high-performance and low-cost programmable LSIs.

Low Temperature (≦ 380ºC) and High Performance Ge CMOS Technology with Novel Source/Drain by Metal-Induced Dopants Activation and High-k/Metal Gate Stack for Monolithic 3D Integration

J. H. Park, M. Tada, D. Kuzum, P. Kapur, H. Y. Yu, H-.S. P. Wong, K. C. Saraswat

2008 IEEE International Electron Devices Meeting (IEDM), (San Francisco, USA), pp.943-946., 

2008年12月

Low Temperature Boron Activation in Amorphous Germanium for Three Dimensional Integrated Circuits (3D-ICs) using Ni-induced Crystallization

J. H. Park, M. Tada, H. Y. Yu, D. Kuzum, Y. Na and K. Saraswat

Pacific Rim Meeting on Electrochemical and Solid-State Science (PRiME) 2008. (Hawaii, USA)., 

2008年10月

2008 International Conference on Solid State Devices and Materials, (Tsukuba, Japan), pp. 720-721.

M. Tada, N. Inoue, J. Kawahara, H. Yamamoto, F. Ito, T. Fukai, M. Ueki, S. Miyake, T. Takeuchi, S. Saito, M. Tagami, N. Furutake, K. Hijioka, T. Ito, Y. Shibue, T. Senou, R. Ikeda, N. Okada, and Y. Hayashi

2008 International Conference on Solid State Devices and Materials, (Tsukuba, Japan), pp. 720-721., 

2008年09月

Low Temperature Processes using Ni-induced Crystallization Technique for Monolithic Three Dimensional Integration

J. H. Park, M. Tada, H. Peng, and K. C. Saraswat

2008 International Conference on Solid State Devices and Materials, (Tsukuba, Japan), pp. 58-59., 

2008年09月

Low Temperature Single Crystal Germanium Growth on Amorphous Substrate Using Nano-patterning Technique and Metal(Au)-induced Lateral Crystallization (M(Au)ILC)

J. H. Park, P. Kapur, H. Peng, M. Tada, H. Y. Yu, and K. C. Saraswat,

Material Research Society (MRS) Spring meeting., 

2008年03月

Cost-effective and High　Performance Cu Interconnects (keff=2.75) with Continuous SiOCH Stack Incorporating a Low-k Barrier Cap (k=3.1)

M. Ueki, H. Yamamoto, F. Ito, J. Kawahara, M. Tada, T. Takeuchi, S. Saito, N. Fururake, T. Onodera, and Y. Hayashi

2007 IEEE International Electron Devices Meeting (IEDM), (Washington DC, USA), pp. 973-976., 

2007年12月

45nm-node interconnects with porous SiOCH-stacks, tolerant of low-cost packaging applications

Inoue, N. and Tagami, M. and Itoh, F. and Yamamoto, H. and Takeuchi, T. and Saito, S. and Furutake, N. and Ueki, M. and Tada, M. and Suzuki, T. and Hayashi, Y.

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers, 

2007年06月

, 

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

　概要を見る

The 45nm-node interconnect with porous SiOCH-stacks of keff=2.9 is confirmed to have the practical reliability in PGBA and QFP. Adhesion strength of the via-ILD to the lower SiCN capping layer significantly impacts on the wire-bond reliability, but spreading the contact area of the bonding-wire within the fine-pitched bonding-pad suppresses the bonding failures in the low-k stack structures, irrespective of additional process of low-k curing or not. No failure was detected during reliability tests in PBGA package as well as QFP, confirming the practicality of the low keff interconnects for 45nm-node ULSIs. © 2007 IEEE.

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Highly-oriented PVD ruthenium liner for low-resistance direct-plated Cu interconnects

Abe, M. and Ueki, M. and Tada, M. and Onodera, T. and Furutake, N. and Shimura, K. and Saito, S. and Hayashi, Y.

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers, 

2007年06月

　概要を見る

Low-resistance Cu damascene interconnects have been developed with highly oriented PVD-Ru/TaN liner using a direct-plated Cu process. Texture of the direct-plated Cu on the Ru/TaN is strongly correlated with Ru(002) orientation, enriching Cu(111) texture comparable with a conventional plated-Cu film on seed-Cu/Ta/TaN. The resistivity of 0.2μm-wide direct-plated Cu lines with the highly (002)-oriented Ru/TaN liner at 20K is 12.4% lower than that of conventional Cu lines with Ta/TaN liner, meaning that the reduction of the resistivity in Cu lines with Ru liner at RT was achieved by smaller interface scattering besides the lower bulk resistivity of Ru than Ta. The orientation control of Ru liner is a key factor for the low-resistance Cu interconnects needed for scaled-down ULSI interconnects. © 2007 IEEE.

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Plasma co-polymerization technology with molecular-level structure tightening in "in-situ" SiOCH stacks for 32nm-node Cu interconnects

Tada, M. and Yamamoto, H. and Ito, F. and Narihiro, M. and Ueki, M. and Inoue, N. and Abe, M. and Saito, S. and Takeuchi, T. and Furutake, N. and Onodera, T. and Kawahara, J. and Arai, K. and Kasama, Y. and Taiji, T. and Tohara, M. and Sekine, M. and Hayashi, Y.

Technical Digest - International Electron Devices Meeting, IEDM, 

2006年12月

　概要を見る

A novel plasma co-polymerization technology, using flexibly-mixed molecular gas of chain-type vinyl-siloxane and 6-membered ring-type one, has been developed for new Seamless Low-k SiOCH Stacks (SEALS). An ultimate high-modulus silica-amorphous-carbon-composite (SACC)-SiOCH film with 24.8GPa was realized by 100%-injection of the chain-type siloxane, adapting to the hard-mask on molecular-pore-stack (MPS) SiOCH film (k=2.45, 3.0GPa) from 100%-injection of the ring-type siloxane. For the via-dielectrics was utilized a new co-polymerized (CP) SiOCH film (k=2.8, 12.6GPa) from these gas mixture to enhance the mechanical strength. The in-situ sequential deposition of three kinds of films without air-break accomplished excellent adhesion, high quality interface and low O2 ashing damage. The fully-scaled-down, 32nm-node Cu interconnects achieved 83fF/mm (single-load) in 100nm-pitched Cu lines with the new co-polymerized SEALS.

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Nano-Structural Control of Molecular-Pore Stacked (MPS) SiOCH Films Using Plasma Copolymerization Reaction

H. Yamamoto, F. Ito, M. Tada, T. Takeuchi, N. Furutake, and Y. Hayashi

Material Research Society (MRS) 2006 Fall Meeting., 

2006年11月

A Metallurgical Prescription for Electromigration (EM) Reliability Improvement in Scaled-down, Cu Dual Damascene Interconnects

M. Tada, M. Abe, H. Ohtake, N. Furutake, T. Tonegawa, K. Motoyama, M. Tohara, F. Ito, M. Ueki, T. Takeuchi, S. Saito, K. Fujii, M. Sekine, and Y. Hayashi

2006 International Interconnect Technology Conference, (Burlingame, USA), pp. 89-91., 

2006年06月

High-performance Cu-interconnects with Novel Seamless Low-k SiOCH Stacks (SEALS) Featured by Compositional Modulation Process for 45nm-Node ULSI Devices

M. Tagami, H. Ohtake, M. Tada, M. Ueki, F. Ito, T. Taiji, Y. Kasama, T. Iwamoto, H. Wakabayashi, T. Fukai, K. Arai, S. Saito, H. Yamamoto, M. Abe, M. Narihiro, N. Furutake, T. Onodera, T. Takeuchi, Y. Tsuchiya, N. Oda, M. Sekine, M. Hane, and Y. Hayashi

2006 Symposium on VLSI Technology (VLSI), (Hawaii, USA), pp. 108-109., 

2006年06月

A robust 45 nm-node, dual damascene interconnects with high quality Cu/barrier interface by a novel oxygen absorption process

Abe, M. and Tada, M. and Ohtake, H. and Furutake, N. and Narihiro, M. and Arai, K. and Takeuchi, T. and Saito, S. and Taiji, T. and Motoyama, K. and Kasama, Y. and Arita, K. and Ito, F. and Yamamoto, H. and Tagami, M. and Tonegawa, T. and Tsuchiya, Y. and Fujii, K. and Oda, N. and Sekine, M. and Hayashi, Y.

Technical Digest - International Electron Devices Meeting, IEDM, 

2005年12月

　概要を見る

By a novel oxygen absorption process, low oxygen-content Cu-alloy is implemented for fully-scaled-down, 45 nm-node dual damascene interconnects (DDIs) with 140 nm-pitched lines and 70 nmø-vias. In this process, a very thin metal film as an oxygen absorber, which has larger negative change in the standard Gibbs free energy of oxidation than a barrier metal, is put on a natural oxide at a surface of electro-plated, Cu film. The oxygen atoms diffuse to the oxygen absorber, not to the barrier metal under the Cu film, achieving high quality Cu/barrier interface after annealing. Combining the oxygen absorption process with Cu-alloy process, 45 nm-node DDI in molecular-pore-stacking (MPS) SiOCH film is successfully obtained with high endurances for SIV, EM and TDDB. © 2005 IEEE.

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Via-Profile Controlled, Porous Low-k/Cu DDIs with High Thermal Stability

H. Ohtake, S. Saito, M. Tagami, M. Tada, M. Abe, N. Furutake, and Y. Hayashi

2005 International Conference on Solid State Devices and Materials, (Hyogo, Japan), pp. 300-301., 

2005年09月

Feasibility Study of a Novel Molecular-Pore-Stacking (MPS), SiOCH Film in Fully-scale-down, 45nm-node Cu Damascene Interconnects

M. Tada, H. Ohtake, M. Narihiro, F. Ito, T. Taiji, M. Tohara, K. Motoyama, Y. Kasama, M. Tagami, M. Abe, T. Takeuchi, K. Arai, S. Saito, N. Furutake, T. Onodera, J. Kawahara, K. Kinoshita, N. Hata, T. Kikkawa, Y. Tsuchiya, K. Fujii, N. Oda, M. Sekine, and Y. Hayashi

2005 Symposium on VLSI Technology (VLSI), (Kyoto, Japan), pp. 18-19., 

2005年06月

Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs

Ueki, M. and Narihiro, M. and Ohtake, H. and Tagami, M. and Tada, M. and Ito, F. and Harada, Y. and Abe, M. and Inoue, N. and Arai, K. and Takeuchi, T. and Saito, S. and Onodera, T. and Furutake, N. and Hiroi, M. and Sekine, M. and Hayashi, Y.

Digest of Technical Papers - Symposium on VLSI Technology, 

2004年06月

　概要を見る

Fully-scaled-down, 65nm-node Cu dual damascene interconnects (DDIs) with 180nm/200nm-pitched lines and 100nmφ-vias have been developed in full porous-SiOCH films (k=2.5). Two new techniques are introduced such as (1) a low thermal-budget process for securing the DDI via-yield without the Cu agglomeration, and (2) a "DD pore seal" covering all the side walls of the line-trenches and the vias for improving the dielectric reliability. The full porous-SiOCH DDI with the thin Ta/TaN barrier improves the overall RC product by 24% against the porous-on-rigid, hybrid single damascene interconnects (SDIs). The cost-effective, DDIs with keff ∼3.0 is applicable especially for the 65nm-node, low-power ASICs.

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Novel molecular-structure design for PECVD porous SiOCH films toward 45nm-node, ASICs with k=2.3

Hayashi, Y. and Itoh, F. and Harada, Y. and Takeuchi, T. and Tada, M. and Tagami, M. and Ohtake, H. and Hijioka, K. and Saito, S. and Onodera, T. and Hara, D. and Tokudome, K.

Proceedings of the IEEE 2004 International Interconnect Technology Conference, 

2004年

　概要を見る

A porous SiOCH film with k=2.3 is developed by a new concept PECVD, in which pore-involved molecules are piled up together to deposit a "molecular-pore stacked, SiOCH (MPS)" film. The pore size and the density of the film are controlled by designing the pore size and the steric-hindrance side-chains of the source molecules. A newly synthesized, 6-member ring-type, organo-siloxane with the side-chains of large steric-hindrance hydrocarbons realizes the MPS film with k=2.3. The basic feasibility of the MPS film is confirmed through the integration into Cu damascene interconnects. The MPS film is a strong candidate for the low-k, inter-metal-dielectrics in 45nm-node, ASICs.

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A 65nm-node, Cu Interconnect Technology Using Porous Sioch Film (k=2.5) Covered with Ultra-Thin, Low-k Pore Seal (k=2.7)

Tada, M. and Harada, Y. and Tamura, T. and Inoue, N. and Ito, F. and Yoshiki, M. and Ohtake, H. and Narihiro, M. and Tagami, M. and Ueki, M. and Hijioka, K. and Abe, M. and Takeuchi, T. and Saito, S. and Onodera, T. and Furutake, N. and Arai, K. and Fujii, K. and Hayashi, Y.

Technical Digest - International Electron Devices Meeting, 

2003年12月

　概要を見る

A highly reliable, 65nm-node Cu interconnect technology has been developed with 180nm/200nm-pitched lines connected through φ100nm-vias. A porous SiOCH film (k=2.5) with sub-nanometer pores is introduced for the inter-metal dielectrics (IMD) on a non-porous, rigid SiOCH film (k=2.9) for the via-intra-line dielectrics (via-ILD). A key breakthrough is a special pore-seal technique, in which the trench-etched surface of the porous SiOCH is covered with an ultra-thin, low-k organic silica film (k=2.7), thus improving the line-to-line TDDB reliability of the narrow-pitched Cu lines. The fully-scaled-down, 65nm-node Cu interconnects with the porous-on-rigid SiOCH hybrid structure achieve excellent performance and reliability.

Highly thermal-stable, plasma-polymerized BCB polymer film

Kawahara, J. and Nakano, A. and Kinoshita, K. and Harada, Y. and Tagami, M. and Tada, M. and Hayashi, Y.

Plasma Sources Science and Technology, 

2003年11月

　概要を見る

A new plasma-enhanced organic monomer-vapour polymerization (plasma polymerization) method has been developed. It was used to make a divinyl siloxane bis-benzocyclobutene (DVS-BCB) polymer film for Cu dual-damascene interconnects that had high thermal stability and a low dielectric constant, k = 2.6. The method consists of the vaporization of organic monomers, transportation of monomers in the gas phase, and polymerization by plasma to make the polymer film. The method eliminates polymer oxidation of DVS-BCB during the polymerization in high vacuum, which improves the film's thermal stability. The thermal stability of plasma-polymerized BCB (p-BCB) exceeded 400°C because of the higher deposition temperature, and the film had a high resistance to Cu diffusion at 400°C annealing. The narrow-pitched Cu/BCB damascene lines showed a 35% reduction in line capacitance compared with Cu/SiO 2 ones. The p-BCB is shown to be a strong candidate for Cu/low-k interconnects.

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Improvement of TDDB reliability in Cu damascene interconnect by using united hard-mask and Cap (UHC) structure

Tada, M. and Harada, Y. and Ohtake, H. and Saito, S. and Onodera, T. and Hayashi, Y.

Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003, 

2003年

　概要を見る

Reliably of Cu damascene interconnects (DDIs) using United Hard-mask and Cap (UHC) structure, which involves the same material for both Hard-mask and Cap layers is investigated. Line-to-line insulating reliabilities such as a leakage current, TZDB and TDDB are greatly improved by using the UHC structure even without any barrier metal layers, indicating that the interline leakage path is not in a bulk of the low-k dielectric but the interface between the Cap and the CMP-damaged Hard-mask. This new Cu dual damascene interconnect with UHC provides the interconnect reliability of future ULSIs with ultra-thin barrier metals toward a barrier-metal-free structure.

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Cu dual damascene interconnects with in-situ fluorinated carbon-nitride (FCN: -C=N(F)-) barrier layers in low-k organic film

Ohtake, H. and Saito, S. and Tada, M. and Harada, Y. and Onodera, T. and Hayashi, Y.

Technical Digest - International Electron Devices Meeting, 

2002年12月

　概要を見る

The highly reliable low-k/Cu dual damascene interconnects (DDI) with in-situ fluorinated carbon-nitride (FCN) barrier was successfully obtained in an organosiloxane film. Using CxFy/N2-base plasma, the DDI etching is achieved by sidewall- deposited flurorocarbon polymers. In addition, the etched-surface is covered with the FCN barrier, which suppresses the Cu diffusion.

Low-cost Cu Interconnects Using Direct Patterning Process (DPP) of Photo-sensitive MSZ with Low-k, Bottom Anti-reflective layer

M. Tada, T. Ogura, and Y. Hayashi

International Conference on Solid State Devices and Materials, (Nagoya, Japan), pp. 44-45., 

2002年09月

Chemical Structural Control of Plasma-Polymerized Divinylsiloxane Benzocyclobutene Films for Sub 100nm-node ULSI devices

Y. Harada, M. Tada, J. Kawahara, and Y. Hayashi

International Conference on Solid State Devices and Materials, (Nagoya, Japan), pp. 180-181., 

2002年09月

Cu dual damascene interconnects in porous organosilica film with organic hard-mask and etch-stop layers for 70 nm-node ULSIs

Tada, M. and Harada, Y. and Hijioka, K. and Ohtake, H. and Takeuchi, T. and Saito, S. and Onodera, T. and Hiroi, M. and Furutake, N. and Hayashi, Y.

Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002, 

2002年06月

　概要を見る

Hybrid-type, Cu dual damascene interconnects (DDI) are fabricated in a porous organosilica film (k = 2.1) inserted between low-k films of hard-mask (HM) and etch-stop (ES) layers. Plasma-polymerized, divinyl siloxane bis-benzocyclobutene (p-BCB, k = 2.7) film, instead of SiCN film (k > 4), is selected for these HM and ES layers due to the low k-value as well as the high etch-stop property to the porous film. The line capacitance in the hybrid-type, Cu-DDI with BCB-HM and BCB-ES layers decreases 20% compared with that of the Cu-DDI with SiO2-HM and SiCN-ES layers, achieving the effective dielectric constant (keff) of 2.6. This new interconnect structure is a strong candidate for the 70 nm-node ULSIs.

• Access to Document (DOI)

Dual Hard Mask Process for Low-k Porous Organosilica Dielectric in Copper Dual Damascene Interconnect Fabrication

M. Hiroi, M. Tada, H. Ohtake, S. Saito, T. Onodera, N. Furutake, Y. Harada, Y. Hayashi

IEEE 2001 International. Interconnect Technology Conference, (San Francisco, USA), pp. 295-297., 

2001年06月

Barrier-metal-free (BMF), Cu dual-damascene interconnects with Cu-epi-contacts buried in anti-diffusive, low-k organic film

Tada, M. and Ohtake, H. and Harada, Y. and Hiroi, M. and Saito, S. and Onodera, T. and Furutake, N. and Kawahara, J. and Tagami, M. and Kinoshita, K. and Fukai, T. and Mogami, T. and Hayashi, Y.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 

2001年06月

　概要を見る

Barrier-metal-free (BMF), Cu dual-damascene interconnects (DDI) are fabricated in the plasma-polymerized, divinyl siloxane bis-benzocyclobutene (p-BCB: k=2.6) polymer film, which is featured by the anti-diffusive characteristics for the Cu. The BMF-structure has inter-line leak current as low as that of a conventional barrier-inserted structure and is estimated to keep the high insulating property over 10 years under 1MV/cm. The BMF-structure also derives Cu-epi-contacts, reducing the via-resistance of 50% to the conventional Cu/barrier/Cu contacts. The effective dielectric constant was keff=3.1 including very thin SiN etch-stop-layers, accomplishing 20%-fast CMOS device operation to that of the conventional Cu-DDI in the SiO2 with Ta/TaN barriers. The BMF, Cu-DDIs buried directly in the p-BCB film is one of the ultimate structures for high performance, 0.1μm-CMOS devices and beyond.

• Access to Document (DOI)

Process Design Methodology for Via-Shape-Controlled, Copper Dual Damascene Interconnects in Low-k Organic Film

K. Kinoshita, M. Tada, T. Usami, M. Hiroi, T. Tonegawa, K. Shiba, T. Onodera, M. Tagami, S. Saitoh, and Y. Hayashi

IEEE International Electron Devices Meeting (IEDM) 2000, (San Francisco, USA), pp. 257-260., 

2000年12月

Cu Single Damascene Interconnects with Plasma-polymerized Organic Polymers (k=2.6) for High-speed, 0.1 μm CMOS devices

M. Tagami, T. Fukai, M. Hiroi, J. Kawahara, K. Shiba, M. Tada, T. Onodera, S. Saito, K. Kinoshita, T. Ogura, M. Narihiro, K. Arai, K. Yamaguchi, M. Fukaishi, K. Kikuta, T. Mogami, and Y. Hayashi

IEEE International Electron Devices Meeting (IEDM) 2000, (San Francisco, USA), pp. 2851-853., 

2000年12月

Characterization of plasma-polymerized divinyl-siloxane benzocyclobutene (DVS-BCB) polymer film

M. Tada, J. Kawahara, and Y. Hayashi

Advanced Metallization Conference, (Sam Diego, USA), pp. 579-585., 

2000年10月

Highly thermal-stable, plasma-polymerized BCB polymer film (k = 2.6) for Cu dual-damascene interconnects

i

Digest of Technical Papers - Symposium on VLSI Technology, 

2000年06月

　概要を見る

Highly thermal-stable, plasma-polymerized divinyl siloxane bis-benzocyclobutene (p-BCB) polymer film is developed for Cu dual-damascene interconnects. The thermal stability of p-BCB is improved over 400 °C by higher deposition temperature, having high resistance to Cu diffusion at 400 °C-annealing. Lowering the RF plasma-power and the deposition pressure, the p-BCB film has smaller dielectric constant than the conventional spin-coating BCB (k = 2.7). The p-BCB (k = 2.6)/Cu interconnects reveal 46% delay reduction of CMOS ring oscillator to the conventional SiO2/Al ones. The p-BCB is proved as a strong candidate for Cu/low-k interconnects.

• Access to Document (DOI)

MICROSTRUCTURE OF ALKALINE EARTH AND RARE EARTH FLUORIDE THIN FILMS PREPARED BY CHEMICAL PROCESS

Munehiro Tada, Shinobu Fujihara, Toshio Kimura

MRS Fall Meeting & Exhibit (Boston, USA) A6.81., 

1998年12月