研究発表 - 多田　宗弘

A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS

Nebashi, R. and Banno, N. and Miyamura, M. and Bai, X. and Funahashi, K. and Okamoto, K. and Iguchi, N. and Numata, H. and Sugibayashi, T. and Sakamoto, T. and Tada, M.

Proceedings - 30th International Conference on Field-Programmable Logic and Applications, FPL 2020, 

2020年

, 

Proceedings - 30th International Conference on Field-Programmable Logic and Applications, FPL 2020

　概要を見る

A nonvolatile FPGA using atom-switch crossbars is implemented in a 28nm CMOS. The depopulated atom-switch crossbar with double-gate layout achieves 75% area saving. The routability degradation due to the depopulation is mitigated by a modified routing architecture of mixed segment lengths with thinning out connection block populations. To our knowledge, the novel FPGA provides the largest logic capacity of 171k lookup-table (LUT) among 3D-FPGAs based on monolithically integrated nonvolatile switch and memory. The operating frequency and dynamic power are significantly improved as compared to conventional atom-switch FPGAs.

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1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy

Bai, X. and Banno, N. and Miyamura, M. and Nebashi, R. and Okamoto, K. and Numata, H. and Iguchi, N. and Hashimoto, M. and Sugibayashi, T. and Sakamoto, T. and Tada, M.

Digest of Technical Papers - Symposium on VLSI Technology, 

2020年

, 

Digest of Technical Papers - Symposium on VLSI Technology

　概要を見る

1.5x energy-efficient and 1.4x operation-speed, nonvolatile via-switch (VS) FPGA with atom switch and a-Si/SiN/a-Si varistor is demonstrated in a 65nm-node for various basic applications. For rapid and low-cost migration from VS-FPGA to ASIC, 'hard-via' to replace VS with 'ON', named VS-copy (VSC), is newly proposed. The VSC-ASIC is fabricated by sharing all the photo masks with VS-FPGA excepting one via mask revise and three VS masks skip, realizing an exact design copy with minimum NRE cost and TAT. The VS-FPGA equipped with the VSC gives energy-efficient edge device, e.g., for up-to-date AI inference algorithms, covering a wide range of chip volume with extremely low cost.

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Opportunities and Challenges of Atom Switch for Next AI Hardware

Munehiro Tada　Toshitsugu Sakamoto and Makoto Miyamura (Invited)

2019 International Conference on Solid State Device and Materials, (Nagoya, Japan) pp. 409-410., 

2019年09月

3x Improved Set-voltage Variability of Atom Switch with Split-electrode for Very Large Scale Integration

N. Banno, K. Okamoto, H. Numata, N. Iguchi, M. Miyamura, R. Nebashi, X. Bai, H. Hada, T. Sugibayashi, T. Sakamoto, and M. Tada

2019 International Conference on Solid State Device and Materials, (Nagoya, Japan), pp. 351-352., 

2019年09月

Characterization of chalcogenide selectors for crossbar switch used in nonvolatile FPGA

Numata, H. and Banno, N. and Okamoto, K. and Iguchi, N. and Hada, H. and Hashimoto, M. and Sugibayashi, T. and Sakamoto, T. and Tada, M.

2019 Silicon Nanoelectronics Workshop, SNW 2019, 

2019年

　概要を見る

Sputter deposited GexSe1-x films are characterized, prior to device fabrication for a selector. A Se-rich film has GeSe4/2 tetrahedral structure and higher crystallization temperature than Ge-rich films. Printed Ag-paste electrodes are used for I-V measurement and an amorphous Se-rich GexSe1-x film shows the good switching property for the selector with an on/off ratio of 4.8 × 104.

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Single Event Effects Induced on Atom Switch based Field Programmable Gate Array

K. Takeuchi, T. Sakamoto, M. Tada, A. Takeyama, T. Oshima, S. Kuboyama and H. Shindo

Conference on Radiation and Its Effects on Components and Systems (RADECS) (Gothenburg, Sweden)., 

2018年09月

Atom-Switch-based FPGA with Optimized Driving Capability Buffer

X. Bai, M. Miyamura, Y. Tsuji, R. Nebashi, A. Morioka, N. Banno, K. Okamoto, H. Numata, H. Hada, T. Sugibayashi, T. Sakamoto and M. Tada

2018 International Conference on Solid State Devices and Materials, (Tokyo, Japan), pp. 121-122., 

2018年09月

Atom switch with improved cycle endurance using field enhancement for nonvolatile SoC

T. Sakamoto, Y. Tsuji, X. Bai, M. Miyamura, A. Morioka, R. Nebashi, N. Banno, K. Okamoto, N. Iguchi H. Hada, T. Sugibayashi and M. Tada

2018 IEEE International Memory Workshop (IMW), (Kyoto, Japan), pp. 1-4., 

2018年05月

High-density and fault-tolerant Cu atom switch technology toward 28nm-node nonvolatile programmable logic

Nebashi, R. and Banno, N. and Miyamura, M. and Tsuji, Y. and Morioka, A. and Bai, X. and Okamoto, K. and Iguchi, N. and Numata, H. and Hada, H. and Sugibayashi, T. and Sakamoto, T. and Tada, M.

Digest of Technical Papers - Symposium on VLSI Technology, 

2018年

　概要を見る

Key device/circuit technologies for realizing a 28nm-node atom switch programmable logic (AS-PL) have been developed. An advanced polymer solid-electrolyte (PSE) reduces set voltage down to 1.6 V while ensuring ON-state and OFF-state reliabilities under current and voltage stress at 125°C. A fine-grain redundancy in a cross-bar array also contributes to reduce supply voltage by 6%. A routing-based wear leveling improves programming cycles by nine times. The developed technologies allow us to design the 28nm-node AS-PL with a 32% higher performance and 11% lower power.

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Smart Interconnect Technology using Cu Atom Switch for Next Wave of Computing

Munehiro Tada　(Invited)

2017 International Interconnect Technology Conference (IITC), 12.1 (Hsinchu, Taiwan)., 

2017年05月

A low-power Cu atom switch programmable logic fabricated in a 40nm-node CMOS technology

Bai, X. and Sakamoto, T. and Tada, M. and Miyamura, M. and Tsuji, Y. and Morioka, A. and Nebashi, R. and Banno, N. and Okamoto, K. and Iguchi, N. and Hada, H. and Sugibayashi, T.

Digest of Technical Papers - Symposium on VLSI Technology, 

2017年

　概要を見る

For the first time, a 40nm-node, 2x logic density, 3.8x operation speed, and 3x power efficient, nonvolatile programmable logic (NPL) is demonstrated by using Cu atom switch for configuration switches. The switching characteristics of the atom switch are kept in scaling down to 64/32nm device area, and an improved PSE reduces set voltage while keeping low leakage current, enabling core transistors to select the atom switches. The developed 40nm NPL is a strong candidate for the next wave of energy-efficient computing.

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50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic

N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi

2016 IEEE International Electron Devices Meeting (IEDM), (San Francisco, USA) pp. 424-427., 

2016年12月

Programmable SpaceWire interface with atom switch

H. Hihara, N. Tamagawa, T. Imamura, H. Sugaya, T. Sugibayashi, M. Miyamura, T. Sakamoto, M. Tada, H. Hada, K. Wakabayashi, A. Iwasaki

2016 International SpaceWire Conference (SpaceWire), Yokohama, Japan, pp. 1-4., 

2016年10月

A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch

Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama and Masanori Hashimoto

2016 26th International Conference on Field Programmable Logic and Applications (FPL), (Lausanne, Switzerland), pp. 1-4., 

2016年08月

A 2x Logic Density Programmable Logic Array using Atom Switch Fully Implemented with Logic Transistors at 40nm‐node and beyond

Y. Tsuji, X. Bai, A. Morioka, M. Miyamura, R. Nebashi, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, H. Hada and T. Sugibayashi

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), (Honolulu, USA), pp. 1-2., 

2016年06月

Highly-dense Mixed Grained Reconfigurable Architecture with Via-switch

Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama and Masanori Hashimoto

Design Automation Conference (DAC), (Austin, USA), WORK-IN-PROGRESS POSTER SESSION 100.12., 

2016年06月

Robust Cu Atom Switch with over-400°C thermally tolerant Polymer-solid Electrolyte (TT-PSE) for Nonvolatile Programmable Logic

K. Okamoto, M. Tada, N. Banno, N. Iguchi, H. Hada, T. Sakamoto, M. Miyamura, Y. Tsuji, R. Nebashi, A. Morioka, X. Bai, T. Sugibayashi

2016 Symposium on VLSI Technology (VLSI), (Hawaii, USA), p124-125., 

2016年06月

Highly-dense Mixed Grained Reconfigurable Architecture with Via-switch

Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama and Masanori Hashimoto

ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, (Santa Rosa, USA), pp.32-35., 

2016年03月

A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch

Hotate, J. and Kishimoto, T. and Higashi, T. and Ochi, H. and Doi, R. and Tada, M. and Sugibayashi, T. and Wakabayashi, K. and Onodera, H. and Mitsuyama, Y. and Hashimoto, M.

FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications, 

2016年

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IEEE

　概要を見る

This paper proposes a highly-dense reconfigurable architecture that introduces via-switch device, which is a kind of resistive RAM and is used in crossbar switches. Since via-switch is implemented in BEOL layers only, the FEOL layer under the crossbar can be fully exploited for highly-dense logic blocks. The proposed architecture uses the FEOL layer for fine-grained look-up tables and coarse-grained arithmetic/memory units for better performance and highly wide applications. In a case study of application mapping, the proposed architecture reduces array area by 76% thanks to mixed grained logic structure and overlay bidirectional interconnection. Thanks to 18F2 footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by 26× and the delay and energy in the interconnection are reduced by 90% and 93% at 0.5V operation.

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Novel processor architecture for onboard infrared sensors

Hihara, H. and Iwasaki, A. and Tamagawa, N. and Kuribayashi, M. and Hashimoto, M. and Mitsuyama, Y. and Ochi, H. and Onodera, H. and Kanbara, H. and Wakabayashi, K. and Tada, M.

Proceedings of SPIE - The International Society for Optical Engineering, 

2016年

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SPIE-INT SOC OPTICAL ENGINEERING

　概要を見る

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

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