Details of a Researcher - Yamasaki Nobuyuki

Papers - Yamasaki Nobuyuki

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Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology

Cortes C., Amano H., Yamasaki N.

2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings (2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings) 2017-November 1 - 6 2018.03

Research paper (international conference proceedings), Accepted

It is essential for any embedded systems and increasing popularity of Internet of Things (IoT) be energy efficient. Such systems tend to work intermittently and reducing leakage in the idle time is essential. Energy reduction techniques bring the system to a low power mode which also provokes transition overheads. If such overheads are not considered, the task may not be schedulable under a given deadline. To get a gain in energy savings, the idle state must be longer than a minimum required time. This time is referred as Break Even Time (BET). To properly design efficient algorithms and schedulers we must calculate and include the BET. In this paper, we present the first studies to examine the BET using accurate parameters extracted from a real chip using Silicon On Thin Box (SOTB) technology employing Body Bias Control (BB) energy saving technique. In this study, we demonstrate the BET range for SOTB microcontrollers, on the order of 0.5ms up to 1ms.

Access to Document (DOI)

A Low Latency Real-time Execution with Interrupt Wake-up Mechanism on RMT Processor

KOHEI OSAWA, KEIGO MIZOTANI, HIROYUKI CHISHIRO, YAMASAKI NOBUYUKI

情報処理学会論文誌 58 ( 2 ) 531 - 543 2017.02

Performance Evaluation of RUNT Algorithm

Hiroyuki Chishiro, Masayoshi Takasu, Rikuhei Ueda, YAMASAKI NOBUYUKI

ACM SIGBED Review 13 ( 1 ) 15 - 21 2016.01

Research paper (scientific journal)

An Integration of Imprecise Computation Model and Real-Time Voltage and Frequency Scaling on Responsive Multithreaded Processor

Keigo Mizotani, Yusuke Hatori, Yusuke Kumura, Masayoshi Takasu, Hiroyuki Chishiro, Yamasaki Nobuyuki

International Journal of Computers and Their Applications 22 ( 3 ) 127 - 135 2015.09

Research paper (scientific journal)

Zero-Jitter Semi-Fixed-Priority Scheduling with Harmonic Periodic Task Sets

Hiroyuki Chishiro, Yamasaki Nobuyuki

International Journal of Computers and Their Applications 22 ( 3 ) 118 - 126 2015.09

Research paper (scientific journal)

インプリサイス計算モデルにおける温度を考慮した動的電圧周波数制御の実機評価

溝谷圭悟, 上田陸平, 高須雅義, 千代浩之, 松谷宏紀, 山崎信行

情報処理学会論文誌 55 ( 8 ) 1841 - 1855 2014.08

Research paper (scientific journal), Accepted

Implementation of ITRON Specification OS for RMT Processor

上田陸平, 藤井啓, 千代浩之, 松谷宏紀, 山崎信行

情報処理学会論文誌 54 ( 7 ) 1835 - 1848 2013.07

Accepted

Recent advances in embedded systems demands high-performance under real-time constraints. Responsive Multithreaded Processor (RMT Processor) employs prioritized Simultaneous Multithreading (SMT) architecture with hardware-assisted context switch for such high-end embedded systems. In this paper, real-time OS based on ITRON specification is extended to support multithread processing on RMT Processor. Thread-control instructions, which are specific to RMT Processor, are used for thread creation and dispatch to reduce the context switching overhead. A dedicated thread is assigned to interrupt pro- cessing in order to maintain the worst-case interrupt response time when the number of threads executing simultaneously increases. Experimental results show that service calls that include context switch operations are accelerated by the hardware-assisted context switch, task schedulability is also improved accordingly, and the dedicated thread for interrupt processing can maintain the interrupt response time.

Router Microarchitectures for Reducing Priority Inversions in Priority-aware On-chip-networks

谷口将一, 山崎大輝, 笹川雄二郎, 松谷宏紀, 山崎信行

情報処理学会論文誌 54 ( 7 ) 1861 - 1872 2013.07

優先度付きオンチップルータVIX

KAZUTOSHI SUITO, TAKUMA KOGO, DAIKI YAMAZAKI, HIROKI MATSUTANI, YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム 6 ( 1 ) 87-98 2013.01