Details of a Researcher - Yamasaki Nobuyuki

Papers - Yamasaki Nobuyuki

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Design and evaluation of a lightweight codec for error-free POF

Kohei Wada, Nobuyuki Yamasaki

SPIE Photonics West Vol. 13916-15 1-7 2026.01

Research paper (international conference proceedings), Accepted

Responsive link for real-time communications

Nobuyuki Yamasaki

SPIE Photonics West Vol. 13916-17 1-7 2026.01

Research paper (international conference proceedings), Accepted

Exploring Shared Reservation Stations for Embedded Processors

Kazuki Kogure, Nobuyuki Yamasaki

2025 Thirteenth International Symposium on Computing and Networking Workshops (CANDARW) 377 - 379 2025.11

Research paper (international conference proceedings), Accepted

iRMTvisor: A Real-Time Hypervisor with IPC Control Scheme

Haruka Sanuki, Nobuyuki Yamasaki

2025 Thirteenth International Symposium on Computing and Networking (CANDAR) 66 - 74 2025.11

Research paper (international conference proceedings), Accepted

Pseudo-SMT Processor with Context Cache

Moyu Yanagi, Nobuyuki Yamasaki

2025 Thirteenth International Symposium on Computing and Networking Workshops (CANDARW) 360 - 364 2025.11

Research paper (international conference proceedings), Accepted

Migration Using Context Cache for Multicore RISC-V Processor

Akira Yamazawa, Tsutomu Itou, Kazutoshi Suito and Nobuyuki Yamasaki

Concurrency and Computation: Practice and Experience vol.37 2025.10

Research paper (scientific journal), Joint Work, Accepted

With the advancement of computer technology, modern systems increasingly run multiple programs. A context switch occurs when the operating system switches the executing program from one thread to another. During this process, the system saves the current thread's context to memory and restores the context of the following thread from memory. However, the context switch has significant overhead, which can degrade overall system performance if it occurs frequently. In this study, we design the context cache for a multicore RISC-V processor to reduce the migration overhead caused by context switches between multiple cores. By utilizing a context cache, we aim to accelerate context switches and improve system performance and efficiency. We evaluated the context cache, which reduced the overhead of thread migration. Furthermore, we assessed the trade-off between performance and area by changing its configuration.

Design of Light Codec for Error-free POF

Kohei Wada, K. Muramoto, Y. Koike and Nobuyuki Yamasaki

The 33rd International Conference on Plastic Optical Fibers 2025.10

Research paper (international conference proceedings), Joint Work

A Design of Fault-Tolerant System for Safety-Critical Systems

Kai Yoshizawa, Nobuyuki Yamasaki

2025 11th International Conference on Automation, Robotics, and Applications (ICARA) 280 - 284 2025.02

Research paper (international conference proceedings), Joint Work, Accepted

In safety-critical systems where failures or faults can lead to accidents, especially in special and harsh environments like those encountered in spacecraft, it is well known that multiple levels of errors can significantly increase the likelihood of system failure. For instance, system-level errors may occur due to cable breaks caused by severe vibrations, while gate-level errors can arise from radiation effects on System-on-Chip (SoC) semiconductors. Furthermore, in such specialized environments, human repair is often not feasible, necessitating that the system continue to operate even when a fault occurs in a part of it. Therefore, this research discusses the design, implementation, and evaluation of a redundant system that combines multi-level redundancy mechanisms to tolerate multiple errors and maintain operation. The implementation was carried out on the Space I/O Core (SIOC), a System-on-Chip equipped with processors and I/O for distributed real-time systems. Additionally, bitstreams were created from the implemented logic, and the performance of the fault-tolerant system was evaluated using an actual FPGA.

A Learning-based Control Scheme for Prioritized SMT Processor

Kaname Sato, Nobuyuki Yamasaki

Proceedings - 2024 Twelfth International Symposium on Computing and Networking Workshops (CANDARW) (Proceedings - 2024 Twelfth International Symposium on Computing and Networking Workshops (CANDARW)) 76 - 82 2024.11

Research paper (international conference proceedings), Accepted

Context Cache for Multicore RISC-V Processor

Akira Yamazawa, Tsutomu Itou, Kazutoshi Suito and Nobuyuki Yamasaki

Proceedings - 2024 Twelfth International Symposium on Computing and Networking (CANDAR) (Proceedings - 2024 Twelfth International Symposium on Computing and Networking (CANDAR)) 272 - 278 2024.11

Research paper (international conference proceedings), Accepted

Communication Error Measurement System to Design High-Efficient Codec for Error-Free POF

Kohei Wada, K. Muramoto, Y. Koike and Nobuyuki Yamasaki

The 32nd International Conference on Plastic Optical Fibers 2024.11

Research paper (international conference proceedings), Joint Work

Towards Applying POF to Distributed Control Systems

Nobuyuki Yamasaki

The 33rd International Conference on Plastic Optical Fibers 2024.11

Research paper (international conference proceedings), Single Work

A Design Scheme for Highly Efficient Mixed-Criticality Systems Using IPC Control

Kosuke Yashima, Nobuyuki Yamasaki

14th International Workshop on Networking, Computing, Systems, and Software 2024.02

Research paper (international conference proceedings)

A Scheme Reducing Task Drops for Data Dependent Tasks on Mixed Criticality Systems

Reo Nagura, Nobuyuki Yamasaki

14th International Workshop on Networking, Computing, Systems, and Software 2024.02

Research paper (international conference proceedings)

A Non-stop Fault-Tolerant Real-Time System-on-Chip/System-in-Package

Shota Nakabeppu, Nobuyuki Yamasaki

2023 Eleventh International Symposium on Computing and Networking (CANDAR) 2024.02

Research paper (international conference proceedings), Accepted

Today, embedded real-time systems such as automobiles, spacecraft, and sensor networks are parts of social infrastructures. Since a system failure in these systems may lead to a severe accident, these systems should be designed as fault-tolerant systems. If a power failure occurs in an embedded real-time system, values of all flip-flops and main memory are lost, resulting in a system failure.This paper describes the design, implementation, and evaluation of a system-on-chip/system-in-package for a non-stop fault-tolerant real-time system that continues to operate even with an unstable power supply. We designed and implemented a non-stop fault-tolerant real-time system-on-chip (SoC) that integrates a non-stop microprocessor, a non-volatile memory (MRAM), a volatile memory (SRAM), and IO peripherals. We also co-designed and implemented a non-stop fault-tolerant real-time system-in-package (SiP) that integrates the SoC, an FPGA, memories, a USB power delivery (USB PD), DC/DC converters, a potentiometer, and a board-to-board (BtoB) connector at the same time to support functions not included in the SoC but required. We evaluated the bit error rate of store operations and benchmark performance with checkpoint creations on the actual SiP.

A Design of Multithreaded RISC-V Processor for Real-Time System

Yuta Nojiri, Nobuyuki Yamasaki

2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW) 2024.02

Research paper (international conference proceedings), Accepted

The rising prominence of RISC-V, despite its inherent lack of multithreading support, has sparked research initiatives to design and implement multithreaded RISC-V processors. In this paper, we present a novel multithreaded RISC-V processor explicitly tailored for real-time systems. Our design allows for dynamic thread manipulation- encompassing creation, execution, halting, deletion, and more- to emulate the behavior of tasks in a real-time operating system’s task queue. We introduce specialized instructions to RISC-V to facilitate these thread control operations. The proposed processor is equipped with eight logical cores, enabling simultaneous execution of up to eight threads. A context cache is integrated to efficiently manage context switches between threads, achieving context switches in four clocks. This feature empowers the processor to concurrently run a greater number of threads than its core count. Simulation results underscore the benefits of our design: multithreaded execution yields an instruction per cycle (IPC) rate that surpasses single-threaded execution by up to 5.5 times. Furthermore, our priority system ensures preferential execution of high-priority threads over their lower-priority counterparts. Consequently, we have realized a multithreaded RISC-V processor capable of prioritized execution across eight threads and concurrent execution beyond its core count.

Design of Decoded Instruction Cache

Takero Magara, Nobuyuki Yamasaki

2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW) 2024.02

Research paper (international conference proceedings), Accepted

Recent microprocessors improve performance by extracting various levels of parallelism. Among these, out-of-order processors focus on ILP to improve performance. On the other hand, out-of-order processors consume a lot of power because they fetch and decode many instructions.We propose a Decoded Instruction Cache (DIC), in which the control signals generated by decoding RISC instructions are stored as decoded instructions in the DIC. The scheme improves performance and reduces power consumption because the results of fetch and decode can be reused. The DIC also supports multi-threaded execution, so TLP is also improved.When implemented in a multithreaded RISC processor, the DIC improves IPC by 2.39%.

Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems

Shota Nakabeppu, Nobuyuki Yamasaki

IEICE Transactions on Electronics (Institute of Electronics, Information and Communication, Engineers, IEICE) E106.C ( 7 ) 365 - 381 2023.07

Research paper (scientific journal), Joint Work, Accepted

It is very important to design an embedded real-time system as a fault-tolerant system to ensure dependability. In particular, when a power failure occurs, restart processing after power restoration is required in a real-time system using a conventional processor. Even if power is restored quickly, the restart process takes a long time and causes deadline misses. In order to design a fault-tolerant real-time system, it is necessary to have a processor that can resume operation in a short time immediately after power is restored, even if a power failure occurs at any time. Since current embedded real-time systems are required to execute many tasks, high schedulability for high throughput is also important. This paper proposes a non-stop microprocessor architecture to achieve a fault-tolerant real-time system. The non-stop microprocessor is designed so as to resume normal operation even if a power failure occurs at any time, to achieve little performance degradation for high schedulability even if checkpoint creations and restorations are performed many times, to control flexibly non-volatile devices through software configuration, and to ensure data consistency no matter when a checkpoint restoration is performed. The evaluation shows that the non-stop microprocessor can restore a checkpoint within 5µsec and almost hide the overhead of checkpoint creations. The non-stop microprocessor with such capabilities will be an essential component of a fault-tolerant real-time system with high schedulability.

Access to Document (DOI)

Data Rearrange Unit for Efficient Data Computation

Akiyuki Mamiya, Nobuyuki Yamasaki

International Journal of Networking and Computing 12 ( 2 ) 295 - 316 2022.07

Research paper (scientific journal), Joint Work, Accepted

Recently, the demand for computation-intensive applications such as multimedia and AI applications has increased. Data-parallel execution units are typically used for calculations in these applications to increase computational throughput. However, the data required for computation may need to be accessed at discontinuous memory addresses, which can reduce computation efficiency. Generally, normal memory access instructions access data blocks of continuously allocated memory addresses, containing both valid and invalid data for computation. These memory access patterns result in low computation density in the data parallel execution units, wasting computation resources. Therefore, simply increasing the number of data-parallel execution units leads to an increase in wasted computational resources, which will become a significant issue in embedded systems where multiple resource limitations exist. It is essential to improve computational efficiency to perform practical computation in such systems. This paper introduces a Data Rearrange Unit (DRU), which gathers and rearranges valid computation data between main memory and execution units. The DRU improves the performance of multimedia and AI application by significantly reducing the access rate from/to main memory and increasing computation efficiency. It is applicable to most hardware architectures, and its effectiveness can be further enhanced by the execution unit interface that directly connects the DRU to the execution unit. We demonstrate the effectiveness of our DRU by implementation on the RMTP SoC, improving convolution throughput on a data-parallel execution unit by a maximum of 94 times while only increasing the total cell area by about 12.7%.

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Prioritized Asynchronous Calls for Parallel Processing on Responsive MultiThreaded Processor

Lopez Tomas A., Yamasaki Nobuyuki

Proceedings - 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022 (Proceedings - 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022) 46 - 55 2022

Research paper (international conference proceedings), Accepted

With the advent of parallel processors for embedded systems, it is very important to design new runtime and system features so that embedded software developers can take advantage of the increased throughput and responsiveness without the hindrances of low-level synchronization and data sharing. In this paper, we design and implement a fully-prioritized, work-conserving, and event-driven parallel computing runtime on Responsive MultiThreaded Processor (RMTP), a simultaneous multi-threading (SMT) processing platform with priority for real-time systems, which implements hardware-based resource allocation and context switching. The proposed runtime achieves low-cost forks and fine-grained prioritized scheduling by using special-purpose hardware functionalities on the RMTP, and also reduces resource over-subscription penalties while allowing for dynamic parallelism by employing a continuation-stealing execution strategy. We evaluate the performance of the proposed system with a set of benchmarks derived from the MiBench suite, and show that meaningful speedup can be achieved even when the degree of parallelism at each level is dynamically varied.

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