Details of a Researcher - Yamasaki Nobuyuki

Papers - Yamasaki Nobuyuki

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A Learning-based Control Scheme for Prioritized SMT Processor

Kaname Sato, Nobuyuki Yamasaki

Proceedings - 2024 Twelfth International Symposium on Computing and Networking Workshops (CANDARW) (Proceedings - 2024 Twelfth International Symposium on Computing and Networking Workshops (CANDARW)) 76 - 82 2024.11

Research paper (international conference proceedings), Accepted

Context Cache for Multicore RISC-V Processor

Akira Yamazawa, Tsutomu Itou, Kazutoshi Suito and Nobuyuki Yamasaki

Proceedings - 2024 Twelfth International Symposium on Computing and Networking (CANDAR) (Proceedings - 2024 Twelfth International Symposium on Computing and Networking (CANDAR)) 272 - 278 2024.11

Research paper (international conference proceedings), Accepted

A Design Scheme for Highly Efficient Mixed-Criticality Systems Using IPC Control

Kosuke Yashima, Nobuyuki Yamasaki

14th International Workshop on Networking, Computing, Systems, and Software 2024.02

Research paper (international conference proceedings)

A Scheme Reducing Task Drops for Data Dependent Tasks on Mixed Criticality Systems

Reo Nagura, Nobuyuki Yamasaki

14th International Workshop on Networking, Computing, Systems, and Software 2024.02

Research paper (international conference proceedings)

A Non-stop Fault-Tolerant Real-Time System-on-Chip/System-in-Package

Shota Nakabeppu, Nobuyuki Yamasaki

2023 Eleventh International Symposium on Computing and Networking (CANDAR) 2024.02

Research paper (international conference proceedings), Accepted

Today, embedded real-time systems such as automobiles, spacecraft, and sensor networks are parts of social infrastructures. Since a system failure in these systems may lead to a severe accident, these systems should be designed as fault-tolerant systems. If a power failure occurs in an embedded real-time system, values of all flip-flops and main memory are lost, resulting in a system failure.This paper describes the design, implementation, and evaluation of a system-on-chip/system-in-package for a non-stop fault-tolerant real-time system that continues to operate even with an unstable power supply. We designed and implemented a non-stop fault-tolerant real-time system-on-chip (SoC) that integrates a non-stop microprocessor, a non-volatile memory (MRAM), a volatile memory (SRAM), and IO peripherals. We also co-designed and implemented a non-stop fault-tolerant real-time system-in-package (SiP) that integrates the SoC, an FPGA, memories, a USB power delivery (USB PD), DC/DC converters, a potentiometer, and a board-to-board (BtoB) connector at the same time to support functions not included in the SoC but required. We evaluated the bit error rate of store operations and benchmark performance with checkpoint creations on the actual SiP.

A Design of Multithreaded RISC-V Processor for Real-Time System

Yuta Nojiri, Nobuyuki Yamasaki

2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW) 2024.02

Research paper (international conference proceedings), Accepted

The rising prominence of RISC-V, despite its inherent lack of multithreading support, has sparked research initiatives to design and implement multithreaded RISC-V processors. In this paper, we present a novel multithreaded RISC-V processor explicitly tailored for real-time systems. Our design allows for dynamic thread manipulation- encompassing creation, execution, halting, deletion, and more- to emulate the behavior of tasks in a real-time operating system’s task queue. We introduce specialized instructions to RISC-V to facilitate these thread control operations. The proposed processor is equipped with eight logical cores, enabling simultaneous execution of up to eight threads. A context cache is integrated to efficiently manage context switches between threads, achieving context switches in four clocks. This feature empowers the processor to concurrently run a greater number of threads than its core count. Simulation results underscore the benefits of our design: multithreaded execution yields an instruction per cycle (IPC) rate that surpasses single-threaded execution by up to 5.5 times. Furthermore, our priority system ensures preferential execution of high-priority threads over their lower-priority counterparts. Consequently, we have realized a multithreaded RISC-V processor capable of prioritized execution across eight threads and concurrent execution beyond its core count.

Design of Decoded Instruction Cache

Takero Magara, Nobuyuki Yamasaki

2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW) 2024.02

Research paper (international conference proceedings), Accepted

Recent microprocessors improve performance by extracting various levels of parallelism. Among these, out-of-order processors focus on ILP to improve performance. On the other hand, out-of-order processors consume a lot of power because they fetch and decode many instructions.We propose a Decoded Instruction Cache (DIC), in which the control signals generated by decoding RISC instructions are stored as decoded instructions in the DIC. The scheme improves performance and reduces power consumption because the results of fetch and decode can be reused. The DIC also supports multi-threaded execution, so TLP is also improved.When implemented in a multithreaded RISC processor, the DIC improves IPC by 2.39%.

Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems

Shota Nakabeppu, Nobuyuki Yamasaki

IEICE Transactions on Electronics (Institute of Electronics, Information and Communication, Engineers, IEICE) E106.C ( 7 ) 365 - 381 2023.07

Research paper (scientific journal), Joint Work, Accepted

It is very important to design an embedded real-time system as a fault-tolerant system to ensure dependability. In particular, when a power failure occurs, restart processing after power restoration is required in a real-time system using a conventional processor. Even if power is restored quickly, the restart process takes a long time and causes deadline misses. In order to design a fault-tolerant real-time system, it is necessary to have a processor that can resume operation in a short time immediately after power is restored, even if a power failure occurs at any time. Since current embedded real-time systems are required to execute many tasks, high schedulability for high throughput is also important. This paper proposes a non-stop microprocessor architecture to achieve a fault-tolerant real-time system. The non-stop microprocessor is designed so as to resume normal operation even if a power failure occurs at any time, to achieve little performance degradation for high schedulability even if checkpoint creations and restorations are performed many times, to control flexibly non-volatile devices through software configuration, and to ensure data consistency no matter when a checkpoint restoration is performed. The evaluation shows that the non-stop microprocessor can restore a checkpoint within 5µsec and almost hide the overhead of checkpoint creations. The non-stop microprocessor with such capabilities will be an essential component of a fault-tolerant real-time system with high schedulability.

Access to Document (DOI)

Data Rearrange Unit for Efficient Data Computation

Akiyuki Mamiya, Nobuyuki Yamasaki

International Journal of Networking and Computing 12 ( 2 ) 295 - 316 2022.07

Research paper (scientific journal), Joint Work, Accepted

Recently, the demand for computation-intensive applications such as multimedia and AI applications has increased. Data-parallel execution units are typically used for calculations in these applications to increase computational throughput. However, the data required for computation may need to be accessed at discontinuous memory addresses, which can reduce computation efficiency. Generally, normal memory access instructions access data blocks of continuously allocated memory addresses, containing both valid and invalid data for computation. These memory access patterns result in low computation density in the data parallel execution units, wasting computation resources. Therefore, simply increasing the number of data-parallel execution units leads to an increase in wasted computational resources, which will become a significant issue in embedded systems where multiple resource limitations exist. It is essential to improve computational efficiency to perform practical computation in such systems. This paper introduces a Data Rearrange Unit (DRU), which gathers and rearranges valid computation data between main memory and execution units. The DRU improves the performance of multimedia and AI application by significantly reducing the access rate from/to main memory and increasing computation efficiency. It is applicable to most hardware architectures, and its effectiveness can be further enhanced by the execution unit interface that directly connects the DRU to the execution unit. We demonstrate the effectiveness of our DRU by implementation on the RMTP SoC, improving convolution throughput on a data-parallel execution unit by a maximum of 94 times while only increasing the total cell area by about 12.7%.

Access to Document (DOI)

Prioritized Asynchronous Calls for Parallel Processing on Responsive MultiThreaded Processor

Lopez Tomas A., Yamasaki Nobuyuki

Proceedings - 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022 (Proceedings - 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022) 46 - 55 2022

Research paper (international conference proceedings), Accepted

With the advent of parallel processors for embedded systems, it is very important to design new runtime and system features so that embedded software developers can take advantage of the increased throughput and responsiveness without the hindrances of low-level synchronization and data sharing. In this paper, we design and implement a fully-prioritized, work-conserving, and event-driven parallel computing runtime on Responsive MultiThreaded Processor (RMTP), a simultaneous multi-threading (SMT) processing platform with priority for real-time systems, which implements hardware-based resource allocation and context switching. The proposed runtime achieves low-cost forks and fine-grained prioritized scheduling by using special-purpose hardware functionalities on the RMTP, and also reduces resource over-subscription penalties while allowing for dynamic parallelism by employing a continuation-stealing execution strategy. We evaluate the performance of the proposed system with a set of benchmarks derived from the MiBench suite, and show that meaningful speedup can be achieved even when the degree of parallelism at each level is dynamically varied.

Access to Document (DOI)

Real-Time Execution based on Fluid Scheduling by using IPC Control Scheme

Santo A., Yamasaki N.

Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 (Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021) 459 - 463 2021

Research paper (international conference proceedings), Accepted

Fluid scheduling is an optimal real-time scheduling applicable to multiprocessor systems and is a scheduling model so that every real-time task is executed at a constant speed from release time to deadline. It is necessary for fluid scheduling to control the execution speed of each task. But, since the execution speed of the task is invariable in a conventional general purpose processor. Therefore, fluid scheduling is conventionally achieved by repeatedly executing and stopping tasks. However, this method incurs significant overheads due to frequent task switching. On the other hand, fluid scheduling without overhead by using an IPC control scheme has been proposed. The IPC control scheme controls the execution speed of each thread in an SMT processor. We propose a new IPC control scheme to extract thread-level parallelism and improve throughput effectively, also improving the schedulability of the fluid schedule. The evaluation results show that the proposed method improved the total throughput of the fluid schedule.

Access to Document (DOI)

Data Rearrange Unit for Efficient Data Computation in Embedded Systems

Mamiya A., Yamasaki N.

Research paper (international conference proceedings), Accepted

Recently demands for computation intensive applications such as convolutional neural networks (CNNs) have been increasing. In these applications, valid data for computation are allocated in non-continuous addresses. Therefore, common burst memory access pattern results in a low spatial locality of valid data per access. As a result, computation of data parallel execution units degrades in throughput, as computation resource is wasted by computing invalid data. This is especially a problem in embedded systems in which constraints in power consumption provoke a requirement for high computation efficiency. In this paper, we introduce a Data Rearrange Unit (DRU), a hardware unit rearranging computation data to increase spatial locality of valid data. The DRU drastically reduces the main memory access rate and increases computation efficiency by decreasing memory access to reduce power consumption. We demonstrate the effectiveness of our DRU by implementation on the RMTP SoC [1] [2] improving convolution throughput on a data parallel execution unit by a maximum of 94times, while only increasing the total cell area by about 13%.

Access to Document (DOI)

A Learning-based Fetch Thread Gating Mechanism for A Simultaneous Multithreading Processor

Ide Y., Yamasaki N.

Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020 (Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020) 19 - 28 2020.11

Research paper (international conference proceedings), Accepted

Simultaneous Multithreading (SMT) technology is widely adopted in modern high-end processors to maximize on-chip hardware utilization. In an SMT processor, multiple threads are executed in parallel, sharing hardware resources. This technique aggregates potential efficiency which will not be available in a single thread processor. However, when a data cache miss or a branch prediction miss occurs, every thread competing for hardware resources causes the degradation of hardware utilization. Therefore, instruction fetch policies have been proposed to manage hardware resources efficiently in SMT processors. The fetch policies distribute hardware resources indirectly, through fetch bandwidth control. Conventionally, a fetch policy selects fetch threads based only on the resource usage at the moment, while the characteristics of threads are not exploited on decision. Therefore most conventional fetch control schemes only take effects only after an outstanding event occurs. Capability of resource restriction is limited even with an aggressive fetch control scheme. In this paper, we propose a Fetch Gate Estimator (FGE) that is a fetch gating mechanism based on machine learning, which is implemented as a hardware module. The FGE evaluates each thread to decide whether an instruction fetch from a thread should be gated. The FGE is trained dynamically by the execution statistics resulted from the inferences, so that characteristics of each thread are encoded into a learning model. Thus, the FGE is trained dynamically in parallel with execution of programs. We applied a single layer perceptron as learning model inside the FGE for circuit simplicity, and investigated performance impacts. Evaluation results show that the perceptron-based FGE can train itself from acquired execution statistics to identify inefficient threads adaptively, adjusting resources through the fetch gate control mechanism.

Access to Document (DOI)

Codeword set selection for the error-correcting 4b/10b line code with maximum clique enumeration

Takeda M., Yamasaki N.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences) E103A ( 10 ) 1227 - 1233 2020.10

Research paper (scientific journal), Accepted, ISSN 09168508

This paper addresses the problem of finding, evaluating, and selecting the best set of codewords for the 4b/10b line code, a dependable line code with forward error correction (FEC) designed for real-time communication. Based on the results of our scheme [1], we formulate codeword search as an instance of the maximum clique problem, and enumerate all candidate codeword sets via maximum clique enumeration as proposed by Eblen et al. [2]. We then measure each set in terms of resistance to bit errors caused by noise and present a canonical set of codewords for the 4b/10b line code. Additionally, we show that maximum clique enumeration is #P-hard.

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Space Responsive Multithreaded Processor (SRMTP) for Spacecraft Control

Nakabeppu S., Ide Y., Takahashi M., Tsukahara Y., Suzuki H., Shishido H., Yamasaki N.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings) 2020.04

Research paper (international conference proceedings), Accepted

Access to Document (DOI)

Implementation of fluid scheduling using IPC control mechanism

Tsukahara Y., Nobuyuki Y.

Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS (Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS) 2019-December 402 - 405 2019.12

Research paper (international conference proceedings), Accepted, ISSN 15219097

In real-Time systems such as automobiles, correctness of processing tasks depends not only on its result, but also on time. Real-Time scheduling is a basic approache to achieve real-Time execution in real-Time systems. Fluid scheduling is an optimal real-Time scheduling model, which keeps the execution speed of each task proportional to its processor utilization. However, the speed of a task cannot be controlled arbitrarily on a general processor, making it impossible to implement fluid scheduling directly. Therefore, there have been many studies on pseudo fluid scheduling where the algorithm is based on repeat task execution which speed is constant in an interval. We apply the special mechanisms of Responsive MultiThreaded Processor (RMTP) to the novel control mechanism in order to implement fluid scheduling directly. RMTP is a prioritized SMT processor for real-Time processing, which has 1. a thread speed control mechanism which controls execution speed of each thread and 2. a context cache enabling context switches in four clock cycles. In this paper, by adding a novel thread speed control mechanism, execution speeds of 40 threads are controlled to be constant over short time intervals, directly making fluid scheduling possible.

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Fast interrupt handling scheme by using interrupt wake-up mechanism

Wada R., Yamasaki N.

Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019 (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019) 109 - 114 2019.11

Research paper (international conference proceedings), Accepted

In recent years, embedded real-time systems have grown in complexity and are required to be able to handle both periodic and aperiodic tasks. When an external interrupt occurs via an I/O peripheral, the program counter jumps to the corresponding exception vector. This results in large overhead due to context switching. However, embedded real-time systems are required to execute tasks in real-time with high precision. The Responsive Multithreaded Processor (RMTP), a prioritized SMT CPU, consists of eight hardware contexts treated as eight logical processing cores and has various hardware mechanisms for fine-grained real-time processing on the order of 10 μs. One hardware mechanism implemented in RMTP is an interrupt wake-up mechanism that enables interrupt-triggered thread wake ups. When a thread is designated to be an interrupt handling thread, it starts execution one clock cycle after an interrupt occurs. In this paper, we design and implement a software mechanism which reduces the interrupt response time by using this mechanism and demonstrate the effectiveness of our proposed method by RTL simulations. Evaluation results show that our proposed method achieves high real-time performance by reducing the interrupt response time by up to 82% compared to the baseline.

Access to Document (DOI)

Finding the maximum number of symbols for the 4b/10b line code with error correction

Takeda M., Yamasaki N.

Research paper (international conference proceedings), Accepted

In this paper, we present 20 symbols for the error correcting 4b/10b line coding scheme, increasing the number of available symbols from the 18 originally proposed. The two additional symbols are used to supplement special control codes and increase compatibility with other line codes such as 8b/10b. In addition, we show that the 20 found is the maximum number of symbols possible for 4b/10b by formulating the problem as the maximum clique problem, an NP-hard problem. Finally, we show that the generalized problem of finding a set with the maximum number of symbols is NP-hard as well.

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Experimental validation of agile attitude control with sinc function-based profiler for reducing residual vibrations

Kamiya T., Shimoda K., Ozawa Y., Yokota K., Satoh T., Yamasaki N.

Proceedings of the International Astronautical Congress, IAC (Proceedings of the International Astronautical Congress, IAC) 2019-October 2019

Research paper (international conference proceedings), Accepted, ISSN 00741795

This paper presents a tracking control system combining feedforward and feedback with shaped input, using a benchmark problem applied to a two-mode system. Simulations and experimental validation of the new control system for tracking control of flexible spacecraft including comparison with conventional methods are presented. The results show that the residual vibrations after the moves by the proposed control system are smaller than the conventional methods in the presence of an unknown high-order flexible mode. Sinc function-based command shaping where the spacecraft attitude is controlled along a sequentially commanded trajectory and the residual vibration after the move can be significantly reduced. Sinc function is known as an extra-insensitive function which has no frequency response above a certain threshold frequency. Three feedback controllers are applied to the control system and compared using the benchmark problem. This controller design has several unique characteristics. First, the sinc function-based shaped input is designed to reduce residual vibrations after maneuvers under the existence of unknown high-order mode. Conventional input shapers for flexible spacecraft are not effective for multi-mode system with unknown flexible modes, where actual flexible spacecraft usually has such unknown high-order flexible modes. Second, only the dynamics of the low-order mode need to be considered in designing all the feedforward, feedback controller, and shaped input. Experimental validation is performed by hardware-in-the-loop (HIL) test configuration with newly developed real-time onboard computer to evaluate the feasibility of processing load by the proposed algorithms for real-time processing. Because the proposed algorithms do not contain any iteration algorithm, the proposed algorithms can be implemented in actual satellites with feasible processing load. The assumed two-mode system represents the most simplified multi-mode system with unknown high-order mode, so the similar results can be expected for systems equipped with more complicated flexible structures.

Analysis of body bias control using overhead conditions for real time systems: A practical approach

Torres C.C.C., Okuhara H., Yamasaki N., Amano H.

IEICE Transactions on Information and Systems (IEICE Transactions on Information and Systems) E101D ( 4 ) 1116 - 1125 2018.04

Research paper (scientific journal), Accepted, ISSN 09168532

In the past decade, real-Time systems (RTSs), which must maintain time constraints to avoid catastrophic consequences, have been widely introduced into various embedded systems and Internet of Things (IoTs). The RTSs are required to be energy efficient as they are used in embedded devices in which battery life is important. In this study, we investigated the RTS energy efficiency by analyzing the ability of body bias (BB) in providing a satisfying tradeoff between performance and energy. We propose a practical and realistic model that includes the BB energy and timing overhead in addition to idle region analysis. This study was conducted using accurate parameters extracted from a real chip using silicon on thin box (SOTB) technology. By using the BB control based on the proposed model, about 34% energy reduction was achieved.

Access to Document (DOI)

Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology

Cortes C., Amano H., Yamasaki N.

2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings (2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings) 2017-November 1 - 6 2018.03

Research paper (international conference proceedings), Accepted

It is essential for any embedded systems and increasing popularity of Internet of Things (IoT) be energy efficient. Such systems tend to work intermittently and reducing leakage in the idle time is essential. Energy reduction techniques bring the system to a low power mode which also provokes transition overheads. If such overheads are not considered, the task may not be schedulable under a given deadline. To get a gain in energy savings, the idle state must be longer than a minimum required time. This time is referred as Break Even Time (BET). To properly design efficient algorithms and schedulers we must calculate and include the BET. In this paper, we present the first studies to examine the BET using accurate parameters extracted from a real chip using Silicon On Thin Box (SOTB) technology employing Body Bias Control (BB) energy saving technique. In this study, we demonstrate the BET range for SOTB microcontrollers, on the order of 0.5ms up to 1ms.

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A Low Latency Real-time Execution with Interrupt Wake-up Mechanism on RMT Processor

KOHEI OSAWA, KEIGO MIZOTANI, HIROYUKI CHISHIRO, YAMASAKI NOBUYUKI

情報処理学会論文誌 58 ( 2 ) 531 - 543 2017.02

Performance Evaluation of RUNT Algorithm

Hiroyuki Chishiro, Masayoshi Takasu, Rikuhei Ueda, YAMASAKI NOBUYUKI

ACM SIGBED Review 13 ( 1 ) 15 - 21 2016.01

Research paper (scientific journal)

An Integration of Imprecise Computation Model and Real-Time Voltage and Frequency Scaling on Responsive Multithreaded Processor

Keigo Mizotani, Yusuke Hatori, Yusuke Kumura, Masayoshi Takasu, Hiroyuki Chishiro, Yamasaki Nobuyuki

International Journal of Computers and Their Applications 22 ( 3 ) 127 - 135 2015.09

Research paper (scientific journal)

Zero-Jitter Semi-Fixed-Priority Scheduling with Harmonic Periodic Task Sets

Hiroyuki Chishiro, Yamasaki Nobuyuki

International Journal of Computers and Their Applications 22 ( 3 ) 118 - 126 2015.09

Research paper (scientific journal)

インプリサイス計算モデルにおける温度を考慮した動的電圧周波数制御の実機評価

溝谷圭悟, 上田陸平, 高須雅義, 千代浩之, 松谷宏紀, 山崎信行

情報処理学会論文誌 55 ( 8 ) 1841 - 1855 2014.08

Research paper (scientific journal), Accepted

Implementation of ITRON Specification OS for RMT Processor

上田陸平, 藤井啓, 千代浩之, 松谷宏紀, 山崎信行

情報処理学会論文誌 54 ( 7 ) 1835 - 1848 2013.07

Accepted

Recent advances in embedded systems demands high-performance under real-time constraints. Responsive Multithreaded Processor (RMT Processor) employs prioritized Simultaneous Multithreading (SMT) architecture with hardware-assisted context switch for such high-end embedded systems. In this paper, real-time OS based on ITRON specification is extended to support multithread processing on RMT Processor. Thread-control instructions, which are specific to RMT Processor, are used for thread creation and dispatch to reduce the context switching overhead. A dedicated thread is assigned to interrupt pro- cessing in order to maintain the worst-case interrupt response time when the number of threads executing simultaneously increases. Experimental results show that service calls that include context switch operations are accelerated by the hardware-assisted context switch, task schedulability is also improved accordingly, and the dedicated thread for interrupt processing can maintain the interrupt response time.

Router Microarchitectures for Reducing Priority Inversions in Priority-aware On-chip-networks

谷口将一, 山崎大輝, 笹川雄二郎, 松谷宏紀, 山崎信行

情報処理学会論文誌 54 ( 7 ) 1861 - 1872 2013.07

優先度付きオンチップルータVIX

KAZUTOSHI SUITO, TAKUMA KOGO, DAIKI YAMAZAKI, HIROKI MATSUTANI, YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム 6 ( 1 ) 87-98 2013.01

Research paper (scientific journal), Joint Work, Accepted

Distributed Real-Time Systems on Responsive Link

HIROYUKI CHISHIRO, YAMASAKI NOBUYUKI

Journal of Communication and Computer 9 ( 12 ) 52-61 2012.12

Research paper (scientific journal), Joint Work, Accepted

Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems

KAZUTOSHI SUITO, RIKUHEI UEDA, KEI FUJII, TAKUMA KOGO, HIROKI MATSUTANI, YAMASAKI NOBUYUKI

IEEE Micro 32 ( 6 ) 52-61 2012.12

Research paper (scientific journal), Joint Work, Accepted

Responsive Linkを用いた分散リアルタイムシステム向け高信頼な通信機構の設計と実装

KAZUTOSHI SUITO, TAKUMA KOGO, HIROKI MATSUTANI, YAMASAKI NOBUYUKI

情報処理学会論文誌 53 ( 12 ) 2728-2739 2012.12

Research paper (scientific journal), Joint Work, Accepted

予測を用いたNoC向け混雑回避機構

TANIGUCHI MASAKAZU, MATSUTANI HIROKI, YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム 5 ( 3 ) 112-123 2012.05

Research paper (scientific journal), Joint Work, Accepted

Rate Monotonicに基づく拡張インプリサイスタスク用リアルタイムスケジューリング

HIROYUKI CHISHIRO, AKIRA TAKEDA, KENJI FUNAOKA, YAMASAKI NOBUYUKI

情報処理学会論文誌 52 ( 8 ) 2365-2377 2011.08

Joint Work, Accepted

RT-Est: 準固定優先度スケジューリング向けリアルタイムオペレーティングシステム

HIROYUKI CHISHIRO, YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム 4 ( 1 ) 53-68 2011.02

Joint Work, Accepted

Global EDF-based Scheduling with Laxity-driven Priority Promotion

SHINPEI KATO, YAMASAKI NOBUYUKI

Elsevier Journal of Systems Architecture 57 ( 5 ) 498-517 2011.01

Joint Work, Accepted

SMT/CMP向け固定優先度スケジューリング用動的電圧周波数制御の提案とRMT Processorを用いた実機評価

YUJI IKEDA, SHINPEI KATO, YAMASAKI NOBUYUKI

情報処理学会論文誌 51 ( 12 ) 2216-2226 2010.12

Joint Work, Accepted

優先度付きSMT Processorにおける準固定優先度スケジューリング

HIROYUKI CHISHIRO, YAMASAKI NOBUYUKI

情報処理学会論文誌 51 ( 12 ) 2227-2237 2010.12

Joint Work, Accepted

リアルタイム実行のための優先度付きSMTプロセッサ用IPC制御機構

BUNJI INAGAKI, YAMASAKI NOBUYUKI

情報処理学会論文誌 51 ( 12 ) 2206-2215 2010.12

Joint Work, Accepted

三次元実装パッケージ実現のためのハイブリッドFPCの提案

KIKUO WADA, RYOUJI OHSU, SHIGEKAZU HINO, YAMASAKI NOBUYUKI

電子情報通信学会論文誌 93 ( 11 ) 455-463 2010.11

Joint Work, Accepted

分散リアルタイム通信Responsive Link

YAMASAKI NOBUYUKI, TOSHIHIRO MATSUI

電子情報通信学会誌 92 ( 8 ) 690-694 2009.08

Joint Work

Linuxカーネル用リアルタイムスケジューリングモジュール

YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム 2 ( 1 ) 75-86 2009.03

Research paper (scientific journal), Joint Work

Rate Monotonicに基づくマルチプロセッサ用リアルタイムスケジューリング

YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム 2 ( 1 ) 64-74 2009.03

Research paper (scientific journal), Joint Work

マルチプロセッサ用の最適な実時間スケジューリング

YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム 1 ( 3 ) 1-13 2008.12

Research paper (scientific journal), Joint Work

マルチプロセッサ用の実時間電圧周波数制御

YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム 1 ( 2 ) 96-110 2008.08

Research paper (scientific journal), Joint Work

実時間システムにとって，実時間性を保証可能なシステム使用率が高いほど，プロセッサの電力量の効率にも優れている．本論文では，システム使用率を100%でも実時間性を保証可能なマルチプロセッサ用の実時間スケジューリング手法を拡張した実時間電圧周波数制御手法を提案する．静的な手法は，電圧と周波数をプロセッサ間で均一もしくは独立に制御可能であるとき，理論的に最適である．動的な手法は，静的手法が多項式時間で電圧と周波数を決定可能であることを利用している．シミュレーションによる評価の結果，静的な手法は電圧と周波数を細かく制御可能であれば最適な値に近づくことを示した．また，動的な手法はシステムの選択可能な周波数に依存する度合が低いことを示した．

マルチコアプロセッサにおける非周期タスクの応答性向上

YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム 1 ( 2 ) 83-95 2008.08

Research paper (scientific journal), Joint Work

本論文では，オンチップマルチプロセッサにおいて，周期リアルタイムタスクがデッドラインまでに完了することを保証して，さらに非周期タスクの応答時間をできる限り短縮するためのテンポラルマイグレーション手法を提案する．テンポラルマイグレーション手法は，非周期タスクが到着した際に，そのプロセッサ上で優先度の高い周期タスクが存在する場合は，リアルタイム性を保証できる範囲でそれらの周期タスクを一時的にほかのプロセッサにマイグレーションし，プロセッサ時間を非周期タスクに譲ることで応答性を向上させる．本論文では，テンポラルマイグレーション手法を従来のシングルプロセッサ用Total Bandwidth Server（TBS）アルゴリズムと組み合わせたアルゴリズムを設計する．シミュレーションによる評価では，テンポラルマイグレーション手法を用いることで，TBSアルゴリズムの非周期タスクに対する応答性を劇的に向上できることを示す．

ポーショニング方式に基づく動的優先度スケジューリング

YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム Vol.49 ( No.SIG2 ) 113-126 2008.03

Research paper (scientific journal), Joint Work

RMd2-SIP：マルチプロセッサにおける実時間スケジューリングアルゴリズム

YAMASAKI NOBUYUKI

情報処理学会論文誌: コンピューティングシステム Vol.48 ( No.SIG13 ) 270-286 2007.09

Research paper (scientific journal), Joint Work

Pfairスケジューリングにおけるコンテキストキャッシュの有効利用

YAMASAKI NOBUYUKI

情報処理学会論文誌: コンピューティングシステム Vol.48 ( No.SIG3 ) 1-12 2007.02

Research paper (scientific journal), Joint Work

SMTプロセッサにおける実行効率を向上するリアルタイムスケジューリング

YAMASAKI NOBUYUKI

情報処理学会論文誌: コンピューティングシステム Vol.47 ( No.SIG12 ) 133-146 2006.09

Research paper (scientific journal), Joint Work

Design and Implementation of the Reconfiguration Mechanism for a Modular Humanoid Robot

Tetsuya Taira , Nobuyuki Yamasaki

Journal of Robotics and Mechatronics Vol.18 ( No.3 ) 286-298 2006.06

Research paper (scientific journal), Joint Work

資源制約を持つ拡張インプリサイスタスクの実時間スケジューリング

YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム Vol.46 ( No.SIG16 ) 69-84 2005.12

Research paper (scientific journal), Joint Work

Design and Implementation of the Multimedia Operation Mechanism for Responsive Multithreaded Processor

T. Itou , N. Yamasaki

Journal of Robotics and Mechatronics Vol.17 ( No.4 ) 456-462 2005.08

Research paper (scientific journal), Joint Work

Development of Modular Humanoid Robot based on Functionally Distributed Modular Robot Architecture

Tetsuya Taira , Nobuyuki Yamasaki

Journal of Robotics and Mechatronics Vol.17 ( No.2 ) 130-141 2005.04

Research paper (scientific journal), Joint Work

Prioritized Data Transfer for a Bilateral Robot Control via Real-Time Network System

Yutaka Uchimura,Nobuyuki Yamasaki,Kouhei Ohnishi

Trans. of Institute of Electrical Engineers of Japan Vol.125 ( No.2 ) 199-204 2005.02

Research paper (scientific journal), Single Work

Responsive Multithreaded Processor for Distributed Real-Time Systems

YAMASAKI NOBUYUKI

Journal of Robotics and Mechatronics Vol.17 ( No.2 ) 130-141 2005

Research paper (scientific journal), Single Work

Responsive Multithreaded Processor の命令供給機構

YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム Vol.45 ( No.SIG11 ) 105-118 2004.10

Research paper (scientific journal), Joint Work, Accepted

人間支援のための分散リアルタイムネットワーク基盤技術プロジェクトから：RMT Processorの紹介

YAMASAKI NOBUYUKI

計測自動制御学会計測と制御 Vol.43 ( No.6 ) 487-491 2004.06

Single Work

Design Concept of Responsive Multithreaded Processor for Distributed Real-Time Control

Nobuyuki Yamasaki

Journal of Robotics and Mechatronics Vol.16 ( No.2 ) 194-199 2004.04

Research paper (scientific journal), Single Work

分散制御用リアルタイム通信Responsive Linkの設計および実装

YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム Vol.45 ( No.SIG3 ) 50-63 2004

Research paper (scientific journal), Single Work, Accepted

Functionally Distributed Control Architecture for Autonomous Mobile Robots

Tetsuya Taira,Nobuyuki Yamasaki

Journal of Robotics and Mechatronics Vol.16 ( No.2 ) 217-224 2004

Research paper (scientific journal), Joint Work

Real-time Network System by Responsive Processor and Its Application to Bilateral Robot control

Y. Uchimura , N. Yamasaki , T. Yakoh and K. Ohnishi

Transactions of the Society of Instrument and Control Engineers Vol.40 ( No.2 ) 199-206 2004

Research paper (scientific journal), Joint Work

An Integrated Approach for Implementing Imprecise Computations", IEICE Transactions on Information and Systems

Hidenori Kobayashi,Nobuyuki Yamasaki

IEICE Transactions on Information and Systems E86-D ( No.10 ) 2003.10

Research paper (scientific journal), Joint Work

Responsive Multithreaded Processorの命令実行機構

YAMASAKI NOBUYUKI

情報処理学会論文誌コンピューティングシステム Vol.44 ( No.SIG 11 ) 226-235 2003.08

Research paper (scientific journal), Joint Work, Accepted

並列分散制御用レスポンシブプロセッサ

YAMASAKI NOBUYUKI

日本ロボット学会誌 Vol.21 ( No.1 ) 30-32 2003.01

Single Work

分散リアルタイムネットワーク用プロセッサとその応用

YAMASAKI NOBUYUKI

情報処理学会情報処理 Vol.44 ( No.1 ) 6-13 2003.01

Single Work

人間支援のための分散リアルタイムネットワーク基盤技術プロジェクトの紹介

YAMASAKI NOBUYUKI

情報処理学会情報処理 Vol.44 ( No.1 ) 3-5 2003.01

Joint Work

不揮発性メモリを用いた永続システムの設計方法

YAMASAKI NOBUYUKI

電子情報通信学会論文誌D-I 2002.09

Research paper (scientific journal), Joint Work

分散リアルタイム制御システムの設計方法

YAMASAKI NOBUYUKI

第5回組み込みシステム開発技術展 2002.06

Single Work

並列分散リアルタイム制御用レスポンシブプロセッサ

山﨑信行

計測自動制御学会計測と制御 Vol.40 ( No.12 ) 884-877 2001.12

Research paper (scientific journal), Single Work

A Real-Time Network Manager for Distributed Imprecise Computation

H. Kobayashi, K. Katoh, N. Yamasaki, Y. Anzai

IFAC Conference on New Technologies for Computer Control 2001.11

Joint Work, Accepted

A New Processor Architecture for Real-Time Systems

M. Uchiyama, T. Itou, J. Sato, N .Yamasaki, Y. Anzai

IFAC Conference on New Technologies for Computer Control 2001.11

Joint Work, Accepted

並列分散リアルタイム処理

YAMASAKI NOBUYUKI

第15回MST2001カンファレンス 2001.11

Single Work

Responsive Processor for Parallel/Distributed Real-Time Control

N. Yamasaki

IEEE/RSJ International Conference on Intelligent Robots and Systems 2001.10

Single Work, Accepted

Design and Implementation of Responsive Processor for Parallel/Distributed Control and Its Development Environments

N. Yamasaki

Journal of Robotics　and Mechatronics　 Vol.13 ( No.2 ) 125-133 2001.09

Single Work

A Management Scheme of Hardware Modules for Reconfigurable Robot Systems

I. Takata, H. Kobayashi, T. Kojima, N. Yamasaki, Y. Anzai

IEEE International Conference on Information Technology in Mechatronics 2001.09

Joint Work, Accepted

Design and Implementation of Responsive Processor for Parallel/Distributed Control and Its Development Environments

YAMASAKI NOBUYUKI

Journal of Roboticsand Mechatronics Vol.13 ( No.2 ) 125-133 2001.09

Research paper (scientific journal), Single Work

並列プロセッサアーキテクチャの動向と将来性

山﨑信行

第4回組込みシステム開発技術専門セミナー Vol.ES-19 35-85 2001.06

Single Work

並列分散リアルタイム制御用レスポンシブ・プロセッサ

山﨑信行、松井俊浩

日本ロボット学会誌 Vol.19 ( No.3 ) 68-77 2001.04

Research paper (scientific journal), Joint Work

Responsive Processor for Parallel/Distributed Real-Time Control

N. Yamasaki

IEEE ICECCS2000　(Tutorial)　 1-6 2000.09

Single Work, Accepted

オフィスロボットJijo-2の音声対話システム

松井俊浩、麻生英樹、John Fry、浅野太、本村陽一、原功、栗田多喜夫、速水悟、山﨑信行

日本ロボット学会誌 Vol.18 ( No.2 ) 142-149 2000.02

Research paper (scientific journal), Joint Work

Responsive Processor for Parallel/Distributed Real-Time Processing

N. Yamasaki, T. Matsui

COOL Chips II　 153-167 1999.04

Joint Work, Accepted

A Responsive Processor for Parallel/Distributed Real-time Processing

N. Yamasaki, T. Matsui

Symposium on Global Information Processing　Technology 1999　 Vol.1 101-109 1999.04

Joint Work

並列分散リアルタイム制御用高速応答プロセッサの提案

山﨑信行

オーム社エレクトロニクス ( No.3 ) 58-61 1998.03

Single Work

A Functionally Distributed Responsive Micro Controller for Distributed Real-time Processing

N. Yamasaki, T. Matsui

IEEE/RSJ International Conference on Intelligent Robots and Systems　 Vol.2 793-798 1997.09

Joint Work, Accepted

An Office Conversant Mobile Robot That Learns by Navigation and Conversation

T. Matsui, H. Asoh, I. Hara, Y. Motomura,S. Akaho, T. Kurita, F. Asano, N. Yamasaki

1997 Real World Computing Symposium　 59-62 1997

Joint Work, Accepted

パーソナルロボット用機能別並列計算アーキテクチャASPIREのRISCを用いた設計と実装

山﨑信行、安西祐一郎

日本ロボット学会誌 Vol.14 ( No.4 ) 123-131 1996.04

Research paper (scientific journal), Joint Work

パーソナルロボットのためのアクティブインタフェースの設計と実装

山﨑信行、安西祐一郎

日本ロボット学会誌 Vol.14 ( No.3 ) 141-149 1996.03

Research paper (scientific journal), Joint Work

パーソナルロボット用機能別並列計算機アーキテクチャ:ASPIRE

山﨑信行、安西祐一郎

情報処理学会論文誌 Vol.37 ( No.1 ) 81-91 1996.01

Joint Work

Applying Personal Robots and ActiveInterface to Video Conference Systems

N. Yamasaki, Y. Anzai

International Conference on Human-Computer Interaction　 Vol.2 243-248 1995.07

Joint Work

Active Interface for　Human-Robot Interaction

N. Yamasaki, Y. Anzai

IEEE International Conference on Robotics　and Automation　 Vol.3 3103-3109 1995.05

Joint Work, Accepted

物理学におけるコンピュータ・シミュレーション

山﨑信行

固体物理 Vol.29 ( No.4 ) 158-159 1994.04

Single Work

RT-Michele : 分散環境に対応したヒューマン・ロボット・インタフェースシステム

中内靖、川杉憲二、岡田豊史、山﨑信行、安西祐一郎

日本ロボット学会誌 Vol.12 ( No.3 ) 431-438 1994.03

Research paper (scientific journal), Joint Work

Designing Interfaces of Autonomous Agents

T. Yakoh, N. Yamasaki, Y. Anzai

International Conference on Human-Computer Interaction　 Vol.2 86-91 1993

Joint Work, Accepted

Multi-Agent Interface Architecture for Human-Robot Cooperation

Y. Nakauchi, T. Okada, N. Yamasaki, Y. Anzai

IEEE International　Conference on Robotics and Automation　 2786-2788 1992.05

Joint Work, Accepted

Human-Robot Interface Architecture for Distributed Environments

Y. Nakauchi, K. Kawaguchi, T. Okada, N. Yamasaki, Y. Anzai

IEEE International Workshop on Robot and Human Communication　 413-418 1992

Joint Work, Accepted

A Request of the Robot: An Experiment with the Human-Robot Interactive System HuRIS

Y. Yamamoto, M. Sato, K. Hiraki, N. Yamasaki, Y. Anzai

IEEE International Workshop on Robot and Human Communication　 204-209 1992

Joint Work, Accepted

はじめて学ぶCプログラミング

山﨑信行、高木聡

ソフトバンク社 C MAGAZINE 1989.10

Research paper (scientific journal), Joint Work

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