Presentations -
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The MINC chip
Asia and South Pacific Design Automation Conference 1998,
1998.01 -
Wavelength division multiple access ring-virtual topology on a simple ring network
3rd IEEE International Symp.on Parallel Architecture，Algorithms，and Networks,
1997.12 -
Adaptive Routing on the Recursive Diagonal Torus
International Shimposium on High Performance Computing,
1997.11 -
Memory based light weight couumincation architecture for local area distibuted computing
International Workshop on Inovative Architecture,
1997.10 -
A reconfigurable markov chain simulator for analysis of parallel systems
IEEE International Conference on Innovetive Systems in Silicon,
1997.10 -
nD-MIN:Multistage Interconnection Network with multiple dimeusional structure
ISCA 10th International Conference on Parallel and Distributed Computing Systems,
1997.10 -
Toward the Realistic ”Virtual Hardware”
International Workshop on Inovative Architecture,
1997.10 -
A reconfigurable sensor-data processing system for perfonal robots
Field-Programmable Logic'97,
1997.09 -
Shared vs.Snoop:Evaluation of Cache Structure for Single Chip Multiprocessors
Euro-Par'97,
1997.08 -
An Emulation System of the WASMⅡ:A Data driven computer on a Virtual Hardware
Y.Shibuta，X.Ling，H.Amano
Field-Programmable Logic'96,
1996.09 -
ATTEMPT-1:A Reconfigurable Multiprocessor Testbed
K.Inoue，T.Kisuki，M.Okuno，E.Shimizu，T.Terasawa，H.Amamo
Fieldf-Programmable Logic'96,
1996.09 -
The JUMP-1 Router chip:A Veratile router for Supporting a Distributed Shared Memory
H.Nishi， K.Nishimura， K.Anjo， H.Amano， T.Kudoh
IEEE 15th Annual Phoenix Conference on Computers and Communications,
1996.03 -
Fault Torelant MIN with Multiple Outlets
A.Funahashi， T.hanawa， H.Amano
IEEE Pacific Rim International Symposium on Fault Tolerant Systems,
1995.12 -
A Preprocessing system of the EULASH:An Environment for Efficient use of Multiprocessors with Local Memory
J.Yamanoto， D.Hattori， T.Tokuyoshi， Y.Yamaguchi， H.Amano
7th IASTED/ISMM International Conference on Parallel and Distributed computing and systems,
1995.10 -
MINC: Multistage Interconnection Network with Cache Control Mechanism
T.Hanawa，H.Yasukawa，K.Nishimura，H.Amano
ISCA/IEEE 9th International Conference on Parallel and Distributed Computing Systems,
1995.09 -
Structure and Performance of the MDX:A Network Class for Large Scale Multiprocessors
A.Murata，T.Boku，T.Harada，H.Amano
ISCA/IEEE 9th International Conference on Parallel and Distributed Computing Systems,
1995.09 -
Hierarchical bit-map directory schemes on the RDT interconnection network for a massively parallel processor JUMP-1
T.Kudoh，H.Amano，T.Matsumoto，K.Hiraki，Y.Yang
International Conference on Parallel Processing,
1995.08 -
An LSI implementation of the Simple Serial Synchronized Multistage Interconnection Network
T.Kamei，M.Sasahara，H.Amano
Synthesis and System Integration of Mixed Technologies,
1995.08 -
A Cache Coherency Protocol for Multiprocessor Chip
T.Terasawa，H.Amano
International Conference on Wafer Scale Integration,
1995.01 -
Overview of the JUMP-1，an MPP Prototype for General Purpose Parallel Computations
K.Hiraki，H.Amano，M.Kuga，T.Sueyoshi，T.Kudoh，H.Nakashima，H.Nakajo，H.Matsuda，T.Matsumoto.S.Mori
International Symposium on Parallel Architecture，Algorithms and Networks,
1994.12