Presentations -
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Zynq Cluster for CFD Parametric Survey
AMANO HIDEHARU
the International Symposium on Applied Reconfigurable Computing (ARC) (Lio De Janeiro) ,
2016.02,Oral presentation (general)
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Randomizing Packet Memory Networks for Low-latency Processor-memory Communication
AMANO HIDEHARU
The 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP) (Crete) ,
2016.02,Oral presentation (general), IEEE
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Power Optimization considering the chip temperature of low power reconfigurable accelerator CMA-SOTB
AMANO HIDEHARU
he 4rd International Symposium on Computing and Networking (CANDAR),
2015.12,Oral presentation (general), IEICE
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A 297MOPS/0.4mW Ultra Low Power Coarse-grained Reconfigurable Accelerator CMA-SOTB-2
AMANO HIDEHARU
The 10th International Conference on ReConFigurable Computing and FPGAs (IEEE) ,
2015.12,Oral presentation (general)
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On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck
AMANO HIDEHARU
the 9th ACM/IEEE International Symposium on Networks-on-Chip (NOCS) (Banqueber) ,
2015.10,Oral presentation (general)
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REDUCTION CACLULATOR IN AN FPGA BASED SWITCHING HUB FOR HIGH PERFORMANCE CLUSTERS
AMANO HIDEHARU
International Conference on Field Programmable Logic and Applications (London) ,
2015.09,Poster presentation, IEEE
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3D Shared Bus Architecture Using Inductive Coupling Interconnect
AMANO HIDEHARU
EEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chips (McSoC) (Torino) ,
2015.09,Oral presentation (general), IEEE
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Expandable Chip Stacking Method for Many-Core Architectures Consisting of Tiny Chips,
AMANO HIDEHARU
EEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chips (McSoC) (Torino) ,
2015.09,Oral presentation (general), IEEE
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A Metamorphotic Network-on-Chip for Various Types of Parallel Applications
AMANO HIDEHARU
IEEE International Conference on Application-specific Systems, Architectures and Processors (Toronto) ,
2015.07,Oral presentation (general), IEEE
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An Optimal Power Supply and Body Bias Voltage for Ultra Low Power Micro-Controller with Silicon on Thin BOX MOSFET
AMANO HIDEHARU
International Symposium on Low Power Electronics and Design (Rome) ,
2015.07,Oral presentation (general), IEEE
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Parallel processing of Breadth First Search by Tightly Coupled Accelerators
AMANO HIDEHARU
the 21st International Conference on Parallel and Distributed Processing Techniques and Applications (Las Vegas) ,
2015.07,Oral presentation (general)
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Breadth First Search on Cost-efficient Multi-GPU Systems
AMANO HIDEHARU
the International Symposium on Highly-Efficient Accelerators and Reconfigureable Technologies (HEART) (Boston) ,
2015.05,Oral presentation (general)
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Off-loading LET generation to PEACH2: A switching hub for high performance GPU clusters
AMANO HIDEHARU
International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (Boston) ,
2015.05,Oral presentation (general)
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Spatial and Temporal Granularity Limits of Body Biasing in UTBB-FDSOI
Johannes Maximilian Kuehn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel
Design Automation & Test in Europe (DATE 2015) (Grenoble, France) ,
2015.03,Oral presentation (general)
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Time Analysis of Applying Back Gate Bias for Reconfigurable Architectures with SOTB MOSFET
Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano
The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2015) (Yulin, Taiwan) ,
2015.02 -
Data Reduction and Parallelization for Human Detection System
Mao Hatto, Takaaki Miyajima, Hideharu Amano
The 19th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI2015) (Yulin, Taiwan) ,
2015.02,Poster presentation
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Image Processing bu a 0.3V 2mW Coarse grained reconfigurable accelerator CMA-SOTB with a solar battery
Yu Fujita, Koichiro Masuyama, Hideharu Amano
International Conference on Field Programmable Technologies (Shanghai China) ,
2014.12,Poster presentation
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A preliminarily evaluation of PEACH3: a switching hub for tightly coupled accelerators,
Takuya Kuhara, Takahiro Kaneda, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano
2nd International Workshop on Computer Systems and Architectures (Shizuoka, Japan) ,
2014.12,Oral presentation (general)
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FPGA Implementation of Viscous Function in a package for Computational Fulid Dynamics
Dipikarini Mishra, Mao Hatto, Takuya Kuhara, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
Workshop on 2014 2nd International Symposium on Computing and Networking (Shizuoka, Japan) ,
2014.12,Oral presentation (general)
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Hardware/Software co-design Architecture for Blokus Duo Solver,
Naru Sugimoto, Hideharu Amano
The International Conference on Field Programmable Technologies (Shanghai, China) ,
2014.12,Poster presentation