Presentations -
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Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs
{H. Matsutani} and {M.Koibuchi} and {D.Ikebuchi} and {K.Usami} and {H.Nakamura} and {H. Amano}
NoCS 2010 (Grenoble, FRANCE) ,
2010.05,Oral presentation (general), IEEE
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Geyser-1 and Geyser-2: MIPS R3000 CPU Chips with Fine-grain Runtime Power Gating
{L. Zhao} and {D. Ikebichi} and {Y.Saito} and {M.Kamata} and {N.Seki} and {Y.Kojima} and {H.Amano} and {S.Koyama} and {T.Hashida} and {Y.Umahashi} and {D.Masuda} and {K.Usami} and {T.Sunata} and {K.Kimura} and {M.Namiki} and {S.Takeda} and {H.Nakamura} and {M.Kondo}
IEEE CoolChips XIII (Yokohama, JAPAN) ,
2010.04,Oral presentation (general)
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A Performance Evaluation of CUBE: One-dimensional 512 FPGA Cluseter
M. Yoshimi} and {Y. Mishikawa} and {M.Miki} and {Y.Hiroyasu} and {H.Amano} and {O.Mencer}
International Symposium on Advanced Reconfigurable Computing (Bangkok, Thailand) ,
2010.03,Oral presentation (general)
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Low Power Image Processing using MuCCRA-3: A Dynamically Reconfigurable Processor Array
Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda and AMANO HIDEHARU
International Conference on Field Programmable Technology(ICFPT09) (Sydny, Australia) ,
2009.12,Other, IEEE
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A Study on Interconnection Networks of the Dynamically Reconfigurable Processor MuCCRA
Masaru Kato, Toru Sano, Yoshiki Saito AMANO HIDEHARU
International Conference on Field Programmable Technology (ICFPT) (Sydny, Australia) ,
2009.12,Poster presentation
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Leakage Power Reduction for Coarse-Grained Dynamically Reconfigurable Processor Arrays Using Dual VT Cells
Kei'ichiro Hirai, Masaru Kato, Yoshiki Saito and AMANO HIDEHARU
International Conference on Field Programmable Technology (ICFPT09) (Sydny, Australia) ,
2009.12,Oral presentation (general)
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MuCCRA-Cube: a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link
Shotaro Saito and Yoshinori Kohama and Yasufumi Sugimori and Yohei Hasegawa and Hiroki Matsutani and Toru Sano and Kazutaka Kasuga and Yoichi Yoshida and Kiichi Niitsu and Noriyuki Miura and Tadahiro Kuroda and HIDEHARU AMANO
International Conference on Field Programmable Logic and Applications (FPL'09) (Prague, Poland) ,
2009.08,Oral presentation (general)
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Performance Analysis of ClearSpeed's CSX600 Interconnects
Yuri Nishikawa and Michihiro Koibuchi and Masato Yoshimi and Akihiro Shitara and Kenichi Miura and AMANO HIDEHARU
International Symposium on Parallel and Distributed Processing with Applications (Chendju, China) ,
2009.08,Oral presentation (general)
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Modularizing Flux Limiter Functions for a Computational Fluid Dynamics Accelerator on FPGAs
Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, AMANO HIDEHARU
International Conference on Field Programmable Logic and Applications (FPL09) (Prague, Poland) ,
2009.08,Poster presentation
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Japanese Dynamically Reconfigurable Processors
AMANO HIDEHARU
Engineering of Reconfigurable Systems and Algorithms (ERSA09) (Las Vegus) ,
2009.07,Oral presentation (invited, special)
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A Real Chip Evaluation of MuCCRA-3: A Low Power Dynamically Reconfigurable Processor Array
Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tanbunheng, Yoshihiro Yasuda and AMANO HIDEHARU
Engineering of Reconfigurable Systems and Algorithms (Las Vegus, U.S.A.) ,
2009.07,Poster presentation, IEEE
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Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors
Toru Sano, Yoshiki Saito and AMANO HIDEHARU
Engineering of Reconfigurable Systems and Algorithms (ERSA09) (Las Vegus, U.S.A.) ,
2009.07,Oral presentation (general)
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Evaluation of a Multi-core Reconfigurable Architecture with Variable Core Size
YVu Mah Tuan and AMANO HIDEHARU
Reconfigurable Architecture Workshop (RAW'09) (Roma, Itary) ,
2009.05,Oral presentation (general), IEEE
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RHiNET-3/SW an 80-Gbit/s high-speed network switch for distributed parallel computing
S.Nishimura, T.Kudoh, H.Nishi, J.Yamamoto, R>Ueno, K.Harasawa, S.Fukuda, Y.Shikichi, S.Akutsu, K.Tasho, H.Amano
Hot Interconnect 9,
2001.08,Oral presentation (general)
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MMLRU selection Function: An output selection function on Adaptive Routing
M.Koibuchi, A.Funahashi, A.Jouraku, H.Amano,
ISCA International Conference on Parallel and Distributed Computing Systems.,
2001.08,Oral presentation (general)
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General purpose Monitoring System POT for parallel computers
Y.Kanamori, M.Shimada, H.Amano
International Conference on Parallel and Distributed Processing Techniques and Applications,
2001.06 -
Performance evaluation of a multicast mechanism for a massively parallel machine JUMP-1
N.Suzuki, H.Amano, T.Tamura, Y.Osana, K.Nishimura,
International Conference on Parallel and Distributed Processing Techniques and Applications,
2001.06 -
Multistage Interconnection Network Recursive Clos II (R-ClosII): a scalable Hierarchical network for a compiler directed multiprocessor ASCA
T.Morimura, K.Tanaka, K.Iwai, H.Amano,
International Conference on Parallel and Distributed Processing Techniques and Applications,
2001.06 -
Performance evaluation of Parallel I/O Mechanism on a Massively Parallel Processing System JUMP-1
Y.Osana, H.Nakajo, N.Suzuki, T.Tamura, H.Amano
International Conference on Parallel and Distributed Processing Techniques and Applications,
2001.06 -
General purpose Monitoring System POT for parallel computers
Y.Kanamori, M.Shimada, H.Amano
International Conference on Parallel and Distributed Processing Techniques and Applications,
2001.06