Presentations -
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Vertical link on/off control methods for wireless 3-D NoCs
Zhang Hao
ARCS2012 (International Synmposium on Architecture of Computing Systems) (Prague, Czech) ,
2012.02,Oral presentation (general)
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CMA-2 : The second prototype of a low power reconfigurable accelerator
IZAWA MAI
ASP-DAC2012 (Sydney, Australia) ,
2012.01,Poster presentation, IEEE
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Cool Mega-Array: a highly energy efficient reconfigurable accelerator
M.Ozaki} and H.Amano, and et.al.
ICFPT2011 (Deli, India) ,
2011.12,Oral presentation (general), IEEE
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Reducing Power for Dynamically Reconfigurable Processor Array by Reducing Number of Reconfigurations
M.Kimura} and {K.Hironaka} and {H.Amano
ICFTP 2011 (Deli, India) ,
2011.12,Oral presentation (general), IEEE
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Vegeta: An Implementation and Evaluation of Development-support Middleware on Multiple OpenCL Platform
{A.Shitara} and {T.Nakahama} and {M.Yamada} and {T.Kamata} and {Y.Nishikawa} and {M.Yoshimi} and {H.Amano}
ICNC2011 (Osaka, Japan) ,
2011.11,Oral presentation (general), IEICE
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Power-aware Multi-tree Ethernet for HPC Interconnects
{M.Koibuchi} and {T.Watanabe} and {A.Minamihata} and {M.Nakao} and {T.Hiroyasu} and {H.Matsutani} and {H.Amano
ICNC 2011 (Osaka, Japan) ,
2011.11,Oral presentation (general)
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Time and Space-Multiplexed Compilation Challenge for Dynamically Reconfigurable Processors
T.Toi} and {T.Awashima} and {M.Motomura} and {H.Amano
IEEE MWSCAS 2011 (Seoul, Korea) ,
2011.08,Oral presentation (invited, special)
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Implementation and Evaluation of Program Development Middleware for Cell Broadband Engine Clusters
T.Kamata} and {M.Yamada} and {A.Shitara} and {Y.Nisikawa} and {M.Yoshimi} and {H.Amano
PDPTA 2011 (LasVegas, USA.) ,
2011.07,Oral presentation (general), IASTED
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High Speed CRC with 64-bit generator polynomial on an FPGA'
{A.Amila} and {H.Amano}
HEARTS 2011 (London, UK.) ,
2011.06,Oral presentation (general)
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An Implementation of Out-Of-Order Execution System for Acceleration of Computational Fluid Dynamics on FPGAs'
{H.Matsutani} and {Y.Take} and {D.Sasaki} and {M.Kimura} and {Y.Ono} and {Y.Nishiyama} and {M.Koibuchi} and {T.Kuroda} and {H.Amano}
HEARTS 2011 (London, UK) ,
2011.06,Oral presentation (general), IEICE
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A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs
{H.Matsutani} and {Y.Take} and {D.Sasaki} and {M.Kimura} and {Y.Ono} and {Y.Nishiyama} and {M.Koibuchi} and {T.Kuroda} and {H.Amano}
NoCS 2011 (Pittsburgh, Pennsylvania, USA) ,
2011.05,Oral presentation (general), IEEE
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Execution of a Computational Fluid Dynamics Application on FLOPS-2D, a multi-FPGA platform
{H.Amano} and {H.Morisita} and {K.Inakagata} and {Y.Osana} and {N.Fujita}
DATE Workshop Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing (Grenoble, France) ,
2011.03,Oral presentation (invited, special)
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Dynamic Vdd Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction
T.Yamamoto} and {K.Hironaka} and {M.Kimura} and {K.Usami}
Proc. of International Conference on Advanced Reconfigurable Computing Systems 2012 (England) ,
2011.03,Oral presentation (general), IEEE
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Reducing power consumption for Dynamically Reconfigurable Processor Array with partially fixed configuration mapping
Kazue Hironaka
International Conference on Field Programmable Technologies (Beijin, CHINA) ,
2010.12,Poster presentation, IEEE
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A Variable-pipeline On-chip Router Optimized to Traffic Pattern
Yuto Hirata
International Workshop on Network on Chip Architectures(NoCArc'10) (Atlanta, USA) ,
2010.12,Oral presentation (general)
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Wire Congestion Aware Synthesis for a Dynamically Reconfigurable Processor
Takao Toi
International Conference on Field Programmable Techology (Beijin, CHINA) ,
2010.12,Poster presentation, IEEE
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Recent Trends of Dynamically Reconfigurable Processors
AMANO HIDEHARU
Asia-Pacific Radio Science Conference (Toyama, JAPAN) ,
2010.09,Oral presentation (invited, special)
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A Proposal of Thread Virtualization Environment for Cell Broadband Engine
Masahiro Yamada
International Conference on Parallel and Distributed Systems (Marina del Ray, USA) ,
2010.08,Oral presentation (general)
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A Deadlock-free Non-minimal Fully Adaptive Routing Using Virtual Cut-through Switching
Y. Nishikawa} and {M.Koibuchi} and {H.Matsutani} and {H.Amano}
International Conference on Networking, Architecture and Strage (NAS) (Macau, CHINA) ,
2010.06,Oral presentation (general), IEEE
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Implementation and Evaluation of an Arithmetic Pipeline on FLOPS-2D:Multi-FPGA System
H. Morisita} and {K. Inakagata} and {Y.Osana} and {N.Fujita} and {H.Amano}
International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (Tsukuba, JAPAN) ,
2010.06,Oral presentation (general)