Presentations -

Zynq Cluster for CFD Parametric Survey

AMANO HIDEHARU

the International Symposium on Applied Reconfigurable Computing (ARC) (Lio De Janeiro) , 

2016.02

, 

Oral presentation (general)

Randomizing Packet Memory Networks for Low-latency Processor-memory Communication

AMANO HIDEHARU

The 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP) (Crete) , 

2016.02

, 

Oral presentation (general), IEEE

Power Optimization considering the chip temperature of low power reconfigurable accelerator CMA-SOTB

AMANO HIDEHARU

he 4rd International Symposium on Computing and Networking (CANDAR), 

2015.12

, 

Oral presentation (general), IEICE

A 297MOPS/0.4mW Ultra Low Power Coarse-grained Reconfigurable Accelerator CMA-SOTB-2

AMANO HIDEHARU

The 10th International Conference on ReConFigurable Computing and FPGAs (IEEE) , 

2015.12

, 

Oral presentation (general)

On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck

AMANO HIDEHARU

the 9th ACM/IEEE International Symposium on Networks-on-Chip (NOCS) (Banqueber) , 

2015.10

, 

Oral presentation (general)

REDUCTION CACLULATOR IN AN FPGA BASED SWITCHING HUB FOR HIGH PERFORMANCE CLUSTERS

AMANO HIDEHARU

International Conference on Field Programmable Logic and Applications (London) , 

2015.09

, 

Poster presentation, IEEE

3D Shared Bus Architecture Using Inductive Coupling Interconnect

AMANO HIDEHARU

EEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chips (McSoC) (Torino) , 

2015.09

, 

Oral presentation (general), IEEE

Expandable Chip Stacking Method for Many-Core Architectures Consisting of Tiny Chips,

AMANO HIDEHARU

EEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chips (McSoC) (Torino) , 

2015.09

, 

Oral presentation (general), IEEE

A Metamorphotic Network-on-Chip for Various Types of Parallel Applications

AMANO HIDEHARU

IEEE International Conference on Application-specific Systems, Architectures and Processors (Toronto) , 

2015.07

, 

Oral presentation (general), IEEE

An Optimal Power Supply and Body Bias Voltage for Ultra Low Power Micro-Controller with Silicon on Thin BOX MOSFET

AMANO HIDEHARU

International Symposium on Low Power Electronics and Design (Rome) , 

2015.07

, 

Oral presentation (general), IEEE

Parallel processing of Breadth First Search by Tightly Coupled Accelerators

AMANO HIDEHARU

the 21st International Conference on Parallel and Distributed Processing Techniques and Applications (Las Vegas) , 

2015.07

, 

Oral presentation (general)

Breadth First Search on Cost-efficient Multi-GPU Systems

AMANO HIDEHARU

the International Symposium on Highly-Efficient Accelerators and Reconfigureable Technologies (HEART) (Boston) , 

2015.05

, 

Oral presentation (general)

Off-loading LET generation to PEACH2: A switching hub for high performance GPU clusters

AMANO HIDEHARU

International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (Boston) , 

2015.05

, 

Oral presentation (general)

Spatial and Temporal Granularity Limits of Body Biasing in UTBB-FDSOI

Johannes Maximilian Kuehn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel

Design Automation & Test in Europe (DATE 2015) (Grenoble, France) , 

2015.03

, 

Oral presentation (general)

Time Analysis of Applying Back Gate Bias for Reconfigurable Architectures with SOTB MOSFET

Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano

The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2015) (Yulin, Taiwan) , 

2015.02

Data Reduction and Parallelization for Human Detection System

Mao Hatto, Takaaki Miyajima, Hideharu Amano

The 19th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI2015) (Yulin, Taiwan) , 

2015.02

, 

Poster presentation

Image Processing bu a 0.3V 2mW Coarse grained reconfigurable accelerator CMA-SOTB with a solar battery

Yu Fujita, Koichiro Masuyama, Hideharu Amano

International Conference on Field Programmable Technologies (Shanghai China) , 

2014.12

, 

Poster presentation

A preliminarily evaluation of PEACH3: a switching hub for tightly coupled accelerators,

Takuya Kuhara, Takahiro Kaneda, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano

2nd International Workshop on Computer Systems and Architectures (Shizuoka, Japan) , 

2014.12

, 

Oral presentation (general)

FPGA Implementation of Viscous Function in a package for Computational Fulid Dynamics

Dipikarini Mishra, Mao Hatto, Takuya Kuhara, Yasunori Osana, Naoyuki Fujita, Hideharu Amano

Workshop on 2014 2nd International Symposium on Computing and Networking (Shizuoka, Japan) , 

2014.12

, 

Oral presentation (general)

Hardware/Software co-design Architecture for Blokus Duo Solver,

Naru Sugimoto, Hideharu Amano

The International Conference on Field Programmable Technologies (Shanghai, China) , 

2014.12

, 

Poster presentation

Unbalanced Buffer Tree Synthesis to Suppress Ground Bounce for Fine-grain Power Gating

Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura

International Symposium on System-on-Chip (Tampele, Finland) , 

2014.10

, 

Oral presentation (general)

A Thermal Management System for Building Block Computing System

Yu Fujita, Kimiyoshi Usami, Hideharu Amano

International Conference on Enbedded Multicore/Many-core System on Chips (Aizu, Japan) , 

2014.09

, 

Oral presentation (general), IEEE

Body Bias Control for a Coarse Grained Reconfigurable Accelerator Implemented with Silicon on Thin BOX Technology

Honlian Su, Yu Fujita, Hideharu Amano

International Conference on Field Programable Logic and Applications, (Munich, Germany) , 

2014.09

, 

Oral presentation (general)

A high speed design and implementation of dynamically reconfigurable processor using 28nm SOI technology

Toru Katagiri, Hideharu Amano

International Conference on Field Programable Logic and Applications (Munich, Germany) , 

2014.09

, 

Poster presentation

Design of a Low Power NoC Router using Marching Memory Through type

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura

8th IEEE/ACM International Symposium on Networks-on-Chip (Ferrara, Italy) , 

2014.09

, 

Oral presentation (general), IEEE/ACM

Block Computing Systems with Wireless Inductive Through Chip Interface

AMANO HIDEHARU

the 6th Workshop on Design for 3D Silicon Integration (Lausanne, Switzland) , 

2014.06

, 

Oral presentation (invited, special)

Accelerating Breadth First Search on GPU-BOX

Takuji Mitsuishi, Shimpei Nomura, Jun Suzuki, Yuki Hayashi, Masaki Kan, AMANO HIDEHARU

Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2014) (Sendai, Japan) , 

2014.06

, 

Oral presentation (general)

Performance analysis of the multi-GPU System with ExpEther

Shimpei Nomura, Takuji Mitsuishi Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano

Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2014) (Shendai, Japan) , 

2014.06

, 

Oral presentation (general)

Leakage Reduction using Coarse-Grained Static Body Biasing in a Dynamically Reconfigurable Processor

Johannes Maximilian Kühn, Hideharu Amano, Toru Katagiri, Wolfgang Rosenstiel

Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2014) (Sendai, Japan) , 

2014.06

, 

Poster presentation

A Configurable Switch Mechanism for Random NoCs

Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

CoolChips XVII (Yokohama, Japan) , 

2014.04

, 

Poster presentation, IEEE

A low power NoC router using the marching memory through type

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanebe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura

CoolChips XVII, 

2014.04

, 

Oral presentation (general)

Voltage control considering the chip temperature in the three-dimensional stacked multi-core processors

Yu Fujita, Yusuke Koizumi, Rie Uno, Hideharu Amano

CoolChips XVII (Yokohama, Japan) , 

2014.04

, 

Poster presentation, IEEE

Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors

Masaaki Kondo

DATE2014 (Doresden, Germany) , 

2014.03

, 

Oral presentation (general)

Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips

Hiroki Matsutani

DATE 2014 (Doresden, Germany) , 

2014.03

, 

Oral presentation (invited, special)

Task Level Pipelining on Multiple Accelerators via FPGA Switch

Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa AMANO HIDEHARU, Taksuke Boku

Parallel and Distributed Computing and Networks (Insbruch, Austoria) , 

2014.02

, 

Oral presentation (general)

Design and Control Methodology for Fine Grain Power Gating based on Energy Characterization and Code Profiling of Microprocessors

Kimiyoshi Usami

ASP-DAC 2014 (Singapore) , 

2014.01

, 

Oral presentation (general), IEEE

Introduction to Interconnection Networks

AMANO HIDEHARU

CANDAR2013 (Matsuyama, Japan) , 

2013.12

, 

Public lecture, seminar, tutorial, course, or other speech

A co-processor design of an energy efficient reconfigurable accelerator CMA

AMANO HIDEHARU

CANDAR2013 (Matsuyama, Japan) , 

2013.12

, 

Oral presentation (general)

A low power reconfigurable accelerator using a back-gate bias control technique

Honglian So

International Conference on Field Programmable Technologies (Kyoto Japan) , 

2013.12

, 

Poster presentation, IEEE/Keio Univ.

A Speculative Gather System for Cool Mega-Array

Rie Uno

International Conference on Field Programmable Technologies (Kyoto, Japan) , 

2013.12

, 

Poster presentation, IEEE/Keio Univ.

Partially Reconfigurable Flux Calculation Scheme in Advection Term Computation

Sofian Abu Talip

International Conference on Field Programmable Technologies (Kyoto, Japan) , 

2013.12

, 

Poster presentation, IEEE/Keio Univ.

Power Optimization of a micro-controller with Silicon on Thin Buried Oxide

Kuniaki Kitamori

SASIMI2013 (Sapporo, Japan) , 

2013.10

, 

Poster presentation

A Hardware Complete Detection Mechanism for an Energy Efficient Reconfigurable Accelerator CMA

Akihito Tsusaka

International Conference on Field Programmable Logic and Technologies (Porto, Portogal) , 

2013.09

, 

Poster presentation, IEEE

Demonstration of a Heterogeneous Multi-Core Processor with 3-D Inductive Coupling links

Yusuke Koizumi

International Conference on Field Programmable Logic and Technologies (Porto, Portogal) , 

2013.09

, 

Poster presentation, IEEE

Deadlock-Free Routing Strategy for Stacking 3-D NoCs with Different Topologies

Daisuke Sasaki

HEART2013, 

2013.05

, 

Poster presentation, ACM/IEICE

SMASOTB/LPT-3: The first prototype chip of Cool Mega Array on Silicon On Thin Box

Honlian So

HEART2013, 

2013.05

, 

Poster presentation, ACM/IEICE

A Scalable 3D Heterogeneous Multi-Core Processor with Inductive Coupling ThruChip Interface

Nobuyuki Miura

CoolChips XVI (Yokohama) , 

2013.04

, 

Oral presentation (general), IEEE

Dynamic Power On/Off Method for 3D NoCs with Wireless Inductive Coupling Links

Hao Zhang

COOL Chips XVI (Yokohama, Japan) , 

2013.04

, 

Oral presentation (general), IEEE

Headfirst Sliding Routing: A Time-Based Routing Scheme for Bus-NoC Hybrid 3-D Architecture

"{Takahiro Kagami} and {Hiroki Matsutani} and {Michihiro Koibuchi} and {Hideharu Amano}"

7th ACM/IEEE International Symposium on Networks-on-Chip (Arizona, USA) , 

2013.04

, 

Oral presentation (general)

An FPGA Acceleration for the Kd-tree Search in Photon Mapping

Takuya Kuhara

ARC 2013 (International Symposium on Applied Reconfigurable Computing) (Los Angels, USA) , 

2013.03

, 

Oral presentation (invited, special)

A Case for Wireless 3D NoCs for CMPs

Hiroki Matsutani} and {Paul Bogdan} and {Radu Marculescu} and {Michihiro Koibuchi} and {Tadahiro Kuroda} and {Hideharu Amano

ASP-DAC2013 (Yokohama, Japan) , 

2013.01

, 

Oral presentation (general), IEEE

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Yusuke Koizumi

ICFPT2012 (Seoul, Korea) , 

2012.12

, 

Poster presentation

A Study of Adaptive co-processors for Cyclic Redundancy Checks on an FPGA

Amila Akagic, Hideharu Amano

ICFPT2012 (Seoul, Korea) , 

2012.12

, 

Poster presentation

Reconfigurable Out-Of-Order Mechanism Generator for Unstructured Grid Computation in Computational Fluid Dynamics

Takayuki Akamine

FPL2012 (Oslo, Norway) , 

2012.09

, 

Oral presentation (general)

Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array

Toru Katagiri

WReCS 2012 (Merborne, Austoralia) , 

2012.09

, 

Oral presentation (general)

CMA-CUBE: A SCALABLE RECONFIGURABLE ACCELERATOR WITH 3-D WIRELESS INDUCTIVE COUPLING INTERCONNECT

KOIZUMI YUSUKE

FPL2012 (Oslo, Norway) , 

2012.09

, 

Poster presentation

The multi-GPU System with ExpEther

NOMURA SHINPEI

PDPTA (LasVegas, USA) , 

2012.07

, 

Oral presentation (general)

A Case for Random Shortcut Topologies for HPC Interconnects

#HMichihiro Koibuchi/U>

International Symposium on Computer Architecture (Portland, USA) , 

2012.05

, 

Oral presentation (general), IEEE/ACM

Trade-off analysis of Fine-grained Power Gating Methods for Functional Units in a CPU

Weihan Wang

CoolChips XV (Yokohama, Japan) , 

2012.04

, 

Oral presentation (general), IEEE

Cost effective implementation of flux limiter functions using partial reconfiguration

Mohamad Sofian Abu Talip

ARC 2012 (International Symposium on Applied Reconfigurable Computing) (HongKong, China) , 

2012.03

, 

Oral presentation (general)

Vertical link on/off control methods for wireless 3-D NoCs

Zhang Hao

ARCS2012 (International Synmposium on Architecture of Computing Systems) (Prague, Czech) , 

2012.02

, 

Oral presentation (general)

CMA-2 : The second prototype of a low power reconfigurable accelerator

IZAWA MAI

ASP-DAC2012 (Sydney, Australia) , 

2012.01

, 

Poster presentation, IEEE

Cool Mega-Array: a highly energy efficient reconfigurable accelerator

M.Ozaki} and H.Amano, and et.al.

ICFPT2011 (Deli, India) , 

2011.12

, 

Oral presentation (general), IEEE

Reducing Power for Dynamically Reconfigurable Processor Array by Reducing Number of Reconfigurations

M.Kimura} and {K.Hironaka} and {H.Amano

ICFTP 2011 (Deli, India) , 

2011.12

, 

Oral presentation (general), IEEE

Vegeta: An Implementation and Evaluation of Development-support Middleware on Multiple OpenCL Platform

{A.Shitara} and {T.Nakahama} and {M.Yamada} and {T.Kamata} and {Y.Nishikawa} and {M.Yoshimi} and {H.Amano}

ICNC2011 (Osaka, Japan) , 

2011.11

, 

Oral presentation (general), IEICE

Power-aware Multi-tree Ethernet for HPC Interconnects

{M.Koibuchi} and {T.Watanabe} and {A.Minamihata} and {M.Nakao} and {T.Hiroyasu} and {H.Matsutani} and {H.Amano

ICNC 2011 (Osaka, Japan) , 

2011.11

, 

Oral presentation (general)

Time and Space-Multiplexed Compilation Challenge for Dynamically Reconfigurable Processors

T.Toi} and {T.Awashima} and {M.Motomura} and {H.Amano

IEEE MWSCAS 2011 (Seoul, Korea) , 

2011.08

, 

Oral presentation (invited, special)

Implementation and Evaluation of Program Development Middleware for Cell Broadband Engine Clusters

T.Kamata} and {M.Yamada} and {A.Shitara} and {Y.Nisikawa} and {M.Yoshimi} and {H.Amano

PDPTA 2011 (LasVegas, USA.) , 

2011.07

, 

Oral presentation (general), IASTED

High Speed CRC with 64-bit generator polynomial on an FPGA'

{A.Amila} and {H.Amano}

HEARTS 2011 (London, UK.) , 

2011.06

, 

Oral presentation (general)

An Implementation of Out-Of-Order Execution System for Acceleration of Computational Fluid Dynamics on FPGAs'

{H.Matsutani} and {Y.Take} and {D.Sasaki} and {M.Kimura} and {Y.Ono} and {Y.Nishiyama} and {M.Koibuchi} and {T.Kuroda} and {H.Amano}

HEARTS 2011 (London, UK) , 

2011.06

, 

Oral presentation (general), IEICE

A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs

{H.Matsutani} and {Y.Take} and {D.Sasaki} and {M.Kimura} and {Y.Ono} and {Y.Nishiyama} and {M.Koibuchi} and {T.Kuroda} and {H.Amano}

NoCS 2011 (Pittsburgh, Pennsylvania, USA) , 

2011.05

, 

Oral presentation (general), IEEE

Execution of a Computational Fluid Dynamics Application on FLOPS-2D, a multi-FPGA platform

{H.Amano} and {H.Morisita} and {K.Inakagata} and {Y.Osana} and {N.Fujita}

DATE Workshop Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing (Grenoble, France) , 

2011.03

, 

Oral presentation (invited, special)

Dynamic Vdd Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction

T.Yamamoto} and {K.Hironaka} and {M.Kimura} and {K.Usami}

Proc. of International Conference on Advanced Reconfigurable Computing Systems 2012 (England) , 

2011.03

, 

Oral presentation (general), IEEE

Reducing power consumption for Dynamically Reconfigurable Processor Array with partially fixed configuration mapping

Kazue Hironaka

International Conference on Field Programmable Technologies (Beijin, CHINA) , 

2010.12

, 

Poster presentation, IEEE

A Variable-pipeline On-chip Router Optimized to Traffic Pattern

Yuto Hirata

International Workshop on Network on Chip Architectures(NoCArc'10) (Atlanta, USA) , 

2010.12

, 

Oral presentation (general)

Wire Congestion Aware Synthesis for a Dynamically Reconfigurable Processor

Takao Toi

International Conference on Field Programmable Techology (Beijin, CHINA) , 

2010.12

, 

Poster presentation, IEEE

Recent Trends of Dynamically Reconfigurable Processors

AMANO HIDEHARU

Asia-Pacific Radio Science Conference (Toyama, JAPAN) , 

2010.09

, 

Oral presentation (invited, special)

A Proposal of Thread Virtualization Environment for Cell Broadband Engine

Masahiro Yamada

International Conference on Parallel and Distributed Systems (Marina del Ray, USA) , 

2010.08

, 

Oral presentation (general)

A Deadlock-free Non-minimal Fully Adaptive Routing Using Virtual Cut-through Switching

Y. Nishikawa} and {M.Koibuchi} and {H.Matsutani} and {H.Amano}

International Conference on Networking, Architecture and Strage (NAS) (Macau, CHINA) , 

2010.06

, 

Oral presentation (general), IEEE

Implementation and Evaluation of an Arithmetic Pipeline on FLOPS-2D:Multi-FPGA System

H. Morisita} and {K. Inakagata} and {Y.Osana} and {N.Fujita} and {H.Amano}

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (Tsukuba, JAPAN) , 

2010.06

, 

Oral presentation (general)

Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs

{H. Matsutani} and {M.Koibuchi} and {D.Ikebuchi} and {K.Usami} and {H.Nakamura} and {H. Amano}

NoCS 2010 (Grenoble, FRANCE) , 

2010.05

, 

Oral presentation (general), IEEE

Geyser-1 and Geyser-2: MIPS R3000 CPU Chips with Fine-grain Runtime Power Gating

{L. Zhao} and {D. Ikebichi} and {Y.Saito} and {M.Kamata} and {N.Seki} and {Y.Kojima} and {H.Amano} and {S.Koyama} and {T.Hashida} and {Y.Umahashi} and {D.Masuda} and {K.Usami} and {T.Sunata} and {K.Kimura} and {M.Namiki} and {S.Takeda} and {H.Nakamura} and {M.Kondo}

IEEE CoolChips XIII (Yokohama, JAPAN) , 

2010.04

, 

Oral presentation (general)

A Performance Evaluation of CUBE: One-dimensional 512 FPGA Cluseter

M. Yoshimi} and {Y. Mishikawa} and {M.Miki} and {Y.Hiroyasu} and {H.Amano} and {O.Mencer}

International Symposium on Advanced Reconfigurable Computing (Bangkok, Thailand) , 

2010.03

, 

Oral presentation (general)

Low Power Image Processing using MuCCRA-3: A Dynamically Reconfigurable Processor Array

Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda and AMANO HIDEHARU

International Conference on Field Programmable Technology(ICFPT09) (Sydny, Australia) , 

2009.12

, 

Other, IEEE

A Study on Interconnection Networks of the Dynamically Reconfigurable Processor MuCCRA

Masaru Kato, Toru Sano, Yoshiki Saito AMANO HIDEHARU

International Conference on Field Programmable Technology (ICFPT) (Sydny, Australia) , 

2009.12

, 

Poster presentation

Leakage Power Reduction for Coarse-Grained Dynamically Reconfigurable Processor Arrays Using Dual VT Cells

Kei'ichiro Hirai, Masaru Kato, Yoshiki Saito and AMANO HIDEHARU

International Conference on Field Programmable Technology (ICFPT09) (Sydny, Australia) , 

2009.12

, 

Oral presentation (general)

MuCCRA-Cube: a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link

Shotaro Saito and Yoshinori Kohama and Yasufumi Sugimori and Yohei Hasegawa and Hiroki Matsutani and Toru Sano and Kazutaka Kasuga and Yoichi Yoshida and Kiichi Niitsu and Noriyuki Miura and Tadahiro Kuroda and HIDEHARU AMANO

International Conference on Field Programmable Logic and Applications (FPL'09) (Prague, Poland) , 

2009.08

, 

Oral presentation (general)

Performance Analysis of ClearSpeed's CSX600 Interconnects

Yuri Nishikawa and Michihiro Koibuchi and Masato Yoshimi and Akihiro Shitara and Kenichi Miura and AMANO HIDEHARU

International Symposium on Parallel and Distributed Processing with Applications (Chendju, China) , 

2009.08

, 

Oral presentation (general)

Modularizing Flux Limiter Functions for a Computational Fluid Dynamics Accelerator on FPGAs

Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, AMANO HIDEHARU

International Conference on Field Programmable Logic and Applications (FPL09) (Prague, Poland) , 

2009.08

, 

Poster presentation

Japanese Dynamically Reconfigurable Processors

AMANO HIDEHARU

Engineering of Reconfigurable Systems and Algorithms (ERSA09) (Las Vegus) , 

2009.07

, 

Oral presentation (invited, special)

A Real Chip Evaluation of MuCCRA-3: A Low Power Dynamically Reconfigurable Processor Array

Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tanbunheng, Yoshihiro Yasuda and AMANO HIDEHARU

Engineering of Reconfigurable Systems and Algorithms (Las Vegus, U.S.A.) , 

2009.07

, 

Poster presentation, IEEE

Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors

Toru Sano, Yoshiki Saito and AMANO HIDEHARU

Engineering of Reconfigurable Systems and Algorithms (ERSA09) (Las Vegus, U.S.A.) , 

2009.07

, 

Oral presentation (general)

Evaluation of a Multi-core Reconfigurable Architecture with Variable Core Size

YVu Mah Tuan and AMANO HIDEHARU

Reconfigurable Architecture Workshop (RAW'09) (Roma, Itary) , 

2009.05

, 

Oral presentation (general), IEEE

RHiNET-3/SW an 80-Gbit/s high-speed network switch for distributed parallel computing

S.Nishimura, T.Kudoh, H.Nishi, J.Yamamoto, R>Ueno, K.Harasawa, S.Fukuda, Y.Shikichi, S.Akutsu, K.Tasho, H.Amano

Hot Interconnect 9, 

2001.08

, 

Oral presentation (general)

　View Summary

RHiNET-3スイッチの設計と実装

MMLRU selection Function: An output selection function on Adaptive Routing

M.Koibuchi, A.Funahashi, A.Jouraku, H.Amano,

ISCA International Conference on Parallel and Distributed Computing Systems., 

2001.08

, 

Oral presentation (general)

　View Summary

パケット経路の動的選択法と提案と評価

General purpose Monitoring System POT for parallel computers

Y.Kanamori, M.Shimada, H.Amano

International Conference on Parallel and Distributed Processing Techniques and Applications, 

2001.06

　View Summary

汎用並列計算機モニタシステムPOTの設計と実装を行う

Performance evaluation of a multicast mechanism for a massively parallel machine JUMP-1

N.Suzuki, H.Amano, T.Tamura, Y.Osana, K.Nishimura,

International Conference on Parallel and Distributed Processing Techniques and Applications, 

2001.06

　View Summary

JUMP-1の転送機構の実機評価を行う

Multistage Interconnection Network Recursive Clos II (R-ClosII): a scalable Hierarchical network for a compiler directed multiprocessor ASCA

T.Morimura, K.Tanaka, K.Iwai, H.Amano,

International Conference on Parallel and Distributed Processing Techniques and Applications, 

2001.06

　View Summary

スケジュール可能な結合網R-Clos　IIの提案と評価

Performance evaluation of Parallel I/O Mechanism on a Massively Parallel Processing System JUMP-1

Y.Osana, H.Nakajo, N.Suzuki, T.Tamura, H.Amano

International Conference on Parallel and Distributed Processing Techniques and Applications, 

2001.06

　View Summary

JUMP-1のI/O機構の実機評価を行う

General purpose Monitoring System POT for parallel computers

Y.Kanamori, M.Shimada, H.Amano

International Conference on Parallel and Distributed Processing Techniques and Applications, 

2001.06

　View Summary

汎用並列計算機モニタシステムPOTの設計と実装を行う

Performance evaluation of a multicast mechanism for a massively parallel machine JUMP-1

N.Suzuki, H.Amano, T.Tamura, Y.Osana, K.Nishimura,

International Conference on Parallel and Distributed Processing Techniques and Applications, 

2001.06

　View Summary

JUMP-1の転送機構の実機評価を行う

Multistage Interconnection Network Recursive Clos II (R-ClosII): a scalable Hierarchical network for a compiler directed multiprocessor ASCA

T.Morimura, K.Tanaka, K.Iwai, H.Amano,

International Conference on Parallel and Distributed Processing Techniques and Applications, 

2001.06

　View Summary

スケジュール可能な結合網R-Clos　IIの提案と評価

Performance evaluation of Parallel I/O Mechanism on a Massively Parallel Processing System JUMP-1

Y.Osana, H.Nakajo, N.Suzuki, T.Tamura, H.Amano

International Conference on Parallel and Distributed Processing Techniques and Applications, 

2001.06

　View Summary

JUMP-1のI/O機構の実機評価を行う

The Impact of Output selection function on Adaptive routing

A.? Funahashi, M.Koibuchi, A.Jouraku, H.Amano

International Conference on Computers and their applications, 

2001.05

　View Summary

パケット経路の動的選択法と提案と評価

ASCA Chip Set: A multiprocessor architecture for multi-grain parallel processing

T.Abe, T.Morimura, T.Suzuki, K.Tanaka, M.Koibuchi, R.Ogawa, H.Amano,

COOL Chips IV, 

2001.04

　View Summary

スケジュール指向マルチプロセッサASCA用のチップセット

ASCA Chip Set: A multiprocessor architecture for multi-grain parallel processing

T.Abe, T.Morimura, T.Suzuki, K.Tanaka, M.Koibuchi, R.Ogawa, H.Amano,

COOL Chips IV, 

2001.04

　View Summary

スケジュール指向マルチプロセッサASCA用のチップセット

Flow control method in high speed transfer using Optical Interconnect

R.Ueno, S.Inasawa, H.Nsihi, T.Kudoh, H.Amano

IASTED International conference Applied Informatics, 

2001.01

　View Summary

RHiNET-3/SWのノード間の信頼性を保証するフローコントロール方式の評価

Flow control method in high speed transfer using Optical Interconnect

R.Ueno, S.Inasawa, H.Nsihi, T.Kudoh, H.Amano

IASTED International conference Applied Informatics, 

2001.01

　View Summary

RHiNET-3/SWのノード間の信頼性を保証するフローコントロール方式の評価

Floating　Point　Arithmetic　Unit　for　The　Custom　Processor　MAPLE

IASTED　Applied　Informatics, 

1999

　View Summary

スケジュール指向計算機MAPLEの浮動小数点演算ユニットの設計と実装。

ISIS：Multiprocessor　Simulator　Library

IASTED　Applied　Informatics, 

1999

　View Summary

シミュレーション用ライブラリISISの実装について示す。

Pruning　Cache：A　Dynamic　Directory　Generation　Scheme　For　Distributed　Shared　Memory

IASTED　International　Conference　on　Parallel　and　Distributed　Computing　and　Networks, 

1999

　View Summary

分散共有メモリのディレクトリを動的に構成する方法を提案、評価する。

The　Preliminary　Evaluation　of　MBP-light　with　Two　Protocol　Policies　for　a　Massively　Parallel　Processor　JUMP=1

IEEE　Frontiers　1999　, 

1999

　View Summary

超並列計算機の分散共有メモリ制御用プロセッサの予備評価を行う。

Emulation of Multichip WASMII on Reconfigurable System Testbed FLEMING

H. Miyazaki, Y. Shibata, A. Yakayama, X．Ling, H. Amano

Proc. of the PACT’98 Workshop, 

1998.10

　View Summary

WASMIIエミュレータを用いた評価。

MBP-light: A Processor for Management of Distributed Shared Memory

I. Inoue, K. Anjo, J. Tanabe, K. Nishimura, M. Satoh, K. Hiraki, H. Amano

Proc. of IEEE 3rd International Conference on ASIC, 

1998.10

　View Summary

分散共有メモリ制御用のプロセッサアーキテクチャを提案。

Multistage Interconnection Network R-Clos: Emulating the hierarchical multi-bus

T. Morimura, K. Iwai, H. Amano

Proc. of the International Conference on Parallel and Distributed Computing systems, 

1998.09

　View Summary

再帰構造を持つClos網を提案する。

Home Proxy Cache for High Performance DSM on a Workstation cluster

W. Ono, H. Nakajo, A. Ichikawa, K. Anjo, H. Amano, T. Kudoh

Proc. of the International Conference on Parallel and Distributed Computing systems, 

1998.07

　View Summary

PCクラスタネットワーク上での新しいキャッシュの構成法を提案する。

HOSMII: A Virtual Hardware Intergrated with DRAM

Y. Shibata, H. Miyazaki, X. Ling, H. Amano

Proc. of the IPPS/SPDP’98 Workshops,LNCS 1388, 

1998.04

　View Summary

DRAMに基づく仮想ハードウェアシステムを提案する。

An Interconnection Netowrk of ASCA:A multiprocessor for multi-grain parallel processing

Internatinal symposium on Applied Informatics, 

1998.03

　View Summary

ASCA用の結合ネットワークでのスケジュール可能な交信を評価する。

A custom processor for the multiprocessor system ASCA

Internatinal symposium on Applied Informatics, 

1998.03

　View Summary

スケジュール指向のマルチプロセッサ用のカスタムプロセッサアーキテクチャ。

Reconfigurable Systems:A survey

Asia and South Pacific Design Automation Conference 1998, 

1998.01

　View Summary

アジアでの再構成可能なシステムのサーベイ。

The MINC chip

Asia and South Pacific Design Automation Conference 1998, 

1998.01

　View Summary

キャッシュ制御機構付きのMINの実装。

Wavelength division multiple access ring-virtual topology on a simple ring network

3rd IEEE International Symp.on Parallel Architecture，Algorithms，and Networks, 

1997.12

　View Summary

光波長多重ネットワーク用のリング状ネットワークの提案。

Adaptive Routing on the Recursive Diagonal Torus

International Shimposium on High Performance Computing, 

1997.11

　View Summary

RDT上での適応型ルーチング法の提案。

Memory based light weight couumincation architecture for local area distibuted computing

International Workshop on Inovative Architecture, 

1997.10

　View Summary

メモリベース通信に基づくPCクラスタシステム。

A reconfigurable markov chain simulator for analysis of parallel systems

IEEE International Conference on Innovetive Systems in Silicon, 

1997.10

　View Summary

並列システム解析用の可変構造マルコフチェーンシミュレータの開発

nD-MIN:Multistage Interconnection Network with multiple dimeusional structure

ISCA 10th International Conference on Parallel and Distributed Computing Systems, 

1997.10

　View Summary

多次元化してループ構造を持たせることで交信局所性を利用できるMINの提案。

Toward the Realistic ”Virtual Hardware”

International Workshop on Inovative Architecture, 

1997.10

　View Summary

DRAM内臓方式による仮想ハードウェアの提案。

A reconfigurable sensor-data processing system for perfonal robots

Field-Programmable Logic'97, 

1997.09

　View Summary

パーソナルロボット用の再構成可能なセンサデータ処理システム。

Shared vs.Snoop:Evaluation of Cache Structure for Single Chip Multiprocessors

Euro-Par'97, 

1997.08

　View Summary

オンチップマルチプロセッサ用のキャッシュをスヌープと共有方式で比較する。

An Emulation System of the WASMⅡ:A Data driven computer on a Virtual Hardware

Y.Shibuta，X.Ling，H.Amano

Field-Programmable Logic'96, 

1996.09

　View Summary

WASMIIのエミュレータを実装する。

ATTEMPT-1:A Reconfigurable Multiprocessor Testbed

K.Inoue，T.Kisuki，M.Okuno，E.Shimizu，T.Terasawa，H.Amamo

Fieldf-Programmable Logic'96, 

1996.09

　View Summary

変構造型のマルチプロセッサテストベットATTEMPT-1を実装する。

The JUMP-1 Router chip:A Veratile router for Supporting a Distributed Shared Memory

H.Nishi， K.Nishimura， K.Anjo， H.Amano， T.Kudoh

IEEE 15th Annual Phoenix Conference on Computers and Communications, 

1996.03

　View Summary

マルチキャストを効率的に行うRDT用ルータチップの実装。

Fault Torelant MIN with Multiple Outlets

A.Funahashi， T.hanawa， H.Amano

IEEE Pacific Rim International Symposium on Fault Tolerant Systems, 

1995.12

　View Summary

多重出力可能なMINに耐故障性を与える。

A Preprocessing system of the EULASH:An Environment for Efficient use of Multiprocessors with Local Memory

J.Yamanoto， D.Hattori， T.Tokuyoshi， Y.Yamaguchi， H.Amano

7th IASTED/ISMM International Conference on Parallel and Distributed computing and systems, 

1995.10

　View Summary

ローカルメモリを有効に活用する環境Eulash用プリプロセッサを実装。

MINC: Multistage Interconnection Network with Cache Control Mechanism

T.Hanawa，H.Yasukawa，K.Nishimura，H.Amano

ISCA/IEEE 9th International Conference on Parallel and Distributed Computing Systems, 

1995.09

　View Summary

キャッシュ制御付きMINの提案と評価。

Structure and Performance of the MDX:A Network Class for Large Scale Multiprocessors

A.Murata，T.Boku，T.Harada，H.Amano

ISCA/IEEE 9th International Conference on Parallel and Distributed Computing Systems, 

1995.09

　View Summary

新しい不等距離間接網のクラスを定義する。

Hierarchical bit-map directory schemes on the RDT interconnection network for a massively parallel processor JUMP-1

T.Kudoh，H.Amano，T.Matsumoto，K.Hiraki，Y.Yang

International Conference on Parallel Processing, 

1995.08

　View Summary

RDT上での階層bit-map directory手法を提案する。

An LSI implementation of the Simple Serial Synchronized Multistage Interconnection Network

T.Kamei，M.Sasahara，H.Amano

Synthesis and System Integration of Mixed Technologies, 

1995.08

　View Summary

SSS型PBSFチップのLSI化

A Cache Coherency Protocol for Multiprocessor Chip

T.Terasawa，H.Amano

International Conference on Wafer Scale Integration, 

1995.01

　View Summary

オンチップマルチプロセッサ用キャッシュ一致プロトコルの提案。

Overview of the JUMP-1，an MPP Prototype for General Purpose Parallel Computations

K.Hiraki，H.Amano，M.Kuga，T.Sueyoshi，T.Kudoh，H.Nakashima，H.Nakajo，H.Matsuda，T.Matsumoto.S.Mori

International Symposium on Parallel Architecture，Algorithms and Networks, 

1994.12

　View Summary

超並列計算機JUMP-1の提案

Message Transfer Algorithms on the Recursive Diagonal Torus

Y.Yang，H.Amano

International Symposium on Parallel Architecture，Algorithms and Networks, 

1994.12

　View Summary

RDT上でのマルチキャストやデッドロックフリールーチング法の提案。

Matrix Calculations on a multiprocessor based on the SSS-multistage interconnection network

PCG '94 Parallel Computation for Matrix Calculations, 

1994.03

　View Summary

SSS型MINに基づくマルチプロセッサでの行列計算手法の評価。

Recursive Diagonal Torus: An Interconneciton Network for Massively Parallel Processing

Yang，Y.，Amano，H.，Shibamura，H.and Sueyoshi，T.

IEEE 5th IEEE Symposium on Prallel and Distributed Processing, 

1993.12

　View Summary

再帰的なトーラス構造を持つ結合網の提案。

The Colored STMT net: An analysis model for Parallel Systems

Takemoto，T.，Kimura，T.，Yamamoto，O.and Amano，H.

6th ISCA Int.Conf.on Parallel and Distributed Computing Systems, 

1993.10

　View Summary

解析モデルSTMTnetを拡張する。

Performance evaluation of WASMII:a data driven computer on a virtual hardware

X.P.Ling and H.Amano

PARLE93，（Lectual notes incomputer science）, 

1993.06

　View Summary

仮想ハードウェアWASMIIの性能評価。

A Performance analysis for the arbitor of IEEE standard backplane bus Futurebus/Futurebus+

O.Yamamoto，T.Takemoto，T.Kimura and H.Amano

IEEE Pacific Rim Conference, 

1993.05

　View Summary

IEEE Futurebusのバスアービタの解析。

WASMII:a Data Driven Computer on a Virtual Hardware

X.P.Ling and H.Amano

IEEE Int.Workshop on FPGA and Custom Computing Machines, 

1993.05

　View Summary

データ駆動型に基づく仮想ハードウェアの提案。

Neural Network Parallel Computing for Channel ROuting Problems

天野英晴，武藤佳恭，その他

Int.Conf.Automation Robotics and Computer Vision, 

1992.09

　View Summary

ニューラルネットワークによるLSIチャネルルーチングの並列処理。

SSS-MIN:a novel multi stage interconnection architecture for multiprocessors

天野英晴，その他

IFIP 12th World Computer Congress, 

1992.09

　View Summary

単純で高速な多段結合網の提案。

A Parallel Logic Simulation Algorithm based on Query

天野英晴，その他

International Conference on Parallel Processing, 

1992.08

　View Summary

問い合わせに基づく保守的時刻管理で効率のよい並列論理シミュレーションを行う。

The STMT net:An analysis Model for parallel systems

天野英晴，その他

Summer Computer Simulation Conference, 

1992.07

　View Summary

マルコフチェーンに基づく解析モデルの提案。

An extended fault tolerant Batcher network

天野英晴，その他

IEEE workshop on fault tolerant parallel and distributed systems, 

1992.07

　View Summary

耐故障性のあるバッチャ網を拡張した。

An extended Fault Tolerant Batcher network

天野英晴，その他

ISMM workshop on parallel processing，Sept.1991, 

1991.09

　View Summary

耐故障性を持った結合網の提案

An implementation of the BDOC

天野英晴，その他

ISMM workshop on parallel processing，Sept.1991, 

1991.09

　View Summary

BDOC網の実装

A Batcher Double Omega network with combining

天野英晴，その他

International Conference on Parallel Processing，Aug.1991, 

1991.08

　View Summary

並列計算機用交換網の提案

A 0.8μm BiCMOS SEA-OF-GATEs Inplementation of the Tandem Banyan fast packet switch

天野英晴，その他

IEEE CICC '91, 

1991.05

　View Summary

高速パケット交換用チップの実装

A Fault Tolerant Batcher Network

Proc.of ICPP 1990, 

1990.08

　View Summary

Batcher網の故障回避法を提案する。

A Concurrent Program Restracturing System for scientific Calculations

木村哲郎

HICSS 91 Hawaii International Conference on system sciences 1991, 

1990.01

　View Summary

科学技術計算システム用並行記述言語再構成システム。

Cache with Synchronization Mechanism

天野英晴 その他

IFIP 11th World Computer Congress, 

1989.08

　View Summary

マルチプロセッサにおけるキャッシュメモリと同期機構の統一設計の提案。

A New version of parallel production system machine MANJI-Ⅱ

天野英晴，相磯秀夫 その他

IWDM'89 International Workshop on Database Machines, 

1989.08

　View Summary

プロダクションシステム専用並列計算機MANJI-Ⅱの提案。

A Fault Diagnosis Method for a Batcher Network

天野英晴 その他

JTC-CSCC'89（Joint Techinical Conference on Circuits/Systems，Computers and Communications）, 

1989.07

　View Summary

バッチャ網のための故障診断法の提案。

A Static Scheduling Ststem for a Parallel Machine（SM）2-Ⅱ

天野英晴 その他

PARLE'89（Parallel Architectures and Languages Europe）, 

1989.07

　View Summary

科学技術計算の並列処理のためのプロセススケジューリング手法の提案。

Impulse:A High Performance Processing Unit for Scientific Calculation

T.Boku，S.Nomura，H.Amano

The 15th ISCA, 

1988.06

　View Summary

プロセススイッチを高速に行う並列計算機用のプロセッサアーキテクチャを提案する。

マルチプロセッサ型スーパコンピュータ

電子情報通信学会学会誌, 

1987.12

　View Summary

マルチプロセッサ型のスーパコンピュータについてサーベイし報告する。

The Shared Memory structure of MANJI

J.Miyazaki，H.Amano，K.Takeda，H.Aiso

The 2nd IWDM, 

1987.10

　View Summary

プロダクションシステム専用マシンMANJIのメモリ機構を述べる。

The Compatible Acknowledging Ethernet

電子通信学会英文誌, 

1987.10

　View Summary

ローカル・コンピュータネットワークの代表であるEthernetに即時応答を組み込んだAcknowledging Ethernetに改良を加える。

Rolling Mapping:A mapping method for machines with nearest neighbor mesh structure

G.Osawa，A.Murata，H.Amano，H.Aiso

The 2nd SCS, 

1987.07

　View Summary

格子状並列計算機状に有限要素法等の不規則メッシュを効果的に割り付けるマッピング法を提案する。

RSM:A Special communication method for multiprocessors

H.Amano

The 2nd C&A, 

1987.06

　View Summary

プロセッサ間結合機構RSMは同一データを複数のプロセッサに同時に転送可能である。

MANJI:A parallel machine for production system

J.Miyazaki，H.Amano，H.Aiso

HICSS20, 

1987.01

　View Summary

プロダクションシステム専用マシンMANJIはOPS-5を高速に実行するアーキテクチャを持つ。

DIPROS:A distributed processing system for NDL on （SM）2-Ⅱ

T.Boku，T.Kudoh，H.Amano，H.Aiso

HICSS20, 

1987.01

　View Summary

（SM）2-Ⅱにおいて並行プロセス言語を実装する際のプロセスコントローラを実装評価する。

An Adaptable Cluster structure for （SM）2-Ⅱ

C.Saito，H.Amano，T.Kudoh，H.Aiso

CONPAR86, 

1986.09

　View Summary

（SM）2-Ⅱのクラスタ構成を問題に適合するように変化させる方法を提案する。

A VLSI Switch for a Digital PBX

電子通信学会英文誌, 

1986.07

　View Summary

簡単なPBXのためのVLSIチップを提案する。このチップはマルチプレクサ，スイッチ，デマルチプレクサを兼ね，VLSIの実装に適している。

NDL:A language for solving scientific problem on MIMD machines

T.Kudoh，H.Amano，T.Boku，H.Aiso

The 1st SCS, 

1985.12

　View Summary

科学技術用の並列計算機のための並行プロセス記述言語NDLを提案する。

（SM）2-Ⅱ:The new version of the Sparse Matrix Solving Machine

H.Amano，T.Boku，T.Kudoh，H.Aiso

The 12th ISCA, 

1985.06

　View Summary

既に提案した一般疎行列専用並列計算機のプロセッサ間結合法を改良する。

HOBONET:An Inter-PU Connection Network with fault tolrerancy

G.Osawa，T.Yokota，H.Amano，H.Aiso

ICPP, 

1984.08

　View Summary

1つのプロセッサが故障しても正方格子を維持できる結合法を提案する。

（SM）2:The Spase Matrix Solving Machine

H.Amano，T.Yoshida，H.Aiso

The 10th ISCA, 

1983.06

　View Summary

疎行列計算に適した並列計算機のメモリ構成を提案する。