研究者詳細 - 山崎　信行

論文 - 山崎　信行

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Real-Time Execution based on Fluid Scheduling by using IPC Control Scheme

Santo A., Yamasaki N.

Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 （Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021） 459 - 463 2021年

研究論文（国際会議プロシーディングス）, 査読有り

Fluid scheduling is an optimal real-time scheduling applicable to multiprocessor systems and is a scheduling model so that every real-time task is executed at a constant speed from release time to deadline. It is necessary for fluid scheduling to control the execution speed of each task. But, since the execution speed of the task is invariable in a conventional general purpose processor. Therefore, fluid scheduling is conventionally achieved by repeatedly executing and stopping tasks. However, this method incurs significant overheads due to frequent task switching. On the other hand, fluid scheduling without overhead by using an IPC control scheme has been proposed. The IPC control scheme controls the execution speed of each thread in an SMT processor. We propose a new IPC control scheme to extract thread-level parallelism and improve throughput effectively, also improving the schedulability of the fluid schedule. The evaluation results show that the proposed method improved the total throughput of the fluid schedule.

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Data Rearrange Unit for Efficient Data Computation in Embedded Systems

Mamiya A., Yamasaki N.

研究論文（国際会議プロシーディングス）, 査読有り

Recently demands for computation intensive applications such as convolutional neural networks (CNNs) have been increasing. In these applications, valid data for computation are allocated in non-continuous addresses. Therefore, common burst memory access pattern results in a low spatial locality of valid data per access. As a result, computation of data parallel execution units degrades in throughput, as computation resource is wasted by computing invalid data. This is especially a problem in embedded systems in which constraints in power consumption provoke a requirement for high computation efficiency. In this paper, we introduce a Data Rearrange Unit (DRU), a hardware unit rearranging computation data to increase spatial locality of valid data. The DRU drastically reduces the main memory access rate and increases computation efficiency by decreasing memory access to reduce power consumption. We demonstrate the effectiveness of our DRU by implementation on the RMTP SoC [1] [2] improving convolution throughput on a data parallel execution unit by a maximum of 94times, while only increasing the total cell area by about 13%.

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A Learning-based Fetch Thread Gating Mechanism for A Simultaneous Multithreading Processor

Ide Y., Yamasaki N.

Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020 （Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020） 19 - 28 2020年11月

研究論文（国際会議プロシーディングス）, 査読有り

Simultaneous Multithreading (SMT) technology is widely adopted in modern high-end processors to maximize on-chip hardware utilization. In an SMT processor, multiple threads are executed in parallel, sharing hardware resources. This technique aggregates potential efficiency which will not be available in a single thread processor. However, when a data cache miss or a branch prediction miss occurs, every thread competing for hardware resources causes the degradation of hardware utilization. Therefore, instruction fetch policies have been proposed to manage hardware resources efficiently in SMT processors. The fetch policies distribute hardware resources indirectly, through fetch bandwidth control. Conventionally, a fetch policy selects fetch threads based only on the resource usage at the moment, while the characteristics of threads are not exploited on decision. Therefore most conventional fetch control schemes only take effects only after an outstanding event occurs. Capability of resource restriction is limited even with an aggressive fetch control scheme. In this paper, we propose a Fetch Gate Estimator (FGE) that is a fetch gating mechanism based on machine learning, which is implemented as a hardware module. The FGE evaluates each thread to decide whether an instruction fetch from a thread should be gated. The FGE is trained dynamically by the execution statistics resulted from the inferences, so that characteristics of each thread are encoded into a learning model. Thus, the FGE is trained dynamically in parallel with execution of programs. We applied a single layer perceptron as learning model inside the FGE for circuit simplicity, and investigated performance impacts. Evaluation results show that the perceptron-based FGE can train itself from acquired execution statistics to identify inefficient threads adaptively, adjusting resources through the fetch gate control mechanism.

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Codeword set selection for the error-correcting 4b/10b line code with maximum clique enumeration

Takeda M., Yamasaki N.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences （IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences） E103A （ 10 ） 1227 - 1233 2020年10月

研究論文（学術雑誌）, 査読有り, ISSN 09168508

This paper addresses the problem of finding, evaluating, and selecting the best set of codewords for the 4b/10b line code, a dependable line code with forward error correction (FEC) designed for real-time communication. Based on the results of our scheme [1], we formulate codeword search as an instance of the maximum clique problem, and enumerate all candidate codeword sets via maximum clique enumeration as proposed by Eblen et al. [2]. We then measure each set in terms of resistance to bit errors caused by noise and present a canonical set of codewords for the 4b/10b line code. Additionally, we show that maximum clique enumeration is #P-hard.

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Space Responsive Multithreaded Processor (SRMTP) for Spacecraft Control

Nakabeppu S., Ide Y., Takahashi M., Tsukahara Y., Suzuki H., Shishido H., Yamasaki N.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings （IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings） 2020年04月

研究論文（国際会議プロシーディングス）, 査読有り

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Implementation of fluid scheduling using IPC control mechanism

Tsukahara Y., Nobuyuki Y.

Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS （Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS） 2019-December 402 - 405 2019年12月

研究論文（国際会議プロシーディングス）, 査読有り, ISSN 15219097

In real-Time systems such as automobiles, correctness of processing tasks depends not only on its result, but also on time. Real-Time scheduling is a basic approache to achieve real-Time execution in real-Time systems. Fluid scheduling is an optimal real-Time scheduling model, which keeps the execution speed of each task proportional to its processor utilization. However, the speed of a task cannot be controlled arbitrarily on a general processor, making it impossible to implement fluid scheduling directly. Therefore, there have been many studies on pseudo fluid scheduling where the algorithm is based on repeat task execution which speed is constant in an interval. We apply the special mechanisms of Responsive MultiThreaded Processor (RMTP) to the novel control mechanism in order to implement fluid scheduling directly. RMTP is a prioritized SMT processor for real-Time processing, which has 1. a thread speed control mechanism which controls execution speed of each thread and 2. a context cache enabling context switches in four clock cycles. In this paper, by adding a novel thread speed control mechanism, execution speeds of 40 threads are controlled to be constant over short time intervals, directly making fluid scheduling possible.

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Fast interrupt handling scheme by using interrupt wake-up mechanism

Wada R., Yamasaki N.

Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019 （Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019） 109 - 114 2019年11月

研究論文（国際会議プロシーディングス）, 査読有り

In recent years, embedded real-time systems have grown in complexity and are required to be able to handle both periodic and aperiodic tasks. When an external interrupt occurs via an I/O peripheral, the program counter jumps to the corresponding exception vector. This results in large overhead due to context switching. However, embedded real-time systems are required to execute tasks in real-time with high precision. The Responsive Multithreaded Processor (RMTP), a prioritized SMT CPU, consists of eight hardware contexts treated as eight logical processing cores and has various hardware mechanisms for fine-grained real-time processing on the order of 10 μs. One hardware mechanism implemented in RMTP is an interrupt wake-up mechanism that enables interrupt-triggered thread wake ups. When a thread is designated to be an interrupt handling thread, it starts execution one clock cycle after an interrupt occurs. In this paper, we design and implement a software mechanism which reduces the interrupt response time by using this mechanism and demonstrate the effectiveness of our proposed method by RTL simulations. Evaluation results show that our proposed method achieves high real-time performance by reducing the interrupt response time by up to 82% compared to the baseline.

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Finding the maximum number of symbols for the 4b/10b line code with error correction

Takeda M., Yamasaki N.

研究論文（国際会議プロシーディングス）, 査読有り

In this paper, we present 20 symbols for the error correcting 4b/10b line coding scheme, increasing the number of available symbols from the 18 originally proposed. The two additional symbols are used to supplement special control codes and increase compatibility with other line codes such as 8b/10b. In addition, we show that the 20 found is the maximum number of symbols possible for 4b/10b by formulating the problem as the maximum clique problem, an NP-hard problem. Finally, we show that the generalized problem of finding a set with the maximum number of symbols is NP-hard as well.

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Experimental validation of agile attitude control with sinc function-based profiler for reducing residual vibrations

Kamiya T., Shimoda K., Ozawa Y., Yokota K., Satoh T., Yamasaki N.

Proceedings of the International Astronautical Congress, IAC （Proceedings of the International Astronautical Congress, IAC） 2019-October 2019年

研究論文（国際会議プロシーディングス）, 査読有り, ISSN 00741795

This paper presents a tracking control system combining feedforward and feedback with shaped input, using a benchmark problem applied to a two-mode system. Simulations and experimental validation of the new control system for tracking control of flexible spacecraft including comparison with conventional methods are presented. The results show that the residual vibrations after the moves by the proposed control system are smaller than the conventional methods in the presence of an unknown high-order flexible mode. Sinc function-based command shaping where the spacecraft attitude is controlled along a sequentially commanded trajectory and the residual vibration after the move can be significantly reduced. Sinc function is known as an extra-insensitive function which has no frequency response above a certain threshold frequency. Three feedback controllers are applied to the control system and compared using the benchmark problem. This controller design has several unique characteristics. First, the sinc function-based shaped input is designed to reduce residual vibrations after maneuvers under the existence of unknown high-order mode. Conventional input shapers for flexible spacecraft are not effective for multi-mode system with unknown flexible modes, where actual flexible spacecraft usually has such unknown high-order flexible modes. Second, only the dynamics of the low-order mode need to be considered in designing all the feedforward, feedback controller, and shaped input. Experimental validation is performed by hardware-in-the-loop (HIL) test configuration with newly developed real-time onboard computer to evaluate the feasibility of processing load by the proposed algorithms for real-time processing. Because the proposed algorithms do not contain any iteration algorithm, the proposed algorithms can be implemented in actual satellites with feasible processing load. The assumed two-mode system represents the most simplified multi-mode system with unknown high-order mode, so the similar results can be expected for systems equipped with more complicated flexible structures.

Analysis of body bias control using overhead conditions for real time systems: A practical approach

Torres C.C.C., Okuhara H., Yamasaki N., Amano H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems） E101D （ 4 ） 1116 - 1125 2018年04月

研究論文（学術雑誌）, 査読有り, ISSN 09168532

In the past decade, real-Time systems (RTSs), which must maintain time constraints to avoid catastrophic consequences, have been widely introduced into various embedded systems and Internet of Things (IoTs). The RTSs are required to be energy efficient as they are used in embedded devices in which battery life is important. In this study, we investigated the RTS energy efficiency by analyzing the ability of body bias (BB) in providing a satisfying tradeoff between performance and energy. We propose a practical and realistic model that includes the BB energy and timing overhead in addition to idle region analysis. This study was conducted using accurate parameters extracted from a real chip using silicon on thin box (SOTB) technology. By using the BB control based on the proposed model, about 34% energy reduction was achieved.

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Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology

Cortes C., Amano H., Yamasaki N.

2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings （2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings） 2017-November 1 - 6 2018年03月

研究論文（国際会議プロシーディングス）, 査読有り

It is essential for any embedded systems and increasing popularity of Internet of Things (IoT) be energy efficient. Such systems tend to work intermittently and reducing leakage in the idle time is essential. Energy reduction techniques bring the system to a low power mode which also provokes transition overheads. If such overheads are not considered, the task may not be schedulable under a given deadline. To get a gain in energy savings, the idle state must be longer than a minimum required time. This time is referred as Break Even Time (BET). To properly design efficient algorithms and schedulers we must calculate and include the BET. In this paper, we present the first studies to examine the BET using accurate parameters extracted from a real chip using Silicon On Thin Box (SOTB) technology employing Body Bias Control (BB) energy saving technique. In this study, we demonstrate the BET range for SOTB microcontrollers, on the order of 0.5ms up to 1ms.

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RMT Processor の割り込み起床機構を用いた低遅延リアルタイム実行

大沢幸平, 溝谷圭悟, 千代浩之, 山崎信行

情報処理学会論文誌 58 （ 2 ） 531 - 543 2017年02月

Performance Evaluation of RUNT Algorithm

Hiroyuki Chishiro, Masayoshi Takasu, Rikuhei Ueda, YAMASAKI NOBUYUKI

ACM SIGBED Review 13 （ 1 ） 15 - 21 2016年01月

研究論文（学術雑誌）

An Integration of Imprecise Computation Model and Real-Time Voltage and Frequency Scaling on Responsive Multithreaded Processor

Keigo Mizotani, Yusuke Hatori, Yusuke Kumura, Masayoshi Takasu, Hiroyuki Chishiro, Yamasaki Nobuyuki

International Journal of Computers and Their Applications 22 （ 3 ） 127 - 135 2015年09月

研究論文（学術雑誌）

Zero-Jitter Semi-Fixed-Priority Scheduling with Harmonic Periodic Task Sets

Hiroyuki Chishiro, Yamasaki Nobuyuki

International Journal of Computers and Their Applications 22 （ 3 ） 118 - 126 2015年09月

研究論文（学術雑誌）

インプリサイス計算モデルにおける温度を考慮した動的電圧周波数制御の実機評価

溝谷圭悟, 上田陸平, 高須雅義, 千代浩之, 松谷宏紀, 山崎信行

情報処理学会論文誌 55 （ 8 ） 1841 - 1855 2014年08月

研究論文（学術雑誌）, 査読有り

ITRON仕様OSのRMT Processor向け実装

上田陸平, 藤井啓, 千代浩之, 松谷宏紀, 山崎信行

情報処理学会論文誌 54 （ 7 ） 1835 - 1848 2013年07月

査読有り

近年の組込みシステムの高機能化にともない，リアルタイム性に加えシステム全体の高スループット化が求められている．RMT Processorは,このような組込みシステム向けに優先度付きSimultaneous Multithreading(SMT)アーキテクチャを採用しており，ハードウェアレベルでのスレッド制御を行うための機能を有している．本論文では，ITRON仕様のリアルタイムOSを，RMT Processor向けに設計，実装した．その際，スレッドの生成やディスパッチにはRMT Processor固有のスレッド制御命令を使用し，タスクの切替え時間を短縮した．また，同時実行スレッド数を増やした際の最悪割込み応答時間を一定にするため，割込み専用スレッドを設けた．評価により，ハードウェアによるスレッド制御によってコンテキストスイッチに関係するAPIの実行時間が短縮されたこと，それにともないスケジュール成功率が向上したこと，割込み専用スレッドにより最悪割込み応答時間を一定にできていることを示した．

優先度逆転を低減させる優先度付きオンチップネットワーク向けルータアーキテクチャ

谷口将一, 山崎大輝, 笹川雄二郎, 松谷宏紀, 山崎信行

情報処理学会論文誌 54 （ 7 ） 1861 - 1872 2013年07月

優先度付きオンチップルータVIX

水頭一壽, 向後卓磨, 山崎大輝, 松谷宏紀, 山崎信行

情報処理学会論文誌コンピューティングシステム 6 （ 1 ） 87-98 2013年01月

研究論文（学術雑誌）, 共著, 査読有り

Responsive Linkを用いた分散リアルタイムシステム向け高信頼な通信機構の設計と実装

水頭一壽, 向後卓磨, 松谷宏紀, 山崎信行

情報処理学会論文誌 53 （ 12 ） 2728-2739 2012年12月

研究論文（学術雑誌）, 共著, 査読有り

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