研究者詳細 - 山崎　信行

論文 - 山崎　信行

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A Learning-based Control Scheme for Prioritized SMT Processor

Kaname Sato, Nobuyuki Yamasaki

Proceedings - 2024 Twelfth International Symposium on Computing and Networking Workshops (CANDARW) （Proceedings - 2024 Twelfth International Symposium on Computing and Networking Workshops (CANDARW)） 76 - 82 2024年11月

研究論文（国際会議プロシーディングス）, 査読有り

Context Cache for Multicore RISC-V Processor

Akira Yamazawa, Tsutomu Itou, Kazutoshi Suito and Nobuyuki Yamasaki

Proceedings - 2024 Twelfth International Symposium on Computing and Networking (CANDAR) （Proceedings - 2024 Twelfth International Symposium on Computing and Networking (CANDAR)） 272 - 278 2024年11月

研究論文（国際会議プロシーディングス）, 査読有り

A Design Scheme for Highly Efficient Mixed-Criticality Systems Using IPC Control

Kosuke Yashima, Nobuyuki Yamasaki

14th International Workshop on Networking, Computing, Systems, and Software 2024年02月

研究論文（国際会議プロシーディングス）

A Scheme Reducing Task Drops for Data Dependent Tasks on Mixed Criticality Systems

Reo Nagura, Nobuyuki Yamasaki

14th International Workshop on Networking, Computing, Systems, and Software 2024年02月

研究論文（国際会議プロシーディングス）

A Non-stop Fault-Tolerant Real-Time System-on-Chip/System-in-Package

Shota Nakabeppu, Nobuyuki Yamasaki

2023 Eleventh International Symposium on Computing and Networking (CANDAR) 2024年02月

研究論文（国際会議プロシーディングス）, 査読有り

Today, embedded real-time systems such as automobiles, spacecraft, and sensor networks are parts of social infrastructures. Since a system failure in these systems may lead to a severe accident, these systems should be designed as fault-tolerant systems. If a power failure occurs in an embedded real-time system, values of all flip-flops and main memory are lost, resulting in a system failure.This paper describes the design, implementation, and evaluation of a system-on-chip/system-in-package for a non-stop fault-tolerant real-time system that continues to operate even with an unstable power supply. We designed and implemented a non-stop fault-tolerant real-time system-on-chip (SoC) that integrates a non-stop microprocessor, a non-volatile memory (MRAM), a volatile memory (SRAM), and IO peripherals. We also co-designed and implemented a non-stop fault-tolerant real-time system-in-package (SiP) that integrates the SoC, an FPGA, memories, a USB power delivery (USB PD), DC/DC converters, a potentiometer, and a board-to-board (BtoB) connector at the same time to support functions not included in the SoC but required. We evaluated the bit error rate of store operations and benchmark performance with checkpoint creations on the actual SiP.

A Design of Multithreaded RISC-V Processor for Real-Time System

Yuta Nojiri, Nobuyuki Yamasaki

2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW) 2024年02月

研究論文（国際会議プロシーディングス）, 査読有り

The rising prominence of RISC-V, despite its inherent lack of multithreading support, has sparked research initiatives to design and implement multithreaded RISC-V processors. In this paper, we present a novel multithreaded RISC-V processor explicitly tailored for real-time systems. Our design allows for dynamic thread manipulation- encompassing creation, execution, halting, deletion, and more- to emulate the behavior of tasks in a real-time operating system’s task queue. We introduce specialized instructions to RISC-V to facilitate these thread control operations. The proposed processor is equipped with eight logical cores, enabling simultaneous execution of up to eight threads. A context cache is integrated to efficiently manage context switches between threads, achieving context switches in four clocks. This feature empowers the processor to concurrently run a greater number of threads than its core count. Simulation results underscore the benefits of our design: multithreaded execution yields an instruction per cycle (IPC) rate that surpasses single-threaded execution by up to 5.5 times. Furthermore, our priority system ensures preferential execution of high-priority threads over their lower-priority counterparts. Consequently, we have realized a multithreaded RISC-V processor capable of prioritized execution across eight threads and concurrent execution beyond its core count.

Design of Decoded Instruction Cache

Takero Magara, Nobuyuki Yamasaki

2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW) 2024年02月

研究論文（国際会議プロシーディングス）, 査読有り

Recent microprocessors improve performance by extracting various levels of parallelism. Among these, out-of-order processors focus on ILP to improve performance. On the other hand, out-of-order processors consume a lot of power because they fetch and decode many instructions.We propose a Decoded Instruction Cache (DIC), in which the control signals generated by decoding RISC instructions are stored as decoded instructions in the DIC. The scheme improves performance and reduces power consumption because the results of fetch and decode can be reused. The DIC also supports multi-threaded execution, so TLP is also improved.When implemented in a multithreaded RISC processor, the DIC improves IPC by 2.39%.

Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems

Shota Nakabeppu, Nobuyuki Yamasaki

IEICE Transactions on Electronics （Institute of Electronics, Information and Communication, Engineers, IEICE） E106.C （ 7 ） 365 - 381 2023年07月

研究論文（学術雑誌）, 共著, 査読有り

It is very important to design an embedded real-time system as a fault-tolerant system to ensure dependability. In particular, when a power failure occurs, restart processing after power restoration is required in a real-time system using a conventional processor. Even if power is restored quickly, the restart process takes a long time and causes deadline misses. In order to design a fault-tolerant real-time system, it is necessary to have a processor that can resume operation in a short time immediately after power is restored, even if a power failure occurs at any time. Since current embedded real-time systems are required to execute many tasks, high schedulability for high throughput is also important. This paper proposes a non-stop microprocessor architecture to achieve a fault-tolerant real-time system. The non-stop microprocessor is designed so as to resume normal operation even if a power failure occurs at any time, to achieve little performance degradation for high schedulability even if checkpoint creations and restorations are performed many times, to control flexibly non-volatile devices through software configuration, and to ensure data consistency no matter when a checkpoint restoration is performed. The evaluation shows that the non-stop microprocessor can restore a checkpoint within 5µsec and almost hide the overhead of checkpoint creations. The non-stop microprocessor with such capabilities will be an essential component of a fault-tolerant real-time system with high schedulability.

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Data Rearrange Unit for Efficient Data Computation

Akiyuki Mamiya, Nobuyuki Yamasaki

International Journal of Networking and Computing 12 （ 2 ） 295 - 316 2022年07月

研究論文（学術雑誌）, 共著, 査読有り

Recently, the demand for computation-intensive applications such as multimedia and AI applications has increased. Data-parallel execution units are typically used for calculations in these applications to increase computational throughput. However, the data required for computation may need to be accessed at discontinuous memory addresses, which can reduce computation efficiency. Generally, normal memory access instructions access data blocks of continuously allocated memory addresses, containing both valid and invalid data for computation. These memory access patterns result in low computation density in the data parallel execution units, wasting computation resources. Therefore, simply increasing the number of data-parallel execution units leads to an increase in wasted computational resources, which will become a significant issue in embedded systems where multiple resource limitations exist. It is essential to improve computational efficiency to perform practical computation in such systems. This paper introduces a Data Rearrange Unit (DRU), which gathers and rearranges valid computation data between main memory and execution units. The DRU improves the performance of multimedia and AI application by significantly reducing the access rate from/to main memory and increasing computation efficiency. It is applicable to most hardware architectures, and its effectiveness can be further enhanced by the execution unit interface that directly connects the DRU to the execution unit. We demonstrate the effectiveness of our DRU by implementation on the RMTP SoC, improving convolution throughput on a data-parallel execution unit by a maximum of 94 times while only increasing the total cell area by about 12.7%.

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Prioritized Asynchronous Calls for Parallel Processing on Responsive MultiThreaded Processor

Lopez Tomas A., Yamasaki Nobuyuki

Proceedings - 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022 （Proceedings - 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022） 46 - 55 2022年

研究論文（国際会議プロシーディングス）, 査読有り

With the advent of parallel processors for embedded systems, it is very important to design new runtime and system features so that embedded software developers can take advantage of the increased throughput and responsiveness without the hindrances of low-level synchronization and data sharing. In this paper, we design and implement a fully-prioritized, work-conserving, and event-driven parallel computing runtime on Responsive MultiThreaded Processor (RMTP), a simultaneous multi-threading (SMT) processing platform with priority for real-time systems, which implements hardware-based resource allocation and context switching. The proposed runtime achieves low-cost forks and fine-grained prioritized scheduling by using special-purpose hardware functionalities on the RMTP, and also reduces resource over-subscription penalties while allowing for dynamic parallelism by employing a continuation-stealing execution strategy. We evaluate the performance of the proposed system with a set of benchmarks derived from the MiBench suite, and show that meaningful speedup can be achieved even when the degree of parallelism at each level is dynamically varied.

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Real-Time Execution based on Fluid Scheduling by using IPC Control Scheme

Santo A., Yamasaki N.

Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 （Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021） 459 - 463 2021年

研究論文（国際会議プロシーディングス）, 査読有り

Fluid scheduling is an optimal real-time scheduling applicable to multiprocessor systems and is a scheduling model so that every real-time task is executed at a constant speed from release time to deadline. It is necessary for fluid scheduling to control the execution speed of each task. But, since the execution speed of the task is invariable in a conventional general purpose processor. Therefore, fluid scheduling is conventionally achieved by repeatedly executing and stopping tasks. However, this method incurs significant overheads due to frequent task switching. On the other hand, fluid scheduling without overhead by using an IPC control scheme has been proposed. The IPC control scheme controls the execution speed of each thread in an SMT processor. We propose a new IPC control scheme to extract thread-level parallelism and improve throughput effectively, also improving the schedulability of the fluid schedule. The evaluation results show that the proposed method improved the total throughput of the fluid schedule.

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Data Rearrange Unit for Efficient Data Computation in Embedded Systems

Mamiya A., Yamasaki N.

研究論文（国際会議プロシーディングス）, 査読有り

Recently demands for computation intensive applications such as convolutional neural networks (CNNs) have been increasing. In these applications, valid data for computation are allocated in non-continuous addresses. Therefore, common burst memory access pattern results in a low spatial locality of valid data per access. As a result, computation of data parallel execution units degrades in throughput, as computation resource is wasted by computing invalid data. This is especially a problem in embedded systems in which constraints in power consumption provoke a requirement for high computation efficiency. In this paper, we introduce a Data Rearrange Unit (DRU), a hardware unit rearranging computation data to increase spatial locality of valid data. The DRU drastically reduces the main memory access rate and increases computation efficiency by decreasing memory access to reduce power consumption. We demonstrate the effectiveness of our DRU by implementation on the RMTP SoC [1] [2] improving convolution throughput on a data parallel execution unit by a maximum of 94times, while only increasing the total cell area by about 13%.

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A Learning-based Fetch Thread Gating Mechanism for A Simultaneous Multithreading Processor

Ide Y., Yamasaki N.

Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020 （Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020） 19 - 28 2020年11月

研究論文（国際会議プロシーディングス）, 査読有り

Simultaneous Multithreading (SMT) technology is widely adopted in modern high-end processors to maximize on-chip hardware utilization. In an SMT processor, multiple threads are executed in parallel, sharing hardware resources. This technique aggregates potential efficiency which will not be available in a single thread processor. However, when a data cache miss or a branch prediction miss occurs, every thread competing for hardware resources causes the degradation of hardware utilization. Therefore, instruction fetch policies have been proposed to manage hardware resources efficiently in SMT processors. The fetch policies distribute hardware resources indirectly, through fetch bandwidth control. Conventionally, a fetch policy selects fetch threads based only on the resource usage at the moment, while the characteristics of threads are not exploited on decision. Therefore most conventional fetch control schemes only take effects only after an outstanding event occurs. Capability of resource restriction is limited even with an aggressive fetch control scheme. In this paper, we propose a Fetch Gate Estimator (FGE) that is a fetch gating mechanism based on machine learning, which is implemented as a hardware module. The FGE evaluates each thread to decide whether an instruction fetch from a thread should be gated. The FGE is trained dynamically by the execution statistics resulted from the inferences, so that characteristics of each thread are encoded into a learning model. Thus, the FGE is trained dynamically in parallel with execution of programs. We applied a single layer perceptron as learning model inside the FGE for circuit simplicity, and investigated performance impacts. Evaluation results show that the perceptron-based FGE can train itself from acquired execution statistics to identify inefficient threads adaptively, adjusting resources through the fetch gate control mechanism.

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Codeword set selection for the error-correcting 4b/10b line code with maximum clique enumeration

Takeda M., Yamasaki N.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences （IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences） E103A （ 10 ） 1227 - 1233 2020年10月

研究論文（学術雑誌）, 査読有り, ISSN 09168508

This paper addresses the problem of finding, evaluating, and selecting the best set of codewords for the 4b/10b line code, a dependable line code with forward error correction (FEC) designed for real-time communication. Based on the results of our scheme [1], we formulate codeword search as an instance of the maximum clique problem, and enumerate all candidate codeword sets via maximum clique enumeration as proposed by Eblen et al. [2]. We then measure each set in terms of resistance to bit errors caused by noise and present a canonical set of codewords for the 4b/10b line code. Additionally, we show that maximum clique enumeration is #P-hard.

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Space Responsive Multithreaded Processor (SRMTP) for Spacecraft Control

Nakabeppu S., Ide Y., Takahashi M., Tsukahara Y., Suzuki H., Shishido H., Yamasaki N.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings （IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings） 2020年04月

研究論文（国際会議プロシーディングス）, 査読有り

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Implementation of fluid scheduling using IPC control mechanism

Tsukahara Y., Nobuyuki Y.

Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS （Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS） 2019-December 402 - 405 2019年12月

研究論文（国際会議プロシーディングス）, 査読有り, ISSN 15219097

In real-Time systems such as automobiles, correctness of processing tasks depends not only on its result, but also on time. Real-Time scheduling is a basic approache to achieve real-Time execution in real-Time systems. Fluid scheduling is an optimal real-Time scheduling model, which keeps the execution speed of each task proportional to its processor utilization. However, the speed of a task cannot be controlled arbitrarily on a general processor, making it impossible to implement fluid scheduling directly. Therefore, there have been many studies on pseudo fluid scheduling where the algorithm is based on repeat task execution which speed is constant in an interval. We apply the special mechanisms of Responsive MultiThreaded Processor (RMTP) to the novel control mechanism in order to implement fluid scheduling directly. RMTP is a prioritized SMT processor for real-Time processing, which has 1. a thread speed control mechanism which controls execution speed of each thread and 2. a context cache enabling context switches in four clock cycles. In this paper, by adding a novel thread speed control mechanism, execution speeds of 40 threads are controlled to be constant over short time intervals, directly making fluid scheduling possible.

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Finding the maximum number of symbols for the 4b/10b line code with error correction

Takeda M., Yamasaki N.

Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019 （Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019） 460 - 464 2019年11月

研究論文（国際会議プロシーディングス）, 査読有り

In this paper, we present 20 symbols for the error correcting 4b/10b line coding scheme, increasing the number of available symbols from the 18 originally proposed. The two additional symbols are used to supplement special control codes and increase compatibility with other line codes such as 8b/10b. In addition, we show that the 20 found is the maximum number of symbols possible for 4b/10b by formulating the problem as the maximum clique problem, an NP-hard problem. Finally, we show that the generalized problem of finding a set with the maximum number of symbols is NP-hard as well.

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Fast interrupt handling scheme by using interrupt wake-up mechanism

Wada R., Yamasaki N.

研究論文（国際会議プロシーディングス）, 査読有り

In recent years, embedded real-time systems have grown in complexity and are required to be able to handle both periodic and aperiodic tasks. When an external interrupt occurs via an I/O peripheral, the program counter jumps to the corresponding exception vector. This results in large overhead due to context switching. However, embedded real-time systems are required to execute tasks in real-time with high precision. The Responsive Multithreaded Processor (RMTP), a prioritized SMT CPU, consists of eight hardware contexts treated as eight logical processing cores and has various hardware mechanisms for fine-grained real-time processing on the order of 10 μs. One hardware mechanism implemented in RMTP is an interrupt wake-up mechanism that enables interrupt-triggered thread wake ups. When a thread is designated to be an interrupt handling thread, it starts execution one clock cycle after an interrupt occurs. In this paper, we design and implement a software mechanism which reduces the interrupt response time by using this mechanism and demonstrate the effectiveness of our proposed method by RTL simulations. Evaluation results show that our proposed method achieves high real-time performance by reducing the interrupt response time by up to 82% compared to the baseline.

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Experimental validation of agile attitude control with sinc function-based profiler for reducing residual vibrations

Kamiya T., Shimoda K., Ozawa Y., Yokota K., Satoh T., Yamasaki N.

Proceedings of the International Astronautical Congress, IAC （Proceedings of the International Astronautical Congress, IAC） 2019-October 2019年

研究論文（国際会議プロシーディングス）, 査読有り, ISSN 00741795

This paper presents a tracking control system combining feedforward and feedback with shaped input, using a benchmark problem applied to a two-mode system. Simulations and experimental validation of the new control system for tracking control of flexible spacecraft including comparison with conventional methods are presented. The results show that the residual vibrations after the moves by the proposed control system are smaller than the conventional methods in the presence of an unknown high-order flexible mode. Sinc function-based command shaping where the spacecraft attitude is controlled along a sequentially commanded trajectory and the residual vibration after the move can be significantly reduced. Sinc function is known as an extra-insensitive function which has no frequency response above a certain threshold frequency. Three feedback controllers are applied to the control system and compared using the benchmark problem. This controller design has several unique characteristics. First, the sinc function-based shaped input is designed to reduce residual vibrations after maneuvers under the existence of unknown high-order mode. Conventional input shapers for flexible spacecraft are not effective for multi-mode system with unknown flexible modes, where actual flexible spacecraft usually has such unknown high-order flexible modes. Second, only the dynamics of the low-order mode need to be considered in designing all the feedforward, feedback controller, and shaped input. Experimental validation is performed by hardware-in-the-loop (HIL) test configuration with newly developed real-time onboard computer to evaluate the feasibility of processing load by the proposed algorithms for real-time processing. Because the proposed algorithms do not contain any iteration algorithm, the proposed algorithms can be implemented in actual satellites with feasible processing load. The assumed two-mode system represents the most simplified multi-mode system with unknown high-order mode, so the similar results can be expected for systems equipped with more complicated flexible structures.

Analysis of body bias control using overhead conditions for real time systems: A practical approach

Torres C.C.C., Okuhara H., Yamasaki N., Amano H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems） E101D （ 4 ） 1116 - 1125 2018年04月

研究論文（学術雑誌）, 査読有り, ISSN 09168532

In the past decade, real-Time systems (RTSs), which must maintain time constraints to avoid catastrophic consequences, have been widely introduced into various embedded systems and Internet of Things (IoTs). The RTSs are required to be energy efficient as they are used in embedded devices in which battery life is important. In this study, we investigated the RTS energy efficiency by analyzing the ability of body bias (BB) in providing a satisfying tradeoff between performance and energy. We propose a practical and realistic model that includes the BB energy and timing overhead in addition to idle region analysis. This study was conducted using accurate parameters extracted from a real chip using silicon on thin box (SOTB) technology. By using the BB control based on the proposed model, about 34% energy reduction was achieved.

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山崎 信行

論文 - 山崎 信行

山崎　信行

論文 - 山崎　信行