Details of a Researcher - Yamanaka, Naoaki

Papers - Yamanaka, Naoaki

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Scalable frame-synchronisation circuit for highly parallel optical interconnections

K. Yamakoshi, R. Kawano, N. Yamanaka

ELECTRONICS LETTERS Vol.35 ( No.24 ) 2117-2118 1999.11

Research paper (conference, symposium, etc.), Joint Work, Accepted

Dynamic Burst Transfer Time-Slot-Base Network

K. Shiomoto, N. Yamanaka

IEEE Communications Magazine Vol.37 ( No.10 ) 88-96 1999.10

Research paper (conference, symposium, etc.), Joint Work, Accepted

Integrated Physical and Logical Layer Design of Multimedia ATM Networks

S. D. Moitra, E. Oki, N Yamanaka

IEICE TRANSACTIONS on Communications Vol.E82-B ( No.9 ) 1531-1540 1999.09

Research paper (conference, symposium, etc.), Joint Work

New Scheduling Mechanisms for Achieving Fairness Criteria (MCR Plus Equal Share, Maximum of MCR or Max-Min Share

M. Naabeshima, N. Yamanaka

Trans of IECE of Japan Vol.E82-B ( No,6 ) 962-966 1999.06

Research paper (conference, symposium, etc.), Joint Work, Accepted

Scalable 10 Gbit/s 4 x 2 0.25μm CMOS/SIMOX ATM switch LSI circuit LSI circuit based on distributed contention control

E. Oki, . Yamanaka, K. Okazaki, Y. Ohtomo

ELECTRONIC LETTERS Vol.35 ( No.9 ) 1-2 1999.04

Research paper (conference, symposium, etc.), Joint Work

Performance Evaluation of High-Speed Admission Control in ATM Networks Based on Virtual Request Generation

E. Oki, N. Yamanaka

IEICE TRANSACTIONS on Communications Vol.E82-B ( No.3 ) 473-480 1999.03

Research paper (conference, symposium, etc.), Joint Work, Accepted

A Dynamic Reference Single-Ended ECL Input Interface Circuit for MCM-Based 80-Gbps ATM Switch

R. Kawano, N. Yamanaka, E. Oki, T. Kawamura

IEICE TRANSACTIONS on Communications vol.E82-c ( No.3 ) 519-525 1999.03

Research paper (conference, symposium, etc.), Joint Work, Accepted

Scalable 3-Stage ATM Switch Architecture Using Optical WDM Grouped Links Based on Dynamic Bandwidth Sharing

K. Nakai, E. Oki, N. Yamanaka

IEICE TRANSACTIONS on Communications E82-B ( 2 ) 265-270 1999.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

DTM: Dynamic Transfer Mode Based on Dynamically Assigned Short-Hold Time-Slot Relay

N. Yamanaka, K. Shiomoto

IEICE TRANSACTIONS on Communications Vol.E82-B ( No.2 ) 439-446 1999.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

Integrated physical and logical layer design of multimedia ATM networks

Moitra Soumyo D., Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E82-B ( 9 ) 1531 - 1540 1999

ISSN 0916-8516

This letter proposes an integrated approach to multimedia ATM network design. An optimization model that combines the physical layer design with the logical layer design is developed. A key feature of the model is that the objective to be maximized is a profit function. It includes more comprehensive cost functions for the physical and logical layers. A simple heuristic algorithm to solve the model is presented. It should be useful in practice for network designers and operators. Some numerical examples are given to illustrate the application of the model and the algorithm.

A Very-Compact 10-Gb/s Optical Module for 640-Gb/s WDM Interconnection

R. Kawano, S. Yasukawa, N. Yamanaka

Japan Institute of Electronics Packaging Vol.2 ( No.7 ) 552-555 1999

Research paper (conference, symposium, etc.), Joint Work, Accepted

An 80-Gbit/s ATM Switch MCM

K. Okazaki, N. Sugiura, A. Harada, T. Kishimoto, E. Oki, N. Yamanaka

Japan Institute of Electronics Packaging Vol.2 ( No.7 ) 556-560 1999

Research paper (conference, symposium, etc.), Joint Work, Accepted

Scalable 640-Gbit/s ATM switching system with self-load balancing mechanism

Yasukawa S., Yamanaka N., Oki E., Kawano R., Okazaki K., Santoso D.

1412 - 1417 1999

A T-bit/s ATM switching system architecture, called the OPTIMA switch, is proposed. This system is scalable and quasi-non-blocking by virtue of its self-load-balancing mechanism and high-speed interconnection effect. The self-load-balancing mechanism prevents overloading in the switch by automatically checking and balancing the internal load. An experimental 640-Gbit/s ATM switching system was developed and tested; the basic parts of switching function are demonstrated. The switching system was fabricated using advanced 0.25 mm-CMOS devices, high-density MCM technologies, and optical WDM interconnection technologies. The WDM interconnection system, a key part of the scalable 640-Gbit/s OPTIMA switching system, interconnects 80-Gbit/s switching modules using WDM routing technology. The developed 640-Gbit/s switching system can be applied in the creation of a platform for future high-speed multimedia network.

100-Gb/s throughput ATM switch MCM with a 320-channel parallel optical I/O interface

Kawano Ryusuke, Yamanaka Naoaki, Oki Eiji, Yasukawa Seisho, Okazaki Katsuhiko, Ohki Akira, Usui Mitsuo, Sato Nobuo, Katsura Kosuke, Ando Yasuhiro, Kagawa Toshiaki, Hikita Makoto

753 - 758 1999

For an ATM switch system, we have developed a 100-Gb/s I/O throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25 μm CMOS ATM switch LSIs and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using 8 optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from DC to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface.

New transfer methods for client-server traffic in ATM networks

Lecumberri David, Siu Kai Yeung, Narvaez Paolo, Nabeshima Masayoshi, Yamanaka Naoaki

1345 - 1349 1999

This paper presents new transfer schemes for client-server traffic over ATM networks, with the objective of achieving a bounded transmission time of about one second for as many connection requests as possible. We evaluate via simulations the performance of these new schemes in terms of network utilization, cell loss ratio, and transmission time. The simulation results show that these schemes provide effective means of supporting client-server traffic with quasi-real time requirements.

OPTIMA

Yamanaka Naoaki, Kawano Ryusuke, Oki Eiji, Yasukawa Seisho, Okazaki Katsuhiko

26 - 33 1999

A 640 Gb/s high-speed ATM Switching System that is based on the technologies of advanced MCM-C, 0.25μm CMOS and optical WDM interconnection is fabricated for future B-ISDN services. A 40-layer, 160 mm × 114 mm Ceramic MCM realizes the basic ATM switch module with 80 Gb/s throughput. The basic unit ATM switch MCM-C consists of an 8-chip advanced 0.25 μm CMOS VLSI and 32 chip I/O bipolar VLSIs. The MCM employs a 40 layer, very-thin-layer ceramic MCM and a uniquely structured closed loop type liquid cooling system is adopted to cope with the MCM's high-power dissipation of 230 W. The MCM is mounted on a 32 cm × 50 cm mother board. A three-stage ATM switch is realized by optical WDM interconnection between the high-performance MCMs. For WDM interconnection, newly developed compact size 10 Gb/s, 8 WDM optical transmitters and receivers are used. An optical WDM router based on an AWG (Arrayed Waveguide Router) is used for mesh interconnection of boards. The optical WDM interconnect has 640 Gb/s throughput and easy, simple interconnection. The system, MCM, and Optical WDM interconnection will be applied to future B-ISDN backbone networks.

Scalable-distributed-arbitration ATM switch supporting multiple QoS classes

Oki Eiji, Yamanaka Naoaki, Nabeshima Masayoshi

319 - 324 1999

This paper proposes a multi-QoS scalable-distributed-arbitration (MSDA) ATM switch that supports both the high-priority class and the low-priority class under the head-of-line-priority discipline. It has a crosspoint buffer and a transit buffer, each consisting of a high-priority buffer and a low-priority buffer. Arbitration is executed between the crosspoint buffer and the transit buffer in a distributed manner. The MSDA switch extends the advantage of our previously proposed single-QoS scalable-distributed-arbitration (SSDA) switch. It is expandable while permitting high output-line speeds due to the distributed arbitration. The SSDA switch has a problem when its delay-time-based cell selection mechanism is applied to the low-priority class due to the limitation of the number of bits for the delay measure in the cell overhead. We solved this problem by introducing a distributed-ring-arbiter-based cell selection mechanism at each crosspoint for the low-priority class. The low-priority transit buffer at each crosspoint has virtual queues in accordance with the upper input ports. Cells for the low-priority class are selected by distributed ring arbitration among the low-priority crosspoint buffer and the virtual queues at the low-priority transit buffer. Simulations confirm that the MSDA switch ensures fairness in terms of delay time for the high-priority class, while it ensures fairness in terms of throughput for the low-priority class.

Distributed traffic control method for Tbit/s multi-stage ATM switching systems

Nakai Kohei, Oki Eiji, Yamanaka Naoaki

109 - 114 1999

This paper proposes a distributed traffic control method for large multi-stage ATM switching systems. In the proposed switching system, each port of the basic switches has its own traffic monitor, and each line unit (LU) periodically obtains congestion information about available paths from OAM cells in order to route a new virtual circuit independently. The performance of the proposed system depends on the interval between OAM cells. We show how an appropriate interval can be determined in order to maximize the number of user cells that each LU can send.

Nonblocking multi-stage ATM switch using cell-based routing with a hierarchical cell sorting mechanism

Santoso David, Yasukawa Seisho, Yamanaka Naoaki, Miki Tetsuya

265 - 270 1999

A multi-stage switching architecture is a key technology for budding a high-speed ATM switching system. An effective way to make a multi-stage switch nonblocking is to use cell-based routing. However, cell-based routing may cause cell-sequence disorder at the output of the switching fabric. This paper proposes a hierarchical cell-sorting (HCS) switch architecture, which is a nonblocking multi-stage AIM switch using cell-based routing technology. Each basic HCS switch performs cell sorting at every crosspoint, based on timestamp information in the cell-header. This arranges the cells in sequence at the output of each basic HCS switch, since the crosspoints are hierarchically interconnected from the input port to the output port of a basic HCS switch. A multi-stage HCS switch is constructed by interconnecting the input and output lines of these basic HCS switches in a hierarchical manner. Thus, the cell sequence in each final output of the multi-stage switch is preserved in a hierarchical manner. In this way, cell-based routing with 100% throughput is achieved, with no need for internal speed-up techniques.

i-QOCF (iterative quasi-oldest-cell-first) algorithm for input-queued ATM switches

Nabeshima Masayoshi, Yamanaka Naoaki

25 - 30 1999

This paper proposes a new scheduling algorithm for input-queued ATM switch, called iterative quasi-oldest-cell-first (i-QOCF) algorithm. In i-QOCF, each input port and each output port maintains its own list. The length of the list can be N, 2×N, ..., B×N, where B is the size of the buffer that queues cells destined for an output port. The list maintained by an input port contains the identifiers of those output ports to which that input port will send a cell. The list maintained by an output port contains the identifiers of input ports which have a cell destined for that output port. We show the performance of i-QOCF and results in which we compare i-QOCF with i-OCF in terms of cell delay time. We find that an input-queued ATM switch with i-QOCF and virtual output queue (VOQ) can achieve 100% throughput for independent arrival processes. The 3-QOCF is enough to achieve convergence during one cell time. If we use a 3-QOCF in which the list length is 3×N, then its cell delay time performance is almost the same as that of a 4-OCF.

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