Details of a Researcher - Yamanaka, Naoaki

Papers - Yamanaka, Naoaki

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5-Tb/s frame-based ATM switching system using 2.5-Gb/s × 8-λ optical switching technique

Yamakoshi Kimihiro, Nakai Kohei, Matsuura Nobuaki, Oki Eiji, Yamanaka Nabuaki

88 - 92 2001

This paper describes the hardware architecture and performance of a 5-Tb/s frame-based (FB) ATM switching system OPTIMA-2 (OPTically Interconnected Distributed Multi-stage TB/s-ATM switching Network Architecture -2). First, we describe the switch architecture, which is a non-blocking 3-stage switch using optical wavelength division multiplexing (WDM) and dynamic bandwidth sharing technique. Variable-length FB-ATM cells, which can encapsulate IP packets, can be switched while keeping throughput fairness. Second, we propose a scheduling technique for variable-length packets used in the WDM system which selects packets from the eight wavelengths. We show that the scheduling technique can keep fairness and a small delay for variable-length packets. A pipelined-scheduling technique for variable-length packets is also proposed for a high-speed and large-capacity switching system.

WDM optical switching to achieve 5 Tb/s throughput

Matsuura Nobuaki, Yamakoshi Kimihiro, Oki Eiji, Nakai Kohei, Yamanaka Naoaki, Ohyama Takaharu, Akahori Yuji

2083 - 2087 2001

This paper describes a Wavelength-Division-Multiplexing (WDM) optical switching technique that achieves 5-Tb/s switch throughput. This technique is employed in our previously described OPTically Interconnected Distributed Multi-stage Tb/s-ATM switching Network Architecture, called OPTIMA-2. This is a scalable and non-blocking 3-stage switch employing optical WDM and dynamic bandwidth sharing. An inter-stage, cell-based WDM switch is fabricated in combination with field programmable gate arrays (FPGAs) and 2.5-Gb/s 8-wavelength optical interconnection modules. Experimental results from a 5-Tb/s switching system are introduced.

5-Tbit/s frame-based ATM switching system using 2.5-Gbit/s × 8 optical WDM links

Yamakoshi K., Nakai K., Matsuura N., Oki E., Kawano R., Yamanaka N.

3117 - 3121 2001

The hardware architecture of a 5-Tbit/s FB (Frame-Based) ATM switching system OPTIMA-2 (OPTically Interconnected Distributed Multi-stage Tbit/s-ATM switching Network Architecture -2) is described. OPTIMA-2 has a non-blocking 3-stage switch architecture employing optical WDM links and dynamic bandwidth sharing. The WDM links are composed of a sender port, wavelength AWG router and receiver port. The sender port at the output port of a switch-element allocates a packet to one of eight WDM wavelengths and transmits it. The receiver port receives packets of all eight wavelengths via the wavelength AWG router and merges them at an input port of the next-stage switch-element. Total bandwidth is limited to 10 Gbit/s, but the maximum bandwidth of each wavelength is designed to be 2.5 Gbit/s to prevent the statistical multiplexing gain from falling. A scheduler, which selects variable-length packets from the eight wavelengths, can keep fairness and a small delay. The bandwidth of each wavelength is changed dynami cally by the system so that the traffic in each wavelength is equally distributed among the total bandwidth. In OPTIMA-2, variable-length FB-ATM cell, which is familiar with the IP packet, can be switched while keeping the throughput fairness.

次世代コアネットワークのメディアゲートウェイおよびコアノード技術

N. Yamanaka, K. Yamakoshi, R. Kawano

NTT R&D Vol.49 ( No.12 ) 698-705 2000.12

Research paper (bulletin of university, research institution), Joint Work

OPTIMA: Scalable, Multi-Stage, 640-Gbit/s ATM Switching System Based on Advanced Electronic and Optical WDM Technologies

N. Yamanaka, E. Oki, S. Yasukawa, R. Kawano, K. Okazaki

IEEE Trans on Communications Vol.E83 ( No.7 ) 1488-1496 2000.07

Research paper (conference, symposium, etc.), Joint Work, Accepted

An 80 Gb/s Optical I/O Interface ATM Switch MCM

R. Kawano, N. Yamanaka, E. Oki, K. Okazaki, and A. Ohki

Trans of IEICE of Japan Vol.J83-B ( No.4 ) 471-478 2000.04

Research paper (conference, symposium, etc.), Joint Work, Accepted

Very Compact Scalable 80 Gbit/s ATM Switching Module

E. Oki, N. Yamanaka, K. Okazaki, R. Kawano and Y. Ohtomo

Trans of IEICE of Japan Vol.J83-B ( No.4 ) 490-500 2000.04

Research paper (conference, symposium, etc.), Joint Work, Accepted

A Distributed Traffic Control Scheme for Large-Scale Multi-Stage ATM Switching System

K. Shiomoto, E. Oki, N. Yamanaka

IEICE TRANSACTIONS on Communication Vol.E83-B ( No.2 ) 231-237 2000.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

Performance of Scalable-Distributed-Arbitration ATM Switch Supporting Multiple QoS Classes

E. Oki, N. Yamanaka, M. Nabeshima

IEICE TRANSACTIONS on Communication Vol.E83-B ( No.2 ) 204-213 2000.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

The i-QOCF (Iterative Quasi-Oldest-Cell-First) Scheduling Algorithm for Input-Queued ATM Switches

M. Nabeshima, N. Yamanaka

IEICE TRANSACTIONS on Communication Vol.E83-B ( No.2 ) 182-189 2000.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

Scalable multi-stage cell-switching architecture

Yasukawa Seisho, Oki Eiji, Nakai Kohei, Yamanaka Naoaki

NTT R and D 49 ( 12 ) 706 - 712 2000

ISSN 0915-2326

An architecture is described for a switch that is suitable for future large-scale packet-convergence networks. This optically interconnected multi-stage ATM switch architecture (OPTIMA) is a multi-stage switch architecture, and an OPTIMA switch can perform two types of QoS switching. The architecture is scalable - switching capacity can be expanded by interconnecting identical unit switches, without causing degradation in switching performance, because of the switch's route-control mechanism for high-priority traffic and its self-load balancing mechanism for low-priority traffic. Analysis and simulation demonstrated that an OPTIMA switch has high-performance switching capability. Also described is the hardware architecture for the 640 Gbit/s OPTIMA switching system. The OPTIMA switch is suitable for use as a backbone node in future packet-convergence networks.

ATM flow control based on rate prediction with extrapolation under WAN environment

Hasegawa Haruhisa, Yamanaka Naoaki, Shiomoto Kohei

Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi) 83 ( 7 ) 1 - 14 2000

ISSN 8756-6621

The adaptive rate control technique AREX (Adaptive Remote rate control based on Extrapolation) is proposed, which realizes an access to a high-speed bandwidth and a high utilization rate without increase of required buffer amount and degradation of the transfer characteristics, even in an ATM (Asynchronous Transfer Mode) network with a long delay, by carrying out prediction of congestion based on periodically reported information on the utilization rate. In the AREX method, the downstream node (Obsv node) without a rate modification capability observes the utilization rate of the output link and informs the upstream node (Cntl node) with a rate control capability. Based on the information, the Cntl node controls the output rate dynamically. In the conventional feedback rate control, only past information can be obtained due to propagation delay, and the information is given only at an appropriate notification interval. Therefore, as the network size is increased, the necessary amount of buffers is increased, or the response speed for the bandwidth modification request from users needs to be reduced. However, since the worst traffic is estimated from the notification information in the AREX method, a safe rate control can be realized even if the notification is delayed and is given intermittently. Also, by regulating the rate enhancement ratio as an appropriate increasing function, quick access to a large bandwidth can be realized at low load, and a high congestion control effect is achieved at high load. © 2000 Scripta Technica.

High-speed switch system for multimedia service nodes

Yamanaka Naoaki, Yamakoshi Kimihiro, Kawano Ryusuke

NTT R and D 49 ( 12 ) 698 - 705 2000

ISSN 0915-2326

Breakthrough technologies are described for switching hardware and system integration that will enable the development of a Tbit/s-class switching system for multi-service backbone networks. Also described is a switching architecture that is familiar with IP traffic while retaining the advantages of a conventional ATM switch. Following papers describe the newly developed 640-Gbit/s OPTIMA (OPTically Interconnected Multi-stage ATM switch architecture) switching system, including the 640-Gbit/s switching system architecture, 80-Gbit/s switch-element architecture, hardware architecture, and packaging technique.

A 10-Gb/s (1.25 Gb/s x 8) 4 x 2 0.25-mm CMOS/SIMOX ATM Switch Based on Scalable Distributed Arbitration

E. Oki, N. Yamanaka, Y. Ohtomo, K. Okazaki, R. Kawano

EEE JOURNAL OF SOLID-STATE CIRCUITS Vol.34 ( No.12 ) 1921-1934 1999.12

Research paper (conference, symposium, etc.), Single Work, Accepted

80 Gbit/s ATM switch MCM based on multilayer ceramic technology

K. Okazaki, N. Sugiura, A. Harada, N. Yamanaka, and E. Oki

ELECTRONICS LETTERS Vol.35 ( No.24 ) 2074-2076 1999.11

Research paper (conference, symposium, etc.), Joint Work, Accepted

Scalable frame-synchronisation circuit for highly parallel optical interconnections

K. Yamakoshi, R. Kawano, N. Yamanaka

ELECTRONICS LETTERS Vol.35 ( No.24 ) 2117-2118 1999.11

Research paper (conference, symposium, etc.), Joint Work, Accepted

Dynamic Burst Transfer Time-Slot-Base Network

K. Shiomoto, N. Yamanaka

IEEE Communications Magazine Vol.37 ( No.10 ) 88-96 1999.10

Research paper (conference, symposium, etc.), Joint Work, Accepted

Integrated Physical and Logical Layer Design of Multimedia ATM Networks

S. D. Moitra, E. Oki, N Yamanaka

IEICE TRANSACTIONS on Communications Vol.E82-B ( No.9 ) 1531-1540 1999.09

Research paper (conference, symposium, etc.), Joint Work

New Scheduling Mechanisms for Achieving Fairness Criteria (MCR Plus Equal Share, Maximum of MCR or Max-Min Share

M. Naabeshima, N. Yamanaka

Trans of IECE of Japan Vol.E82-B ( No,6 ) 962-966 1999.06

Research paper (conference, symposium, etc.), Joint Work, Accepted

Scalable 10 Gbit/s 4 x 2 0.25μm CMOS/SIMOX ATM switch LSI circuit LSI circuit based on distributed contention control

E. Oki, . Yamanaka, K. Okazaki, Y. Ohtomo

ELECTRONIC LETTERS Vol.35 ( No.9 ) 1-2 1999.04

Research paper (conference, symposium, etc.), Joint Work

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