Details of a Researcher - Yamanaka, Naoaki

Papers - Yamanaka, Naoaki

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A simple cell spacer architecture regenerating source cell interval for multiple traffic classes

Shiomoto Kohci, Yamanaka Naoaki

IEICE Transactions on Communications E80-B ( 1 ) 187 - 191 1997

ISSN 0916-8516

A new simple cell spacing architecture that guarantees the peak cell interval and realizes preferential contention resolution is proposed. Scheduling the cell emission on departure of the previous cell not arrival allows the source peak cell interval to be regenerated without clumping. Priority control is also realized in the proposed spacer. A connection is scheduled either at the head or tail of the contention chain depending on its priority. The proposed method is applied to realize the UPC function. The proposed cell spacer eliminates the clumping effects of CDV completely and achieves high bandwidth efficiency.

Advanced ATM switching system line interface hardware technologies based on MCM-D integrated with ASIC and S-RAMS

Yamanaka Naoaki, Kawamura Tomoaki, Kaizu Katsumi

286 - 289 1997

This paper describes newly developed advanced ATM switching system hardware structures. They are based on the Si-Substrate MCM-D technology which integrates ASIC custom VLSIs, high-speed S-RAMs and FPGAs (Field Programmable Gate Arrays). The MCM-D module realizes the ATM layer function by combining a high-performance ASIC with high-speed S-RAM cache. This is made possible by high density packaging and high-speed (20 ns) access to 1-Mbit of memory. The MCM employs 8 S-RAMs, possible with the stacked RAM technique, to reduce module size. This sub-module technology and MCM technology will advance the development of practical B-ISDN ATM switching systems.

Tandem-crosspoint ATM switch architecture and its cost-effective expansion

Oki Eiji, Yamanaka Naoaki, Yasukawa Seisho

45 - 51 1997

This paper proposes a high-speed input and output buffering ATM switch, named the Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at all crosspoints. The TDXP switch architecture offers several advantages. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. These merits make it easy to implement a high-speed ATM switch. Numerical results show that the TDXP switch can effectively eliminate HOL blocking and achieve high throughput. In addition, we discuss how TDXP switches can be combined to form larger switches in a cost-effective way. We clarify the relative advantages of the crossbar switch configuration and the three-stage Clos switch configuration in achieving a specific throughput. Because the three-stage Clos switch configuration is not strictly non-blocking, we introduce a nearly non-blocking condition and evaluate switch throughput under the condition. The evaluation shows that crossbar switch configuration becomes more cost effective as the throughput of individual switch LSIs, which depends on device technologies, increases.

Extended multicasting technique to allow multiple destinations per output port in ATM switches

Agrawal Jagan P., Yamanaka Naoaki

IEEE Communications Letters 1 ( 4 ) 117 - 118 1997

ISSN 1089-7798

When a multicast cell at an aynchronous transfer mode (ATM) switch requires distribution of its copies to the multiple users and/or outgoing sub-rate links served by one of its output ports, multiple cell copies at that output port are required. The conventional copy approach and broadcast approach of multicasting either cannot handle such situations or handles at the cost of switch performance. In this letter we propose a technique to enhance the ability of the copy and broadcast approaches to multicasting to enable them to handle such situations efficiently and economically.

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A high-speed ATM switch based on scalable distributed arbitration

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E80-B ( 9 ) 1372 - 1376 1997

ISSN 0916-8516

This paper proposes a high-speed crosspoint-buffer-type ATM switch, named Scalable-Distributed-Arbitration (SDA) switch. The SDA switch employs a new arbitration scheme that allows the switch to be scalable. The SDA switch has a crosspoint buffer and a transit buffer at every crosspoint. Arbitration is executed between the crosspoint buffer and the transit buffer. The arbitration selects a cell based on delay time using a synchronous counter. The selected cell is transferred from a crosspoint buffer to the output port by way of several transit buffers. Since arbitration is executed in a distributed manner at each crosspoint and the arbitration time does not depend on the switch size, the SDA switch can be expanded to realize large throughput. Numerical results show that the SDA switch ensures fairness in terms of delay time. In addition, the maximum delay time and the required crosspoint buffer size of the SDA switch are reduced, compared with those in the conventional switch based on ring arbitration. Thus, the proposed SDA switch based on the new arbitration scheme has a simple and expandable architecture, and will be suitable for future high-speed multimedia ATM networks.

An expandable time-division circuit switching LSI and network architecture for broadband ISDN

Kikuchi Shiro, Yamanaka Naoaki

IEEE Journal on Selected Areas in Communications 14 ( 2 ) 328 - 336 1996.02

ISSN 0733-8716

A broadband network architecture is proposed that integrates multimedia services, such as data, video, and telephony information, using 52-Mb/s based STM-paths at the user network interface (UNI). The user can access any new service via the STM-based access network via either synchronous transfer mode (STM) switching or asynchronous transfer mode (ATM) switching. STM circuit switching supports long duration, constant bandwidth data transfer services such as video and high-definition television (HDTV) distribution and will also be used for the crossconnect system. Circuit switching can provide transparent transmission during long connection periods. This paper also proposes an expandable time-division switch architecture, an expandable time-division switching LSI, and an expandable switching module for small to large size system applications. The proposed time-division switching LSI, module, and system handle 52-Mb/s bearer signals and have throughputs of 2.4 Gb/s, 10 Gb/s, and 40 Gb/s, respectively. The time-division switch realizes video distribution with 1:n connections. Finally, a local switching node that features an expandable 52-Mb/s time-division circuit switching network is shown for multimedia access networking.

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A very high-speed ATM switch architecture using internal speed-up technique

Genda Kouichi, Doi Yukihiro, Endo Kenichi, Yamanaka Naoaki

NTT R and D 45 ( 9 ) 847 - 853 1996

ISSN 0915-2326

As a switch architecture of the AMC with switch throughput of 160 Gbit/s, we proposed an internal speed-up crossbar-type ATM switch architecture. This switch accommodates 10-Gbit/s cell streams from AHMs in order to guarantee the QoS of switched cells. A new high-speed arbitration algorithm using three buses on each output line, called the bidirectional arbiter, is used. This handles output contention about twice as fast as the conventional ring-arbiter and has the same fairness function. This increases the switch throughput to 160 Gbit/s efficiently. By combining our high-speed switch and AHMs, we should be able to make a sub-terabit/s ATM switching system for the future Broadband ISDN network.

High-performance packaging technology for ultra-high-speed ATM switching system

Kaizu Katsumi, Kishimoto Tohru, Sasaki Shinich, Yamanaka Naoaki, Genda Kouichi

NTT R and D 45 ( 9 ) 863 - 871 1996

ISSN 0915-2326

This paper describes high-performance, high-density multichip modules (MCMs) using a copper polyimide multi-layer substrate and innovative heat-pipe cooling for high-speed ATM switching system. High-speed ATM link wires are interconnected on the top surface of the MCMs by the newly developed flexible printed circuit cables and connectors to reduce the rear-side I/O count and achieve 620-Mbit/s 32-bit parallel interconnection. A heat-pipe is attached to the back surface of each MCM to cool the power dissipation, which is 30 W per MCM. With a 2-m/s forced airflow, a prototype ATM switch system operated at 320 Gbit/s (with 8×8 MCMs) with a maximum junction temperature of less than 85 °C. These results indicate that this technology is suitable for future B-ISDN high-speed swithing systems.

An expandable multicast ATM switch based on copy-trunk with new delay control and cell spacing functions

Kurimoto Takashi, Genda Kouichi, Yamanaka Naoaki

IEICE Transactions on Communications E79-B ( 8 ) 1061 - 1067 1996

ISSN 0916-8516

A multicast ATM switch with a new external copy module is proposed. The copy module, called copy-trunk, has two new functions to guarantee the QoS of P-MP cells: The delay priority control function and the output-cell-spacing control function. By using the delay priority control function, copied cells with high-priority are always released earlier than those with low-priority so as to avoid increasing the delay time of real-time traffic. The output-cell-spacing control function is used to reduce the burstiness of the output traffic. The output pattern is adaptively controlled by measuring the input load. The effects of these two controls are quantitatively described. The copy-trunk allows the multicast capability of a switch to be efficiently and economically increased to satisfy future traffic volume and services.

Performance evaluation of an ATM connection with several cell flow components

Yamanaka Naoaki, Pitcho Francis, Sato Hiroaki

IEICE Transactions on Communications E79-B ( 5 ) 716 - 718 1996

ISSN 0916-8516

SUMMARY This letter studies the Peak Cell Rate (PCR) policing of ATM connections that consist of multiple cell flow components. It is shown that the conventional methods proposed for policing the aggregate flow do not use the network's resources efficiently. This letter proposes a simple and efficient UPC (Usage Parameter Control) mechanism based on a tandem leaky bucket for multi-component ATM connections. The results show that network resource requirements can be minimized, with reasonable hardware complexity.

An optimum design scheme for flexible multi-QoS logical ATM networks

Oki Eiji, Yamanaka Naoaki

NTT R and D 45 ( 7 ) 673 - 678 1996

ISSN 0915-2326

An optimum design scheme is proposed for VC network topologies on a Flexible Multi-QoS Logical ATM Network, named Full-Net. Full-Net offers high-quality Virtual-Path (VP) networks and controls end-to-end QoS only at the VP-networks access points. To develop the optimum network topology for multimedia traffic in a single ATM network, a logically configured Virtual Channel Handler (VCH) interconnection network is associated with each QoS class. To achieve an optimum design scheme for VC networks, the number of disjoint routes is introduced as the parameter used to optimize VC network topology. The number of disjoint routes is chosen so as to maximize total network efficiency. The optimum number of disjoint routes depends on the required QoS, VC-traffic characteristics, and traffic demand.

High-speed ATM switching system technologies

Yamanaka Naoaki, Doi Yukihiro, Fukuda Hideki, Takenaka Toyofumi, Yashiro Zenichi

NTT R and D 45 ( 9 ) 839 - 846 1996

ISSN 0915-2326

ATM network resource management techniques for CBR virtual paths/channels

Sato Youichi, Yamanaka Naoaki, Sato Ken Ichi

IEICE Transactions on Communications E79-B ( 5 ) 684 - 691 1996

ISSN 0916-8516

SUMMARY The benefits of ATM techniques have been widely recognized and many organizations envisage the introduction of ATM techniques into their telecommunication networks. The ATM benefits can, however, be fully exploited only after effective network resource management techniques have been developed. This paper focuses on CBR-VP management techniques. The ATM transport network architecture and VP roles are summarized. Next, the issues of VP accommodation design are described. The point is how to create a design that accommodates cell loss and cell delay jitter, both of which depend on various network parameters and conditions. For this purpose, analytical procedures based on an M/D/1 queueing model are adopted. The approximation method is shown to be very effective in practical use through computer analysis. The method guarantees conservative QOSs. Finally, the proposed method is applied to several design examples to illustrate VP management issues. The proposed method will enable ATM techniques to be introduced to our telecommunication networks by the mid.

Simple multi-QoS ATM buffer management scheme based on adaptive admission control

Shiomoto Kohei, Yamanaka Naoaki

447 - 451 1996

This paper proposes simple and effective multi-QoS ATM buffer management scheme with admission control. The proposed scheme supports three QoS-service classes by two separate buffers with strict priority and measurement-based as well as individual CLR-based admission control. Two guaranteed classes for video and reliable data are multiplexed into a high priority buffer and individual CLR management is employed. We show that the proposed individual CLR management is simple and effective compared to separate buffers with WRR (weighted round robin). One best-effort class is assigned to the low priority buffer, and includes LAN intercommunication using upper-layer congestion control mechanism. Since measurement-based adaptive admission control is employed for best-effort service, the proposed adaptive admission control achieves high bandwidth efficiency while keeping the target CLR. This multi-QoS management scheme can be applied to future multimedia ATM networks that integrate video, data, and other services.

160 Gbit/s high-speed ATM switching system

Yamanaka Naoaki, Kaizu Katsumi, Kishimoto Tohru, Genda Kouichi

NTT R and D 45 ( 9 ) 855 - 862 1996

ISSN 0915-2326

This paper describes a 160-Gbit/s high-speed multi-chip ATM switching system for broadband ISDN. This system uses a copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 11-layer ceramic power supply layers. It uses 64 MCMs that are interconnected by a 98-high-way flexible printed circuit connector. Si-bipolar VLSIs are mounted on a MCM using the 15-μ m very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is used. The system switches ATM cells at a thoughtput of up to 320 Gbit/s and it is applicable for future B-ISDN.

ALPEN

Yamanaka Naoaki, Shiomoto Kohei, Hasegawa Haruhisa

392 - 397 1996

This paper proposes ALPEN, a simple, flexible and cost-effective ATM-WAN architecture that can emulate multiple ATM-layer protocols such as ABR, FRM, and SHM, using a simple ATM transit network. With ALPEN, it is easy to implement any new ATM-layer protocol by modifying only the edge nodes. Edge nodes are directly responsible for the management of the users' bandwidth, eliminating the long round trip delays of conventional networks. The transit network does not support multi ATM-layer protocols and ALPEN's transit switches do not need large computational power. Flexible, adaptive and sophisticated protocols for an efficient use of resources can be easily supported by the network's edge node. Users can then send as much traffic as permitted by the network's available bandwidth.

ALPEN

Yamanaka Naoaki, Shiomoto Kohei, Hasegawai Haruhisa

IEICE Transactions on Communications E79-B ( 4 ) 611 - 615 1996

ISSN 0916-8516

Real-time emulation method for ATM switching systems in broadband ISDN

Matsumura Tsuneo, Yamanaka Naoaki, Yamaguchi Ryoichi, Ishikawa Keiji

55 - 60 1996

This paper describes a real-time emulation method based on the use of commercial FPGAs, high-speed interconnect switch devices and software tools (gate array LSI to/from FPGA netlist migration and multi-FPGA partitioning tools) to emulate large scale high-speed communication switching system without the need for conventional specific wiring structures between FPGAs and timing control circuit insertion. This method is applied to line interface units (LUs) that have 20 MHz operation; we employ the LU board and emulation boards, both of which have hierarchical structures with small sub-boards. The proposed LU board structure has the advantage of utilizing a common LU board for rapid prototyping as well as developing cost effective, practical high-performance Asynchronous Transfer Mode (ATM) switching systems for broadband ISDN (Integrated Services Digital Networks). The results of multiple FPGA partitioning on the emulation board suggest that the proposed method will yield economic systems that are also practical.

SAM

Pitcho Francis, Yamanaka Naoaki

IEICE Transactions on Communications E78-B ( 9 ) 1330 - 1332 1995.09

ISSN 0916-8516

Multiple-availability-level ATM network architecture

Oki Eiji, Yamanaka Naoaki, Pitcho Francis

IEEE Communications Magazine 33 ( 9 ) 80 - 88 1995.09

ISSN 0163-6804

ATM networks have the potential to achieve switch cost reduction and multi-level network availability because of their high flexibility. For that purpose, this article proposes to use Virtual Circuit (VC) route self-healing schemes to achieve a multiple-availability-level ATM network. First, the advantages of VC route restoration for ATM networks are presented; Virtual Path level and physical level restoration strategies are then compared. The concept of Full-Net is explained, and the self-healing scheme of a VC route is proposed. Finally, the impact of the logical network configurations on network survivability and resource management is presented.

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