Details of a Researcher - Yamanaka, Naoaki

Papers - Yamanaka, Naoaki

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Dynamic reference single-ended ECL input interface circuit for 80Gbit/s MCMs

Kawano R., Yamanaka N., Oki E., Kawamura T.

Electronics Letters 34 ( 17 ) 1641 - 1643 1998.08

ISSN 0013-5194

ALPEN

Yamanaka Naoaki, Shiomoto Kohei, Hasegawa Haruhisa

Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi) 81 ( 8 ) 19 - 30 1998.08

ISSN 8756-6621

This paper proposes a new network architecture, ALPEN (ATM multi-protocol emulation network), based on a new concept for realizing full-scale multimedia communication networks. In ALPEN, various communication protocols, such as ABR (available bit rate), FRM (fast resource management), or SHM (short hold mode), can be handled using a single, simple transit network. Each protocol is emulated at the edge node of the WAN (wide area network), and the status of the transit network is checked by periodically examining the residual bandwidth information of each route. ALPEN is a cost-effective and flexible network architecture because it enables us to implement new services or protocols easily by modifying only the edge nodes. In ALPEN, since individual edge nodes periodically obtain the bandwidth information, it is possible to respond promptly to a user's request to change his bandwidth. In particular, when the network's RTT (round trip time) is long, as in a WAN, ALPEN is a promising way to resolve the problem of performance responsibility. Although each edge node periodically checks the disperse information to all destination edge nodes on a residual bandwidth, the information might be old, or it might be necessary to process it independently at the multiple edge nodes. There-fore, the parameter of "effective residual bandwidth" is estimated by a statistical method; the estimation also considers that bandwidth resources may be overbooked by multiple edge nodes. The statistical method is described in this paper. The ALPEN introduced in this paper is an effective architecture that makes it possible to implement new or various unforeseeable network services in the future multimedia era, in which various services and protocols may exist simultaneously. © 1998 Scripta Technica.

Feedback rate control with congestion prediction by edge nodes in ATM-WAN

Hasegawa Haruhisa, Yamanaka Naoaki, Shiomoto Kohei

1541 - 1546 1998

This paper proposes a new adaptive remote rate control based on extrapolation called AREX. AREX does not require a high-speed switching node to have high calculation load. Consequently, transit switches with high-speed interface do not always need to have high calculation power. As a result rate control can be implemented easily in a WAN. AREX reduces the major problems of feedback rate control, inaccuracy of feedback information and large necessary buffer space caused by long propagation delay. In AREX, a high-speed transit switching node only observes the link utilization ratio of the output VP and notifies it to upstream nodes. Local switching nodes with spare calculation power calculate and control the output rate of each VC. Because the admissible cell rate of each VC is calculated by local switches, ABR service can be emulated there. This paper describes the mechanisms of AREX and discusses the function form that determines its characteristics. AREX tries to converge utilization to the target value. The relationship between target value and overload probability is clarified for network management. The performance of ABR emulated by AREX is evaluated by computer simulation. The results show that AREX provides high throughput and requires less buffer capacity even in a network with long propagation delay.

New scheduling mechanisms which efficiently utilize policing for GFR service

Nabeshima Masayoshi, Yamanaka Naoaki, Hasegawa Haruhisa

80 - 85 1998

Access to Document (DOI)

10-Gb/s palm-size optical transceiver/receiver set with novel cooling structure for WDM sub-Tb/s ATM switch system

Kawano Ryuusuke, Yamanaka Naoaki, Yasukawa Seishou, Okazaki Katsuhiko

839 - 843 1998

We have developed compact 10-Gb/s optical transceiver and receiver modules for a WDM sub-Tb/s ATM switch system. Each module has a cooling part whose structure is based on a high-performance heat transfer device and micro-fans. Instead of a conventional radiation fin, a high-performance device is used to conduct heat from heat sources, such as a laser, to the fin inside the duct on the end of the module, where it is radiated by push-pull micro-fans. Because the conventional cooling structure based on straight fin occupies a larger volume, it is not suitable for high-density arrangement. Our cooling system achieved a heat resistance value of 1.8 °C/W, which was sufficient to stabilize the operation of the laser unit. This cooling structure enables a compact structure to handle high-density heat generation. The power dissipations of the TX and RX are 9.65 and 22.5 W, respectively. The TX and RX modules are the same size: 80×120×20 mm. Measurements show that these optical modules can operate stably without any additional cooling systems even in the switching unit.

Tandem-crosspoint ATM switch with input and output buffers

Oki Eiji, Yamanaka Naoaki

IEEE Communications Letters 2 ( 7 ) 189 - 191 1998

ISSN 1089-7798

This letter proposes a high-speed input and output buffering asynchronous transfer mode (ATM) switch, named the tandem-crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes, which are connected in tandem at every crosspoint. The TDXP switch does not increase the internal line speed in eliminating head-of-line (HOL) blocking. In addition, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. It is shown that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput.

Access to Document (DOI)

Advanced atm switching system hardware technologies based on mcm-d for atm line interface circuits

Kawamura Tomoaki, Yamanaka Naoaki, Kaizu Katsumi

IEICE Transactions on Communications E81-B ( 2 ) 482 - 487 1998

ISSN 0916-8516

This paper describes advanced ATM switching system hardware that uses a high-performance and cost-effective MCM-D module as an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size is reduced to 50.8mm x 50.8mm. This is 40% ofthat (100mm x 65mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a highperformance ASIC with a high-speed (access time 20ns) and large-capacity (l MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module is mounted on an ATM line interface circuit, and realizes 150 Mbit/s throughput ATM-layer functions (header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to advanced ATM switching systems.

Architectural choices in large scale ATM switches

Turner Jonathan, Yamanaka Naoaki

IEICE Transactions on Communications E81-B ( 2 ) 120 - 136 1998

ISSN 0916-8516

The rapid development of Asynchronous Transfer Mode technology in the last 10-15 years has stimulated renewed interest in the design and analysis of switching systems, leading to new ideas for system designs and new insights into the performance and evaluation of such systems. As ATM moves closer to realizing the vision of ubiquitous broadband ISDN services, the design of switching systems takes on growing importance. This paper seeks to clarify the key architectural issues for ATM switching system design and provides a survey of the current state-of-the-art.

Tb/s WDM interconnection system with pocket-size 10 Gb/s transmitter/receiver module and AWG router

Yasukawa S., Yamanaka N., Kawano R., Takeuchi H., Kuwano S.

575 - 576 1998

A Tb/s WDM interconnection system has been developed that utilizes a newly developed pocket-size 10-Gb/s transmitter/receiver module and wide-channel-spacing arrayed waveguide filter (AWGF). This system has 622-Mb/s ATM cell formats and can be applied to a Tb/s ATM switching system. The developed system uses eight different wavelength 10-Gb/s multiple quantum well modulator (MQW) integrated DFB lasers and one 8×8 optical router AWGF with 525-GHz-channel spacing. High-speed response and stable performance over a wide temperature range have been confirmed.

User-programmable flexible ATM network architecture, active-ATM

Yamanaka Naoaki, Oki Eiji, Hasegawa Haruhisa, Chen Thomas M.

IEICE Transactions on Communications E81-B ( 11 ) 2233 - 2236 1998

ISSN 0916-8516

This article proposes active-ATM, a flexible, simple and cost-effective ATM-WAN architecture that can handle multiple user-customized ATM-layer protocols, such as ABR and ABT, by using a simple universal ATM transit network. The proposed active-ATM architecture enables the construction of flexible networks that can evolve easily. With active-ATM and the ATM multi-protocol emulation network architecture called ALPEN, it is easy to implement new ATM-layer protocols by using user-created programs called active-program capsules that modify only the edge nodes. Because these user-sent program capsules can be used to quickly customize the edge nodes, there is no waiting for standardization and implementation of new services. The ATM-layer protocols are emulated only at the edge nodes, making the transit network independent of customer ATM-layer protocols. The active-ATM edge node is based on the flexible programmable node architecture called PUN (programmable unified node). The PUN is a platform for user-programmable ATM-layer services; it is achieved by using programmable devices, such as FPGAs and DSPs. An prototype system has demonstrated the flexibility of the resulting ATM network. The active-ATM architecture is an efficient approach to implementing multimedia, multi-protocol ATM services in an ATM WAN.

Impact of Multimedia Traffic Characteristics on ATM Network Configuration

Oki Eiji, Yamanaka Naoaki

Journal of Network and Systems Management 6 ( 4 ) 377 - 398 1998

ISSN 1064-7570

This paper proposes a new topological design method, named BXCQ, which optimizes logical network configuration while guaranteeing Quality-of-Service (QoS) requirements for each service class in an ATM network. The BXCQ method determines the optimum logical network topology associated with each service class so as to minimize network cost. In our previously proposed Full-Net architecture these different logical topologies can be suitably mapped at the same time on the same ATM physical network by using the Virtual Channel Handler (VCH) to create different logical interconnection networks. The BXCQ method allows us to clarify the relations between multimedia traffic characteristics and desirable logical network configurations in Full-Net. Evaluation results suggest that a service class that is bursty, delay tolerant, and cell loss sensitive with small demand should be supported by a loop-like topology. This study will be useful for designing flexible and cost-effective multimedia networks that can also adapt to not-yet-known services.

Flexible hardware design methodology for high-performance atm switching system using real-time emulation technique

Matsumura Tsuneo, Yamanaka Naoaki, Yamaguchi Ryoichi, Ishikawa Keiji

IEICE Transactions on Communications E81-B ( 2 ) 466 - 471 1998

ISSN 0916-8516

In the first stage of ATM switching system development, the specifications are sometimes changed in order to match revisions in ITU standards. Fatal problems due to specification changes and unexpected bugs force ASIC redesign and subsequent debugging is seriously restricted. These situations demand the introduction of new hardware design methodologies. This paper proposes a flexible hardware design methodology, based on a novel real-time emulation technique, suitable for large-scale high-speed communication switching systems. The emulation technique offers desirable system performance without Application Specific Integrated Circuit (ASIC) fabrication by using commercial Field Programmable Gate Arrays (FPGAs) along with many simply-structured high-speed interconnect switch devices for multiple FPGA connection. This technique suits line interface units (LUs) that have ASICs operating at about 20 MHz; each LU employs an LU board and emulation boards, both of which have hierarchical structures with sub-boards. The emulation boards are indispensable for realizing prototype systems rapidly and dealing with specification changes. Different types of LUs can be realized by mounting different sub-boards to the common LU board. Each emulation board is attached to the LU board by the same connector used for LU sub-board mounting. Therefore, the proposed structure has the advantage of utilizing a common LU board for system emulation as well as permitting the development of practical systems. To suppress undesirable multiple FPGA partitioning, we propose the emulation board architecture that has two types of sub-boards, each of which carries a different type of FPGA. We produced some portions of the proposed LU and tested the nearly 20 MHz real-time emulation of a complicated ASIC designed to realize ATM cell header conversion functions. The results of multiple FPGA partitioning on the emulation board suggest that the proposed design methodology will yield economic systems that can be freely modified to overcome hardware bugs and comply with future ITU standards.

High-speed connection admission control in ATM networks by generating virtual requests for connection

Oki Eiji, Yamanaka Naoaki

295 - 299 1998

This paper proposes a high-speed connection admission control scheme, named PERB CAC (CAC based on Prior Estimation for Residual Bandwidth). This scheme estimates the residual bandwidth in advance by generating a series of virtual requests for connection. When an actual connection request occurs, PERB CAC can instantaneously judge if the required bandwidth is larger than the estimated residual bandwidth, so the connection set-up time can be greatly reduced. Therefore, PERB CAC can realize high-speed connection set-up.

Access to Document (DOI)

A simple bandwidth management strategy based on measurements of instantaneous virtual path utilization in ATM networks

Shiomoto Kohei, Chaki Shinichiro, Yamanaka Naoaki

IEEE/ACM Transactions on Networking 6 ( 5 ) 625 - 634 1998

ISSN 1063-6692

A new connection admission control method based on actual virtual path traffic measurements is proposed to achieve high bandwidth efficiency for various types of traffic. The proposed method is based on the measurement of instantaneous virtual path utilization, which is defined as the total cell rate of the active virtual channels normalized by the virtual path capacity. A low-pass filter is used to determine the instantaneous virtual path utilization from crude measurements. A smoothing coefficient formula is derived as a function of peak rate of the virtual channel. The residual bandwidth is derived from the maximum instantaneous utilization observed during a monitoring period. Simulation shows that the proposed method achieves statistical multiplexing gains of up to 80% of the limit possible with optimum control for similar traffic sources. It can be implemented with very simple hardware. The admission decision is simple: the requested bandwidth is compared with the residual bandwidth. This method is therefore well suited for practical asynchronous transfer mode switching systems. © 1998 IEEE.

Access to Document (DOI)

DTM: Dynamic Transfer Mode Based on Dynamically Assigned Short-Hold Time-Slot Relay

Yamanaka Naoaki, Shiomoto Kohei

IEICE TRANSACTIONS on Communications E82-B ( 2 ) 375 - 380 1998

This paper proposes a new high-speed network architecture called Dynamic Transfer Mode, DTM. At the entrance of the DTM network, destination addresses such as IP addresses are converted into DTM routing information and attached to the packet header. In a DTM network, a connection is set up on-the-fly by sending a series of routing link identifiers to the destination, so burst data transfers like WWW traffic are efficiently carried. A connection between adjacent nodes is created and released dynamically within the burst transfer period. This yields higher statistical multiplexing gain and improved bandwidth efficiency compared to with conventional STM. Time division multiplexing is utilized so there is no delay jitter or cell loss, which are major drawbacks of Asynchronous Transfer Mode. This paper analyzes the performance of a DTM network and describes an implemented switching system. Because a DTM network uses source-routing and passive STM switching, it simplifies the core transit switch while localizing intelligence to edge nodes. A simplified core transit switch is well suited for future high-speed backbone networks.

Advanced ATM switching system hardware technology using MCM-D, stacking RAM micro-processor module

Yamanaka Naoaki, Kawamura Tomoaki, Kaizu Katsumi, Harada Akio

884 - 888 1998

This paper describes newly developed advanced ATM switching system hardware structures based on MCM-D micro-processor modules. The Si-Substrate MCM-D technology which integrates micro-processor, interface control and peripheral control custom VLSIs, high-speed S-RAMs, and FPGAs (Field Programmable Gate Arrays) is employed. An MCM-D micro-processor module is realized by combining a Motorola 68030, high-performance ASICs, and high-speed S-RAM caches. This is made possible by high density packaging and high-speed 4M-byte with parity cache using 25 ns access to 4-Mbit of S-RAM memory. The MCM employs 12 S-RAMs, possible with the stacked RAM technique, to reduce the module size by 7/8 compared to conventional surface mounting modules. This micro-processor module technology and MCM technology will advance the development of practical B-ISDN ATM switching systems.

Development of plastic chip scale package for ATM switching systems

Harada Akio, Kaizu Katsumi, Yamanaka Naoaki, Kawamura Tomoaki

30 - 35 1998

A plastic chip-scale package (CSP) smaller than conventional ones has been developed and applied to ATM switching systems. It uses a low-cost glass-epoxy substrate. Because glass epoxy is widely used in the printed circuit boards (PCBs) of ATM switching systems, its use in the CSPs mounted on a PCB reduces the difference in thermal expansion between the PCB and CSPs, thus lengthening CSP life. The power plane, ground plane, and thermal vias of the CSP are designed to offset the increased thermal resistance due to the CSP's smaller size. Simulation showed a thermal resistance for this CSP with copper layers and thermal vias of as much as 22% less than that of one with no copper layers or thermal vias. A six-layer test board mounting four CSPs was used to simulate a sub-board for ATM switching systems. The thermal resistance of the two CSPs located downstream was about 10% higher than that of the two located upstream. Two CSPs were developed for two types of application-specific ICs: a bus interface controller (BIC) and a peripheral interface circuit (PIC). Both CSPs were 18 mm square with a 0.8-mm outer solder-ball pitch and 256 outer balls. These CSPs occupied areas about 87% and 68% smaller than those of a conventional pin grid array (PGA) and quad flat package (QFP), respectively. The junction temperature of both CSPs satisfied the thermal condition. These high-performance CSPs are thus attractive for use in ATM switching systems.

A high-speed tandem-crosspoint ATM switch architecture with input and output buffers

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E81-B ( 2 ) 215 - 222 1998

ISSN 0916-8516

This paper proposes a high-speed input and output buffering ATM switch, named Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at every crosspoint. Even if a cell can not be transmitted to an output port on the first plane, it has a chance to be transmitted on the next plane. Cell transmission is executed on each switch plane in a pipeline manner. Therefore, more than one cell can be transmitted to the same output port within one cell time slot, although the internal line speed of each switch is equal to the input /output line speed. The TDXP switch architecture has several advantages in implementation. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require to rebuild the cell sequences at output buffers using time stamps, as is required by a parallel switch. These merits make implementing the high-speed ATM switch easy. Numerical results show that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput both for unicasting and multicasting traffic. This switch architecture is expected to enable the development of high-speed ATM switching systems that can realize over 1 Tb/s throughput in a cost-effective way.

A high-speed CAC scheme in ATM networks by using virtual requests for connection

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E81-B ( 10 ) 1927 - 1930 1998

ISSN 0916-8516

A new multiple QoS control scheme with equivalent-window CAC in ATM networks

Oki Eiji, Yamanaka Naoaki, Shiomoto Kohei, Moitra Soumyo D.

IEICE Transactions on Communications E81-B ( 7 ) 1462 - 1473 1998

ISSN 0916-8516

This paper proposes a multiple QoS control scheme that combines the head-of-line priority (HOLP) discipline with equivalent-window connection admission control (CAC). The proposed scheme can support the different cell loss ratios of both delay-sensitive traffic in high-priority buffers and delay-tolerant traffic in low-priority buffers. The CAC scheme extends a measurement-based CAC algorithm for a single buffer to the low-priority buffer with the HOLP discipline to provide the cell loss ratio objective. We introduce an equivalent window for monitoring low-priority cell streams. The equivalent window size equals the period within which the number of times the low-priority buffer is scanned to read cells is constant. Thus the equivalent window size varies with the high-priority queueing state. Numerical results indicate that the proposed QoS control scheme using the equivalent-window CAC can utilize network resources more effectively than the conventional control scheme which is Virtual Path (VP) separation for different cell loss requirement services. In addition, it is confirmed that the proposed scheme provides conservative admissible loads. Thus, this proposed scheme can achieve large statistical gains while providing both high-priority and low-priority cell loss ratio objectives. The proposed scheme will be very useful for cost-effective multimedia services that have different QoS requirements.

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