Details of a Researcher - Yamanaka, Naoaki

Papers - Yamanaka, Naoaki

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Experimental Evaluation on Priority-aware Guaranteed Resource Allocation for Resource Pool Based Reconfigurable Hardware

Masaki Murakami, Takashi Kurimoto, Satoru Okamoto, Naoaki Yamanaka

IEEE/ACM Transactions on Networking (TNET) 2024.02

Last author

Pod allocation algorithms to handle time-varying numbers of applications occurrence on the Access-Metro edge computing

Koki Muramatsu, Yoshihiko Uematsu, Satoru Okamoto, Naoaki Yamanaka

IEICE Communications Express 13 ( 2 ) 35 - 38 2024.02

Last author

AMec (Access-Metro edge computing) is a technology that can reduce the number of edge servers by utilizing in-network excess computing resources such as unallocated cores of control CPU of network devices as a node of the AMec cluster. The important issue is service interruption in that computing resources become unavailable due to executing their main job (e.g. device control and management jobs). In this paper, to avoid interruptions, two types of pod allocation algorithms (both static and dynamic thresholds) are evaluated. The dynamic threshold method is effective in keeping a high allocation success rate even for time-varying numbers of application occurrences.

Networking Experiment of Domain-Specific Networking Platform Based on Optically Interconnected Reconfigurable Communication Processors

Murakami M., Kurimoto T., Okamoto S., Yamanaka N., Muranaka T.

IEICE Transactions on Communications (IEICE Transactions on Communications) E106–B ( 8 ) 660 - 668 2023.08

ISSN 09168516

Access to Document (DOI)

Experimental Evaluation on Priority-Aware Guaranteed Resource Allocation for Resource Pool Based Reconfigurable Hardware

Murakami M., Kurimoto T., Okamoto S., Yamanaka N.

IEEE/ACM Transactions on Networking (IEEE/ACM Transactions on Networking) 32 ( 1 ) 298 - 307 2023

Joint Work, ISSN 10636692

This paper proposes a priority-aware guaranteed hardware resource allocation in virtual packet optical nodes (VPONs) and describes experimental evidence of service provisioning with the proposed method on testbed. A network based on the VPON brings solution of service diversification and traffic explosion because it provides multiple services by hardware level separated virtual networks such as IP/Ethernet/ Multi-Protocol Label Switching. The VPON has reconfigurable hardware which is dedicatedly allocated for each service and service-specific logical functions are implemented respectively. However, a previous hardware resource allocation method is not efficient. In previous work, the hardware resources once allocated to a service are not reallocated until the service terminated whenever the hardware is not optimally used. In recent years, hardware reconfiguration time has become shorter and it has enabled to apply for service demand change by releasing hardware from services with low demand and reallocating it to other services with high demand. Thus, this paper proposes preemptive dynamic hardware resource reallocation algorithm for VPON and a priority-aware guaranteed hardware resource reallocation method to realize efficient resource usage and high service capacity. Results of the computer simulation show improving service capability. Furthermore, to demonstrate the feasibility of service provisioning with the proposed method, emulators of the virtual packet optical node were constructed and performed resource reallocation. Results of the experiment show that the virtual packet optical node can configure function chains for providing services based on calculation results of the proposed resource reallocation method.

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Experiment of Nationwide Multi-Route Skew Cancelling for Dynamic Mapping of MAC Signals over SDM/WDM Network Testbed

Murakami M., Uematsu Y., Okamoto S., Yamanaka N., Soma D., Beppu S., Yoshikane N., Tsuritani T., Kodama T., Jinno M.

OECC/PSC 2022 - 27th OptoElectronics and Communications Conference/International Conference on Photonics in Switching and Computing 2022 (OECC/PSC 2022 - 27th OptoElectronics and Communications Conference/International Conference on Photonics in Switching and Computing 2022) 2022

Research paper (international conference proceedings), Joint Work

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Beyond 5G時代のネットワークビジョン -2030年に向けたアーキテクチャとブレークスルー技術の鳥瞰-

山中直明, 西村光弘, 石黒正揮, 岡崎義勝, 川西哲也, 釣谷剛宏, 中尾彰宏, 原井洋明, 廣岡俊彦, 古川英昭, 宮澤雅典, 山本直克, 吉野修一

電子情報通信学会和文論文誌B B, Vol. J104-B ( No. 3 ) 315 - 336 2021.03

Joint Work

Kalman filter-based heavy hadoop job detection method for energy efficient hybrid electro-optical intra-data center networks

Murakami M., Dubrana N., Uematsu Y., Okamoto S., Yamanaka N.

Optics InfoBase Conference Papers (Optics InfoBase Conference Papers) 2021

Joint Work

Deep programmable network architecture having URLLC-link for highly secure and manageable network

Naoaki Yamanaka, Satoru Okamoto, Takayuki Muranaka, Andrea Fumagalli

22nd Annual Conferece Net-Centric (Net-Centric 2020) Th2-1 2020.12

Research paper (international conference proceedings), Joint Work

Online parameter tuning of the flow classification method in the energy-efficient data center network HOLST

Murakami M., Kubokawa H., Sugiura K., Oki E., Okamoto S., Yamanaka N.

Journal of Optical Communications and Networking (Journal of Optical Communications and Networking) 12 ( 11 ) 344 - 354 2020.11

Joint Work, ISSN 19430620

An online parameter-tuning method for the energy-efficient data center network (DCN) named HOLST (high-speed optical layer 1 switch system for time-slot-switching-based optical data center networks) is proposed. HOLST comprises an optical circuit switching network, optical slot switching network, and electrical packet switching network for the spine layer. It requires flows to be assigned to optimal switches to achieve high power savings. In this study, first we experimentally confirm that the change in the DCN characteristics in the short term of actual data center traffic downgrades the accuracy of flow classification. Subsequently, we propose a procedure for reconfiguring a flow classification function and a method for online parameter tuning for this function. Finally, the accuracy of the flow classification method using the proposed tuning and estimated switching energy consumption in the spine layer are evaluated. The proposed online parameter-tuning function increases the accuracy of flow classification and reduces switching energy consumption relative to the conventional flow classification function.

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Cyber-physical system for autonomous driving vehicle considering with social welfare

Yamanaka N., Yamamoto G., Okamoto S., Fumagalli A.

International Conference on Transparent Optical Networks (International Conference on Transparent Optical Networks) 2020-July 2020.07

Research paper (international conference proceedings), Joint Work, ISSN 2161-2064

Autonomous driving vehicle control network by edge computer having very short response time has been constructed. Each vehicle has an agent program on the edge and communicated with adjacent vehicle agent in the cyber network. The advantage of connected vehicle control from stand-alone vehicle is sophisticated and total/ global optimizing control. The network edge computer calculated 'social welfare' which is the best benefit for all vehicle in the society. This paper describes control architecture and method at edge computer. In addition, some experimental results for controlling autonomous vehicle are also described.

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Experience with a Trans-Pacific Collaborative Mixed Reality Plant Walk

Vellingiri S., White-Swift J., Vania G., Dourty B., Okamoto S., Yamanaka N., Prabhakaran B.

Proceedings - 2020 IEEE Conference on Virtual Reality and 3D User Interfaces, VRW 2020 (Proceedings - 2020 IEEE Conference on Virtual Reality and 3D User Interfaces, VRW 2020) 238 - 245 2020.03

Research paper (international conference proceedings), Joint Work

In this paper, we share our experiences with a Trans-Pacific, collaborative mixed-reality (MR) based plant walk tour involving three geographical locations: (i) Dallas, Texas; (ii) Denver, Colorado; and (iii) Yokohama, Japan. The Wide Area Network (WAN) from Japan to Denver and from Denver to Dallas was through 100 Gbps optical links. These links were a mixture of leased and dedicated infrastructure. The average observed latency was around 131 ms and the maximum available bandwidth was 26.6 Gbps. The tour developed using a component-based framework, provided group travel with a leader-follower criterion involving a semi-active travel technique. By applying a 'modified Virtual Reality' (mVR) triangle paradigm, we examined the user experience of this collaborative tour. We considered Visualization, Synchronization, and Exploration design choices as the three key aspects of the mVR triangle. We assessed the user experience of the tour through a Gibbs triangle, with each of the composition of the Gibbs triangle being a key aspect of the mVR triangle. We obtained users' scores on the three aspects of the mVR using a seven-point, Likert scale questionnaire. We conducted 14 sessions of group travel. Overall, we found the user experience of the trans-pacific plant walk tour to be in the Balanced Experience Region (BER) region or the center part of the Gibbs triangle, which conveys that the majority of the participants experienced a balanced influence of mVR aspects throughout the tour.

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Autonomous driving vehicle controlling network using dynamic migrated edge computer function

Yamanaka N., Yamamoto G., Okamoto S., Muranaka T., Fumagalli A.

International Conference on Transparent Optical Networks (International Conference on Transparent Optical Networks) 2019-July 2019.07

Research paper (international conference proceedings)

Autonomous driving vehicle control by edge computer network having very short response time has been proposed. Each vehicle has an agent program on the edge and automatically moved to adjacent edge computer following to the vehicle movement. On the edge computer, the agent program is processing with other vehicles' agents in a cyber network. We employ triple redundancy and majority rule to achieve high-reliability and less than 10 ms control latency try to be guaranteed. In addition, each vehicle has an IoT sensor including fine-GPS, so all precious position and speed of the vehicle can be monitored. We constructed the autonomous driving experimental course, the autonomous driving vehicle, and the edge computer system with the center cloud and tested in the campus test bed. According to the vehicle movement, network orchestrator setup a new optical path automatically and send the agent program to the adjacent target edge computer. This orchestration function is newly proposed application triggered dynamic optical network. In this presentation, I will show the detailed experimental results. This architecture and experimental results can be applied to the future smart and connected community.

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Experimental Evaluation of Application Triggered Flow Classification Using Operated Data Center Traffic Data

Murakami M., Matsuno M., Okamoto S., Yamanaka N.

OECC/PSC 2019 - 24th OptoElectronics and Communications Conference/International Conference Photonics in Switching and Computing 2019 (OECC/PSC 2019 - 24th OptoElectronics and Communications Conference/International Conference Photonics in Switching and Computing 2019) 2019.07

Research paper (international conference proceedings), Joint Work

Access to Document (DOI)

Experimental Deployment of Dynamic Resource Allocation Using Biological Attractor Selection in Virtual Packet Optical Node

Hara C., Murakami M., Okamoto S., Yamanaka N.

Research paper (international conference proceedings), Joint Work

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Expected Capacity Guaranteed Routing based on Dynamic Link Failure Prediction

Sekigawa S., Okamoto S., Yamanaka N., Oki E.

2019 International Conference on Computing, Networking and Communications, ICNC 2019 (2019 International Conference on Computing, Networking and Communications, ICNC 2019) 170 - 174 2019.04

Research paper (international conference proceedings), Joint Work

In a high-speed backbone network, the failure of network links may cause large data losses, so it is necessary to reserve spare network resources for faster recovery. The conventional protection methods that reserve backup paths do not consider the failure probability of each network link and allocate same amount of network resources for the backup paths regardless of the failure rate of network links. This leads to the excessive or insufficient capacity allocation. This paper proposes the routing method that guarantees the expected value of the allocated capacity based on dynamically changed link failure rate. We formulate a Mixed Integer Liner Programming (MILP) model for the proposed method. We conduct simulations to investigate the effect of the expected capacity guaranteed routing over the conventional routing method in terms of bandwidth blocking probability, transmitted capacity achieved ratio, and the ratio of total transmitted capacity to total requested capacity. The results show that our proposed method marks higher transmitted capacity achieved ratio compared to conventional routing methods. We also find the transmitted capacity achieved ratio of the proposed method maintains 90% under high failure rate.

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A Span Power Management Scheme for Rapid Lightpath Provisioning and Releasing in Multi-Core Fiber Networks

Chatterjee B.C., He F., Oki E., Fumagalli A., Yamanaka N.

IEEE/ACM Transactions on Networking (IEEE/ACM Transactions on Networking) 27 ( 2 ) 734 - 747 2019.04

Joint Work, ISSN 10636692

The lightpath provisioning time or releasing time is adversely affected by the time that optical amplifiers require to adjust to a newly added or terminated signal power. This shortcoming is particularly true with multi-core erbium-doped amplifiers (EDFAs), as multi-core transient-suppressed EDFAs are unavailable at the current time. This paper proposes a fiber span power management scheme based on dummy wavelength signals that are used to shorten the lightpath provisioning and releasing times in multi-core fiber networks. With the shorter time of lightpath provisioning and releasing procedures, the total time that is required to reserve wavelengths in the system is decreased, which means that network resources are used more efficiently. As a result, the blocking performance and average waiting time in the system are improved. To evaluate the performance of the proposed scheme, this paper introduces both analytical model and simulation study. In the introduced model, the ratio of the number of activating and activated dummy wavelengths to the number of dummy wavelengths in each span is considered in the range between 0 and 1. The analysis reveals that the performance of the proposed scheme depends on \alpha , which is the ratio of the number of dummy wavelengths to the number of dummy and lightpath wavelengths in each span, and there exists a point of \alpha where the blocking probability becomes minimum. We further observe that the proposed scheme outperforms the conventional approaches in terms of blocking probability and average waiting time, as traffic loads increase. Finally, we provide the direction on how our introduced model can be considered for a network with multi-span routes.

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Designing a Hadoop system based on computational resources and network delay for wide area networks

Matsuno T., Chatterjee B., Kitsuwan N., Oki E., Veeraraghavan M., Okamoto S., Yamanaka N.

Telecommunication Systems (Telecommunication Systems) 70 ( 1 ) 13 - 25 2019.01

Joint Work, ISSN 10184864

This paper proposes a Hadoop system that considers both slave server’s processing capacity and network delay for wide area networks to reduce the job processing time. The task allocation scheme in the proposed Hadoop system divides each individual job into multiple tasks using suitable splitting ratios and then allocates the tasks to different slaves according to the computational capability of each server and the availability of network resources. We incorporate software-defined networking to the proposed Hadoop system to manage path computation elements and network resources. The performance of proposed Hadoop system is experimentally evaluated with fourteen machines located in the different parts of the globe using a scale-out approach. A scale-out experiment using the proposed and conventional Hadoop systems is conducted by executing both single job and multiple jobs. The practical testbed and simulation results indicate that the proposed Hadoop system is effective compared to the conventional Hadoop system in terms of processing time.

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Biological attractor selection and SDN control interworking in the virtual packet optical node network control

Hara C., Yarita K., Okamoto S., Yamanaka N.

Proceeding on 2019 Optical Fiber Communication, OFC2019, Session160 (Optics InfoBase Conference Papers) Part F160-OFC 2019 2019

Research paper (international conference proceedings), Joint Work

Modeling the effect of wavelength selective switch latency on optical flow switching performance

Shakeri A., Wang X., Razo M., Alabarce M., Oki E., Yamanaka N., Fumagalli A.

Journal of Optical Communications and Networking (Journal of Optical Communications and Networking) 10 ( 12 ) 924 - 935 2018.12

Joint Work, ISSN 19430620

Optical networks are well suited to enable massive data exchanges between datacenters. Elephant data flows can be routed over custom provisioned and dedicated lightpaths (optical flows) while other (mice) flows, which are routed by electronic switches, are unaffected. In some solutions, wavelength-selective switch (WSS) devices are employed in the optical nodes to physically and individually route each lightpath toward its destination. WSS devices take time to be switched and consequently delay the lightpath setup completion time. In this paper, the authors present three approximate Markov chain models to account for three different WSS service policies. These models estimate the expected lightpath setup and teardown time across an optical node that makes use of WSS devices. The first and more conventional policy (model) assumes that each setup and teardown request is handled individually, while the other two policies (models) assume that groups of setup and/or teardown requests are handled together by the WSS. The models' estimates are compared against the results obtained from a computer-based simulator, where both analytical models and simulator account for experimentally measured WSS response times. The simulator is also used to investigate the end-to-end lightpath setup time across an arbitrary mesh network. Results obtained from the models and simulator show that the group-based service policies outperform the conventional policy at high loads. The group-based policies are especially useful in the presence of lightpaths that are frequently set up and have relatively short holding time (i.e., short duration of elephant-optical flows).

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Experimental Demonstration of Disaggregated Emergency Optical System for Quick Disaster Recovery

Shiraiwa M., Yoshikane N., Xu S., Tsuritani T., Miyata N., Mori T., Miyabe M., Katagiri T., Yoshida S., Tanaka M., Hayashi T., Sugiyama H., Satou I., Mikuni M., Okamoto S., Yamanaka N., Jeong B., Awaji Y., Wada N.

Journal of Lightwave Technology (Journal of Lightwave Technology) 36 ( 15 ) 3083 - 3096 2018.08

Joint Work, ISSN 07338724

Disaggregation and white-box approaches are useful in expediting disaster recovery of optical transport networks. When an optical network system is damaged by a large disaster, the damaged devices can be replaced by the disaggregated functional devices, while disregarding vendor boundaries. In the light of the disaggregation and white-box approaches, we are developing a prototype of disaggregated portable emergency optical system (EOS) for early and low-cost postdisaster recovery. The EOS is customizable, and different functions can be selected to meet the different requirements in disaster recovery. In addition to replacing the damaged functions of the original optical system with an EOS, we introduce two new disaggregated functions into the EOS for postdisaster recovery. First, we introduce an optical supervisory channel handshake scheme to aid the interconnection of the surviving optical resources. Second, we introduce a scheme to achieve the quick recovery of the damaged control plane with the surviving or first restored wireless access capability. This is highly desired not only for emergency network control, but also for the quick collection of the network damage information. These two new functions have been implemented into the EOS prototype. We experimentally demonstrated the network recovery of the data-plane and the control-plane with the EOS.

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Delivery Management System Based on Vehicles Monitoring and a Machine-Learning Mechanism

Habault G., Taniguchi Y., Yamanaka N.

IEEE Vehicular Technology Conference (IEEE Vehicular Technology Conference) 2018-August 2018.07

Joint Work

The continuously growing online shopping is increasing the number of attended home deliveries. The last-mile delivery plays an important role in online shopping satisfaction and especially for food deliveries. This paper focuses on food delivery retailers and particularly investigates the possibility to enhance deliveries using information and data knowledge. In fact, in addition to optimize and to share delivery routes, delivery vehicles could be monitored in order to always maintain shortest delivery delays. We propose in this paper a delivery management architecture targeting these principles. This system is composed of several core mechanisms that should keep delivery delays to a minimum while maintaining low service times. A proof-of-concept of this delivery management system has been developed using Electric Scooters, smartphones and several algorithms. It demonstrates how this architecture could work in a food delivery scenario.

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Application-triggered automatic distributed cloud/network resource coordination by optically networked inter/intra data center [invited]

Yamanaka N., Okamoto S., Hirono M., Imakiire Y., Muro W., Sato T., Oki E., Fumagalli A., Veeraraghavan M.

Journal of Optical Communications and Networking (Journal of Optical Communications and Networking) 10 ( 7 ) B15 - B24 2018.07

Research paper (international conference proceedings), Joint Work, ISSN 19430620

Everything is being connected to the Cloud and Internet of Things, and network robots with big data analy- sis are creating important applications and services. The cloud network architecture is moving towards mega-cloud data centers (DCs) provided by companies such as Amazon and Google in combination with distributed small DCs or edge computers. While the traditional restrictions im- posed by distance and bandwidth are being overcome by the development of advanced optical interconnection, modern applications impose more complex performance and quality of service requirements in terms of processing power, response time, and data amount. The rise in cloud perfor- mance must be matched by improvements in network per- formance. Therefore, we propose an application-triggered cloud network architecture based on huge-bandwidth optical interconnections. This paper addresses edge/center cloud and edge/edge integration with the use of virtual ma- chine migration. In addition, to reduce energy consumption, an application-triggered intra-DC architecture is described. Using the proposed architectures and technologies can real- ize energy-efficient and high-performance cloud service.

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Dynamic energy efficient virtual link resource reallocation approach for network virtualization environment

Zhang S., Sato T., Okamoto S., Yamanaka N.

IEICE Transactions on Communications (IEICE Transactions on Communications) E101B ( 7 ) 1675 - 1684 2018.07

Joint Work, ISSN 09168516

The energy consumption of network virtualization environments (NVEs) has become a critical issue. In this paper, we focus on reducing the data switching energy consumption of NVE. We first analyze the data switching energy of NVE. Then, we propose a dynamic energy efficient virtual link resource reallocation (eEVLRR) approach for NVE. eEVLRR dynamically reallocates the energy efficient substrate resources (sresources) for virtual links with dynamic changes of embeddable s-resources to save the data switching energy. In order to avoid traffic interruptions while reallocating, we design a cross layer application-session-based forwarding model for eEVLRR that can identify and forward each data transmission flow along the initial specified substrate data transport path until end without traffic interruptions. The results of performance evaluations show that eEVLRR not only guarantees the allocated s-resources of virtual links are continuously energy efficient to save data switching energy but also has positive impacts on virtual network acceptance rate, revenues and s-resources utilization.

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First experimental demonstration of disaggregated emergency optical system for quick disaster recovery

2018 Optical Fiber Communications Conference and Exposition, OFC 2018 - Proceedings (2018 Optical Fiber Communications Conference and Exposition, OFC 2018 - Proceedings) 1 - 3 2018.06

Research paper (international conference proceedings), Joint Work

Flow/application triggered SDN control in hybrid data-center network 'HOLST'

Imakiire Y., Hirono M., Murakami M., Okamoto S., Yamanaka N.

2018 Optical Fiber Communications Conference and Exposition, OFC 2018 - Proceedings (2018 Optical Fiber Communications Conference and Exposition, OFC 2018 - Proceedings) 1 - 2 2018.06

Joint Work, ISSN 9781943580385

Novel Automatic Service Restoration Technique by Using Self-Reconfiguration of Network Resources for a Disaster-struck Metro-Access Network

Kanai T., Senoo Y., Asaka K., Sugawa J., Tamai H., Saito H., Minato N., Oguri A., Sumita S., Sato T., Kikuchi N., Matsushita S., Tsuritani T., Okamoto S., Yamanaka N., Suzuki K., Otaka A.

Journal of Lightwave Technology (Journal of Lightwave Technology) 36 ( 8 ) 1516 - 1523 2018.04

Joint Work, ISSN 07338724

This paper shows the concept of the elastic lambda aggregation network (EλAN) that will achieve an elastic common access infrastructure for the metro-access network. It proposes a service restoration technique that uses optical path switching and intercentral office handover for EλAN to recover from disasters. The feasibility of the proposed service restoration technique is successfully demonstrated for the first time by using a prototype testbed of a metro-access network. By applying both orthogonal frequency division multiplexing and adaptive modulation, the system automatically changes the transmission parameters (modulation level, the number of subcarriers, and symbol rate) according to the service requirements and conditions of the optical distribution network, such as the link's end-to-end optical loss, in order to achieve accommodate multiple services. In the experiment, an optical network unit in a faulted system automatically reconnected within 10 s to another office 20-km away with the same throughput.

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SDN-enabled headroom services for high-speed data transfers

Alali F., Lin X., Veeraraghavan M., Yamanaka N., Sun W.

2017 23rd Asia-Pacific Conference on Communications: Bridging the Metropolitan and the Remote, APCC 2017 (2017 23rd Asia-Pacific Conference on Communications: Bridging the Metropolitan and the Remote, APCC 2017) 2018-January 1 - 6 2018.02

Research paper (international conference proceedings), Joint Work

WAN provider links are often operated at low utilization levels, which leaves large unused capacity (headroom). In this paper, we propose using Software Defined Networking (SDN) controllers to support novel Static Headroom (SH) and Dynamic Headroom (DH) services to allow customers to fill this headroom with Elephant Flows (EFs) without adversely affecting the provider's ability to meet its Best-Effort (BE) service-level agreements, and ability to absorb extra traffic load created during failure recovery periods. Our solution calls for the use of lower-priority service for EFs. We use simulations to compare SH service with BE service, and DH service with SH service. When EFs are sent on BE service, they could cause packet losses in general-purpose IP traffic, especially when the burstiness of the latter is high, while with SH service, this packet loss rate is reduced to 0. While DH service requires the added complexity of a provider SDN controller, the ability to dynamically route EFs on lower-utilized links results in higher average EF throughput. The higher the non-uniformity (from a node-pair perspective) in network traffic, the greater the DH gain factor.

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First experimental demonstration of disaggregated emergency optical system for Quick Disaster Recovery

Proceeding on Optical Fiber Communication, OFC2018, Part F84 (Optics InfoBase Conference Papers) Part F84-OFC 2018 2018

Research paper (international conference proceedings), Joint Work

Access to Document (DOI)

Flow/application triggered SDN control in hybrid datacenter network “HOLST“

Imakiire Y., Hirono M., Murakami M., Okamoto S., Yamanaka N.

Proceeding on Optical Fiber Communication, OFC2018, Part F84 (Optics InfoBase Conference Papers) Part F84-OFC 2018 2018

Research paper (international conference proceedings), Joint Work

Access to Document (DOI)

Network Function Virtualization: A Survey

Malathi VEERARAGHAVAN, Takehiro SATO, Molly BUCHANAN, Reza RAHIMI, Satoru OKAMOTO, YAMANAKA NAOAKI

IEICE Transactions on Communications B E100-B ( 11 ) 1978 - 1991 2017.11

Research paper (scientific journal), Joint Work

High-Speed Packet Networking Technologies

YAMANAKA NAOAKI, Eiji OKI

The IEICE Transactions on Communications (Japanese Edition) J100-B ( 9 ) 611 - 625 2017.09

Research paper (scientific journal), Joint Work

Experimental evaluation of fault recovery methods in Elastic Lambda Aggregation Network

Takehiro Sato, Yoshihiro Isaji, Yusuke Nakajima, Satoru Okamoto, Naoaki Yamanaka

IEICE Communications Express (ComEX) 6 ( 9 ) 507 - 512 2017.09

Research paper (scientific journal), Joint Work

Optical Networking Paradigm: Past, Recent Trends and Future Directions

Eiji Oki, Naoya Wada, Satoru Okamoto, YAMANAKA NAOAKI, Kenichi Sato

IEICE Transactions on Communications B E100-B ( 9 ) 1564 - 1580 2017.09

Research paper (scientific journal), Joint Work

Software defined networking (SDN) and OpenFlow, which enables the abstraction of vendor/technology-specific attributes, improve the network control and management flexibility of optical transport networks. In this paper, we present an interoperability demonstration of SDN/OpenFlow-based optical path control for multi-domain/multi-technology optical transport networks. We also summarize the abstraction approaches proposed for multi-technology network integration at an SDN controller.

Optical Ad Hoc Networking for Optical Metro/Access Integrated Network

Yoshihiro ISAJI, Takehiro SATO, Satoru OKAMOTO, YAMANAKA NAOAKI, Eiji OKI

The IEICE Transactions on Communications (Japanese Edition) J100-B ( 7 ) 469 - 479 2017.07

Research paper (scientific journal), Joint Work

Adaptive Elastic Spectrum Allocation Based on Traffic Fluctuation Estimate under Time-Varying Traffic in Flexible OFDM-based Optical Networks

Mirai CHINO, Misato KAMIO, Jun MATSUMOTO, Eiji OKI, Satoru OKAMOTO, YAMANAKA NAOAKI

IEICE Transactions on Communications B E100-B ( 6 ) 962 - 973 2017.06

Research paper (scientific journal), Joint Work

Highlights from IEEE HPSR 2016 17th International Conference on High Performance switching and Routing

YAMANAKA NAOAKI, Eiji Oki

IEICE Communication Society -GLOBAL NEWSLETTER 40 ( 4 ) 21 - 23 2016.12

Research paper (scientific journal), Joint Work

Demonstration of SDN/OpenFlow-based Path Control for Large-Scale Multi-Domain/Multi-Technology Optical Transport Networks

Shan Gao, Xiaoyuan Cao, Takehiro Sato, Takaya Miyazawa, Sota Yoshida, Noboru Yoshikane, Hiroaki Harai, Satoru Okamoto, YAMANAKA NAOAKI

IEICE Transactions on Communications B E99-B ( 7 ) 1492 - 1500 2016.07

Research paper (scientific journal), Joint Work

Route Partitioning Scheme for Elastic Optical Networks with Hitless Defragmentation

Seydou Ba, Bijoy Chand Chatterjee, Satoru Okamoto, YAMANAKA NAOAKI, Andrea Fumagalli, Eiji Oki

Journal of Optical Communications and Networking (JOCN) 8 ( 6 ) 356 - 370 2016.06

Research paper (scientific journal), Joint Work

Hitless defragmentation has been introduced as an approach to limit the spectrum fragmentation in elastic optical networks without traffic disruption. It facilitates the accommodation of new request by creating large spectrum blocks, as it moves active lightpaths (retuning) to fill in gaps left in the spectrum by expired ones. Nevertheless, hitless defragmentation witnesses limitations for gradual retuning with the conventionally used first fit allocation. The first fit allocation stacks all lightpaths to the lower end of the spectrum. This leads to a large number of lightpaths that need to be retuned and are subject to interfere with each other’s retuning. This paper proposes a route partitioning scheme for hitless defragmentation in order to increase the admissible traffic in elastic optical networks. The proposed scheme uses route partitioning with the first-last fit allocation to increase the possibilities of lightpath retuning by avoiding the retuning interference among lightpaths. The first-last fit allocation is used to set a bipartition with one partition allocated with the first fit and the second with the last fit. Lightpaths that are allocated on different partitions cannot interfere with each other. Thus the route partitioning avoids the interferences among lightpaths when retuning. We define the route partitioning problem as an optimization problem to minimize the total interferences. We then introduce an integer linear programming problem (ILP) that yields an optimal routing and partitioning. We prove that the route partitioning problem is NP-hard. We present a heuristic algorithm for large networks, where the ILP to represent the route partitioning is not tractable. The simulation results show that the proposed route partitioning scheme using first-last fit outperforms the conventional first fit allocation for hitless defragmentation in term of allowable traffic.

Control Scheme of HOPR-Based Data Centetr Network by Considering VM Situation

Masahiro HAYASHITANI, Kazuya SUZUKI, YAMANAKA NAOAKI

The IEICE Transactions on Communications (Japanese Edition) J99-B ( 4 ) 334 - 344 2016.04

Research paper (scientific journal), Joint Work

TDMA-based OLT Virtualization for ONU Connection Retention in Elastic Lambda Aggregation Network

Takehiro Sato, Asato Kotsugai, Hidetoshi Takeshita, Satoru Okamoto, NAOAKI YAMANAKA, Eiji Oki

The IEICE Transactions on Communications (Japanese Edition) J99-B ( 3 ) 206 - 218 2016.03

Research paper (scientific journal), Joint Work

Elastic Lambda Aggregation Network (EλAN) is expected to maintain the connectivity between Optical Line Terminal (OLT) and Optical Network Units (ONU) by using reconfigurable Active Optical Distribution Network (ODN) in the case of huge network failure. However, when surviving OLTs are very limited, limited number of ONUs can be accommodated even if restoration paths are available. In this paper, we propose a novel recovery method to maintain the connectivity of a large number of ONUs by virtualizing OLT and switching ONU groups using TDMA. In the proposed method, the effect of large communication intervals on the quality of services is alleviated by inserting a proxy. Numerical results showed that the connectivity of more ONUs can be maintained by using the proposed method compared to the restoration method. We also observed that the insertion of the proxy prevents UDP packet loss and improves TCP throughput by 9.8 Mbps at a maximum by the experiment using the EλAN prototype system.

Time estimation of logical optical line terminal migration for Elastic Lambda Aggregation Network

Yoshihiro Isaji, Takehiro Sato, Hidetoshi Takeshita, Satoru Okamoto, Naoaki Yamanaka

IEICE Communications Express (ComEX) 5 ( 3 ) 79 - 84 2016.03

Research paper (scientific journal), Joint Work

Elastic Lambda Aggregation Network (EλAN), the next-generation access and aggregation integrated network, has been proposed. In EλAN, Optical Line Terminals (OLTs) are programmable, and Logical-OLTs (L-OLTs) can be migrated between different P-OLTs. L-OLT migration leads to enhance failure resistance and improve power saving. We have experimented L-OLT migration between P-OLTs in our laboratory. However it is necessary to evaluate how L-OLT migration time changes according to physical distance. Therefore we made an experiment of L-OLT migration in wide area network on JGN-X. This paper proposes estimation equation of L-OLT migration time. The equation leads to determine L-OLT arrangements considering time of L-OLT migration for physical distance.

Energy Efficient Data-centric Networking System on JGN-X Network Virtualization Platform

Satoru Okamoto, Daisuke Matsubara,Naoaki Yamanaka

Journal of the National Institute of Information and Communications Technology 62 ( 2 ) 93 - 100 2016.02

Research paper (scientific journal), Joint Work

In the new generation network, information-centric networking (ICN) is one of the most promising technologies for communication systems which are suitable for the content data provisioning and delivery from/to users. To create a new ICN on the JGN-X network virtualization platform, developing new networking technologies such as virtual network resources control from users, in-network processing for content data creation, and energy efficient routing on the virtual network, were challenged.

Logical Optical Line Terminal Placement Optimization in the Elastic Lambda Aggregation Network With Optical Distribution Network Constraints

Takehiro Sato, Kunitaka Ashizawa, Hidetoshi Takeshita, Satoru Okamoto, Naoaki Yamanaka, Eiji Oki

IEEE/OSA Journal of Optical Communications and Networking (JOCN) 7 ( 9 ) 928 - 941 2015.09

Research paper (scientific journal), Joint Work

The elastic lambda aggregation network (EλAN) has been presented as an access/aggregation integrated network that can accommodate multiple network services. In the EλAN, optical line terminals (OLTs) become programmable and configure logical OLTs (L-OLTs) to support network services that have different protocols and quality of service requirements. To achieve the flexible utilization of network resources and improve energy efficiency, L-OLTs are migrated between programmable OLTs like virtual machines. In this paper, an integer linear programming (ILP) model of the L-OLT placement optimization problem with optical distribution network constraints is presented. Based on this ILP model, the communication suspension time that occurs with L-OLT migration is investigated. We discuss the modification of the L-OLT migration sequence to reduce the communication suspension time. The impact of the modification on the energy saving effect of L-OLT placement optimization is evaluated in this paper.

Application-Centric, Energy-Efficient Network Architecture, ACTION, Based on Virtual Optical Slice Core and Deterministic Optical Access Network

Kunitaka Ashizawa, Satoru Okamoto, Naoaki Yamanaka, Eiji Oki, Andrea Fumagalli, Malathi Veeraraghavan

OSA Journal of the Optical Society of Korea (JOSK) 19 ( 4 ) 340 - 345 2015.08

Research paper (scientific journal), Joint Work

Delay-sensitive slot allocation method minimizing switching idle time in PLZT optical switch for active optical access network

Kunitaka Ashizawa, Takehiro Sato, Hidetoshi Takeshita, Satoru Okamoto, Naoaki Yamanaka, Eiji Oki, Andrea Fumagalli, Malathi Veeraraghavan

IEICE Communications Express (ComEX) 4 ( 6 ) 217 - 222 2015.07

Research paper (scientific journal), Joint Work

Active Optical Network (ActiON) using a conventional slot allocation method in Plumbum Lanthanum Zirconate Titanate (PLZT) optical switches was proposed. The conventional slot allocation method shortens the switching idle time, which is a product of the switching guard time and the number of switching times. However, the transmission waiting time could exceed a user’s allowable delay. This paper proposes a delay-sensitive slot allocation method, which minimizes the switching idle time while considering the user’s allowable delay. Numerical results show that the proposed method reduces the number of switching times by up to 88 percent when compared to the conventional method.

Application Centric Energy Efficient Ethernet with Quality of Service Support

Ion Popescu, Takahiro Miyazaki, Mirai Chino, Xiaoyu Wang, Satoru Okamoto, Annie Gravey, Philippe Gravey, Malathi Veeraraghavan, Maite Brandt-Pearce, Naoaki Yamanaka

IEE Electronics Letters 51 ( 15 ) 1165 - 1167 2015.07

Research paper (scientific journal), Joint Work

Energy Efficient and Enhanced-type Data-centric Network Architecture

Shanming Zhang, Hidetoshi Takeshita, Satoru Okamoto, Naoaki Yamanaka

International Journal of Computer & Information Science (IJCIS) 16 ( 1 ) 60 - 70 2015.03

Research paper (scientific journal), Joint Work

Information-centric networking (ICN) as an alternative has been researched for future Internet architecture. In this paper, a novel network architecture called Energy Efficient and Enhanced-type Data-centric Network (E3-DCN) is proposed for ICN. E3-DCN not only realizes ICN but also has the ability of data generation by organizing and combining relevant resource such as original data and kinds of processing services. In addition, in order to improve energy efficiency of data transmission, E3-DCN chooses optimal transmission path to transmit data based on packet switching and optical switching. Moreover, based on current traffic situation, E3-DCN reconfigures network topology such as unused nodes and links to operate in sleep mode for energy saving dynamically. And meanwhile, data caching strategies are applied into E3-DCN for data distribution based on the distribution of users. Data caching shortens transmission distance, so data transmission energy, latency and network load is decreased. Based on these approaches, E3-DCN achieves an energy efficient network.

Overview of the 10th International Conference on IP+Optical Network (iPOP2014)

NAOAKI YAMANAKA, Satoru Okamoto, Atsushi Hiramatsu

NewBreeze 27 ( 1 ) 4-5 2015.01

Research paper (scientific journal), Joint Work

Span Power Management Scheme for Rapid Lightpath Provisioning in Multi-Core Fiber Networks

Bijoy Chand Chatterjee, Yamini Jayabal,NAOAKI YAMANAKA, Satoru Okamoto, Andrea Fumagalli, Eiji Oki

IEE Electronics Letters 51 ( 1 ) 76 - 78 2015.01

Research paper (scientific journal), Joint Work

The activation time when creating lightpaths is adversely affected by the time optical amplifiers, which are required to adjust the newly added signal power. This shortcoming is particularly true with multicore erbium-doped amplifiers. A fibre span power management scheme is proposed based on the use of dummy wavelength signals, whose function is to alleviate this shortcoming and shorten the required lightpath activation time. An analytical model is developed to estimate the effectiveness of the proposed scheme in achieving this goal.

Photonic Network Vision 2020 - Toward Smart Photonic Cloud

Ken-ichi Kitayama, Atsushi Hiramatsu, Masaki Fukui, Takehiro Tsuritani, YAMANAKA NAOAKI, Satoru Okamoto, Masahiko Jinno, Masafumi Koga

IEEE Journal of Lightwave Technology (JLT) 32 ( 16 ) 2760-2770 2014.08

Research paper (scientific journal), Joint Work

A smart photonic cloud is defined as a universal network platform without any physical or logical constraint that provides flexible connectivity for machine-to-machine communication such as networked high-performance computing or intra- and inter-data center networks. The key requirements for the network in the Big Data era include an ultralarge capacity with low power consumption, low latency, as well as flexibility on demand to the changes in the configuration and bandwidth of the optical path. To cope with the growing demand for network virtualization, novel photonic layer virtualization will be proposed,which differs fromthe conventional approach in terms of the number of slices and the dynamic range of the bandwidth of each slice. First, the objectives and the guiding principle of the vision will be addressed. Next, three “Ss” will be presented that represent the key enabling technologies, namely scale-free photonics, smart photonic networking, and a synthetic transport platform.

Using Optical-Approaches to Raise Energy Efficiency of Future Central and/or Linked Distributed Data Center Network Services

Naoaki Yamanaka, Hidetoshi Takeshita, Satoru Okamoto, Takehiro Sato

International Journal of Networking and Computing 4 ( 2 ) 209 - 222 2014.07

Research paper (scientific journal), Joint Work

Novel optical network architectures are proposed for creating future network services. The first architecture is a centralized approach for higher energy efficiency; it yields a data center-centric metro/access optical aggregation network based on wavelength/time-slot multiplexing. Not only higher application layer functions but also all layer-3 or upper traffic are transferred through the simple metro/access optical aggregation network and switched in a huge centralized giant router at the data center. Its simple optical switching is 200 times more energy efficient and only one electrical router is needed, so power consumption of the network can be reduced ten or twenty fold compared to the existing Internet. The second is service mash-up by linked data through a network that uses broadband optical wire for the IoT era. All service contents, hardware, and software programs are defined as service parts. Optical wire interconnects some service parts and creates new mash-up services in the network. That creates deep network functionality in combination with network and processing functions.

Logical OLT Migration in Elastic Lambda Aggregation Network

Takehiro SATO, Yuki HIGUCHI, Hidetoshi TAKESHITA, Satoru OKAMOTO, NAOAKI YAMANAKA, 大木英司

The IEICE Transactions on Communications (Japanese Edition) J97-B ( 7 ) 474-485 2014.07

Research paper (scientific journal), Joint Work

Elastic Lambda Aggregation Network (EλAN) has been proposed to improve the transmission efficiency and reduce the total energy consumption by integrating access networks of different services. In EλAN, Logical Optical Line Terminals (L-OLT) can be migrated between programmable OLTs (P-OLT). In this paper, the method of L-OLT migration for energy saving is proposed. L-OLT placement optimization problem is introduced to obtain the new placement that minimizes the number of running P-OLTs, and the migration sequence. P-OLT sleeping rate and the number of migrations are evaluated by simulation. The demonstration of L-OLT migration on the EλAN prototype system is also reported.

Fast Calculation Method of Point to Multi-point Routing for Energy Efficient Net- work MiDORi

Akiko Hirao, Hidetoshi Takeshita, Satoru Okamoto, Eiji Oki, Naoaki Yamanaka

IEICE Transactions B J97-B ( 2 ) 99-109 2014.02

Research paper (scientific journal), Joint Work

With the increase of traffic and energy consumption of network, energy-saving is an urgent matter. The realization of Multi-point to Multi-point service which can use network resources effectively is also needed. In this paper, we propose an SPMST (SuperPosed Minimum Spanning Tree) algorithm which can reduce the energy consumption of network by aggregating traffic on specied links and putting unused links into sleep mode. This can cover requirements of MP2MP MiDORi network. By computational simulation, the energy efficiency, short calculation time and capability of SPMST are presented. We veried practical effectiveness of proposed algorithm by using a prototype system of MiDORi network.

Proposal of Data-centric Network for Mobile and Dynamic Machine-to-Machine Communication

Daisuke Matsubara, Hitoshi Yabusaki, Satoru Okamoto, NAOAKI YAMANAKA, Tatsuro Takahashi

IEICE Transactions on Communications E96-B ( 11 ) 2795-2806 2013.11

Research paper (scientific journal), Joint Work

Machine-to-Machine (M2M) communication is expected to grow in networks of the future, where massive numbers of low cost, low function M2M terminals communicate in many-to-many manner in an extremely mobile and dynamic environment. We propose a network architecture called Data-centric Network (DCN) where communication is done using a data identifier (ID) and the dynamic data registered by mobile terminals can be retrieved by specifying the data ID. DCN mitigates the problems of prior arts, which are large size of routing table and transaction load of name resolution service. DCN introduces concept of route attraction and aggregation in which the related routes are attracted to an aggregation point and aggregated to reduce routing table size, and route optimization in which optimized routes are established routes to reduce access transaction load to the aggregation points. These allow the proposed architecture to deal with ever increasing number of data and terminals with frequent mobility and changes in data.

サービス品質保証型の大規模省電力クラウドシステム－3都県に跨る大規模システムによる実証実験－

NAOAKI YAMANAKA

Journal of Digital Practices 4 ( 4 ) 342-351 2013.10

Research paper (conference, symposium, etc.), Joint Work

近年、サーバ、ストレージ、端末、ネットワーク等の技術進展により、クラウドサービスが急激に普及し始めている。また、サービスの多様化やユーザの増加により、サービス提供システムの拡大とともに消費電力が急増しており、システムの省電力化が重要な課題の1つとなっている。本論文では、複数のデータセンタとそれらを接続するネットワークより構成される大規模なクラウドシステムおよび提供するサービスに対して、サービスの品質を維持したシステムの省電力化手法について提案する。また、3都県に跨る大規模システムによる実証実験により、サービス品質を維持したクラウドシステムの省電力化について有効性を検証した。

A Parallelized OSPF Weight Setting Scheme based on a Genetic Algorithm for Multi-Core CPUs

Ko Kikuta, Satoru Okaoto, Eiji Oki, NAOAKI YAMANAKA

Cyber Journals: Multidisciplinary Journals in Science and Technlogy, Journal of Selected Areas in Telecommunications Vol.3 ( Issue 9, No.3 ) 1-8 2013.09

Research paper (conference, symposium, etc.), Joint Work

Open Shortest Path First (OSPF) is one of the most widespread routing protocols in the world. In OSPF networks, routers calculate the paths for every traffic demand, based on weight values that are configured in advance. OSPF Weight Setting (OSPF-WS) is an NP-hard search problem; find the set of weights that maximizes network utilization. Internet Service Providers (ISPs) are facing the challenge of solving OSPF- WS within practical time and find the best weight set for the efficient use of the network. One heuristic approach, a scheme based on the Genetic Algorithm (GA), has been reported to offer fast solution of OSPF-WS. This scheme identifies good solutions comparable with the output of the conventional Integer Linear Programming (ILP) scheme. However, its calculation cost is still excessive for larger networks, thus higher processing performance is required. Unfortunately, the processing speed of single processing cores has become saturated, and the recent trend is a shift to multi-core processors. To best utilize the performance offered by these processors, the algorithm should be redesigned and suitably parallelized for multi-core CPUs. This paper redesigns the scheme of OSPF-WS with GA to create a parallelized algorithm with much lower computation overhead. Its performance is evaluated on a 16-core Intel Xeon processor and the result is a roughly 13 fold faster calculation speed than the original algorithm on a single-core CPU. This result shows the potential of further speedups with larger scale parallel processing units such as the GPGPU.

Next Generation Green Metro/Access Network Architecture using Time-slot-based Optical Aggregation Network for Multi-service Access

NAOAKI YAMANAKA, Hidetoshi Takeshita, Kazumasa Tokuhashi, Takehiro Sato

Cyber Journals: Multidisciplinary Journals in Science and Technology JSAT Vol.3 ( 2 ) 7-12 2013.03

Research paper (conference, symposium, etc.), Joint Work

An extremely energy efficient layer-3 network architecture based on optical slot-type aggregation is proposed for the future Internet. Huge numbers of user traffic streams are multiplexed by optical wavelength/time-slots at the central data center router. Each time-slot is transparent, so all types of service can be integrated on any slot. In other words, user IP packets are aggregated and transferred through the Optical Aggregation Network to the centralized router, transparently. The proposed network architecture realizes a network structure well suited to traffic centralization, and reduces the power consumption to 1/10-1/20 compared to the existing Internet.

Experiment of Point-to-Multipoint VLAN Path Establishment on the Overlay-Model-Based GMPLS-Controlled Wide Area Ethernet

Kou KIKUTA, Daisuke ISHII, Satoru OKAMOTO, NAOAKI YAMANAKA

IEICE TRANSACTIONS on Communications E95-B ( 10 ) 3302-3306 2012.10

Research paper (conference, symposium, etc.), Joint Work

A High-Speed Routing Engine for Software Defined Network

Shan Gao, Sho Shimizu, Satoru Okamoto, NAOAKI YAMANAKA

Cyber Journals: Multidisciplinary Journals in Science and Technology, Journal of Selected Areas in Telecommunications (JSAT) ( August 2012 Edition ) 1-7 2012.08

Research paper (conference, symposium, etc.), Joint Work

Recently, attention is particularly focused on the research of Software defined network (SDN) for reducing network management complexity. The one of a key technology of SDN is OpenFlow. OpenFlow provide a centralized controller for network and the scalability of controller is main issue. In this paper, we propose a high-speed routing engine for improve the scalability of OpenFlow controller. Unlike conventional architectures of routing engine, the proposal is a hardware routing engine that using on-chip diorama network. We define the Diorama Network as a virtual emulated network in a chip. We implement a prototype of the routing engine on an actual dynamically reconfigurable processor (DRP), and test results show that the prototype can execute the shortest path calculation 19 times faster than the current approach.

Connection Setup Signaling Scheme with Flooding-Based Path Searching for Diverse-Metric Network

Ko KIKUTA, Daisuke ISHII, Satoru OKAMOTO, Eiji OKI, NAOAKI YAMANAKA

IEICE TRANSACTIONS on Communications E95-B ( 8 ) 2600-2609 2012.08

Research paper (conference, symposium, etc.), Joint Work

Connection setup on various computer networks is now achieved by GMPLS. This technology is based on the source-routing approach, which requires the source node to store metric information of the entire network prior to computing a route. Thus all metric information must be distributed to all network nodes and kept up-to-date. However, as metric information become more diverse and generalized, it is hard to update all information due to the huge update overhead. Emerging network services and applications require the network to support diverse metrics for achieving various communication qualities. Increasing the number of metrics supported by the network causes excessive processing of metric update messages. To reduce the number of metric update messages, another scheme is required. This paper proposes a connection setup scheme that uses flooding-based signaling rather than the distribution of metric information. The proposed scheme requires only flooding of signaling messages with requested metric information, no routing protocol is required. Evaluations confirm that the proposed scheme achieves connection establishment without excessive overhead. Our analysis shows that the proposed scheme greatly reduces the number of control messages compared to the conventional scheme, while their blocking probabilities are comparable.

Energy efficient network design tool for green IP/Ethernet networks

Hidetoshi Takeshita, NAOAKI YAMANAKA, Satoru Okamoto, Sho Shimizu, Shan Gao

Elsevier Journal Optical Switching and Networking 9 ( Issue 3 ) 264-270 2012.07

Research paper (conference, symposium, etc.), Joint Work

An innovative energy-efficient network design algorithm and a tool to lower the network power consumption are proposed. The goal is an energy efficient network that carries its rated communication load while meeting the QoS requirements by using the minimum set of nodes and links. QoS metrics include hop limit, bandwidth limit reliability and stability. The proposed algorithm addresses the set-covered problem. To discover the optimum network configuration efficiently, we propose a network configuration generation algorithm that utilizes DAPDNA-2, a parallel data flow type reconfigurable processer. The processor automatically produces the node/link set in n-digit binary form where links are modeled as ‘‘1’’ for power on and ‘‘0’’ for power off; it also confirms that the QoS requirements are satisfied. Evaluation results show that DAPDNA-2 is 2-orders faster than the conventional sequential method running on a Pentium-4 processor. Prototype Gigabit Layer-2 switches having remote link power on/off and traffic monitoring functions are developed. Using these switches, we successfully demonstrate an energy efficient IP/Ethernet network. The evaluation results show that network power savings of up to 30% can be realized under the NFSNET topology model. The proposed algorithm and power efficient network architecture can be applied to realize the future green network.

Hybrid Passive/Active Optical Access Network Architecture that Reduces OLT Power Consumption

Kazumasa Tokuhashi, Daisuke Ishii, Satoru Okamoto, NAOAKI YAMANAKA

Cyber Journals: Multidisciplinary Journals in Science and Technology, Journal of Selected Areas in Telecommunications(JSAT) ( June Edition ) 2012.06

Research paper (conference, symposium, etc.), Joint Work

A State-of-the-Art Low-Power Optical Network Research

NAOAKI YAMANAKA, Kazumasa Tokuhashi, Hidetoshi Takeshita

The Review of Laser Engineering 40 ( 5 ) 351-355 2012.05

Research paper (conference, symposium, etc.), Joint Work

The power consumption of network devices will continue to increase due to the increase in transmission speed and reach 97 GW by 2020. This paper introduces urgently needed network power reduction methods. First, the paper focuses on the optical access network architectures that use active devices such as high-speed optical switches or variable wavelength lasers to achieve slgnificant energy savings. These new architectures are expected to dramatically reduce the Optical Network Unit (ONU)'s power consumption by introducing an effective sleep mode. Second, this paper introduces an extremely energy efficient future-Internet architecture that uses a large optical aggregation network. It combinesthe centralized Service Cloud with the Cloud Router and application servers and the Optical Aggregation Network. The optical aggregation network can be realized with just simple optical circuit switches, wavelength-Converters,and wavelength-multiplexers/demultiplexers; the complicated layer-3 function is realized only at the center Cloud Router. The optical aggregation network realizes a network structure well suited to today's traffic centralization. According to our evaluation, total network power consumption Can be reduced to Just 1/1000 compare to the electrical based network architecture.

MPCP based Active Optical Access Network with PLZT High-speed Optical Switch

Kazumasa Tokuhashi, Kunitaka Ashizawa, Daisuke Ishii, Satoru Okamoto, NAOAKI YAMANAKA, Koji Wakayama, Keiichi Nashimoto

Elsevier Journal Optical Switching and Networking 9 ( Issue 2 ) 118-129 2012.04

Research paper (conference, symposium, etc.), Joint Work

An active optical access network architecture with our newly developed PLZT ((Pb, La) (Zr, Ti)O3) high-speed optical switch is introduced, with a view to realizing the nextgeneration high capacity scalable access network. This system is developed based on the latest IEEE standard of PON (10G-EPON; IEEE802.3av) in consideration of the coordination with future high capacity PON. PLZT high-speed optical switches are able to switch an optical signal at nano-second speed (<5–10 ns). Generally, the merits of using optical switches are increasing the number of subscribers and transmission distance easily, preventing malicious ONUs from interfacing with the communication between OLT and the other ONUs, realizing fast fiber and OLT protection/restoration and providing various services by controlling optical switches dynamically. This paper focuses on two key technologies; a PLZT optical switch and a new discovery process for active optical access network based on MPCP defined at IEEE802.3. A major challenge in designing active optical access network is supporting the discovery process of MPCP because it does not offer broadcast transmission unlike the regular PON. We propose here a new discovery process; it has been tested successfully in an implementation of our proposed system.

Scalable Active Optical Access Network Using Variable High-Speed PLZT Optical Switch/Splitter

Kunitaka Ashizawa, Takehiro Sato, Kazumasa Tokuhashi, Daisuke Ishii, Satoru Okamoto, NAOAKI YAMANAKA, Eiji Oki

IEICE TRANSACTIONS on Communications E95-B ( 3 ) 730-739 2012.03

Research paper (conference, symposium, etc.), Joint Work

This paper proposes a scalable active optical access network using high-speed Plumbum Lanthanum Zirconate Titanate (PLZT) optical switch/splitter. The Active Optical Network, called ActiON, using PLZT switching technology has been presented to increase the number of subscribers and the maximum transmission distance, compared to the Passive Optical Network (PON). ActiON supports the multicast slot allocation realized by running the PLZT switch elements in the splitter mode, which forces the switch to behave as an optical splitter. However, the previous ActiON creates a tradeoff between the network scalability and the power loss experienced by the optical signal to each user. It does not use the optical power efficiently because the optical power is simply divided into 0.5 to 0.5 without considering transmission distance from OLT to each ONU. The proposed network adopts PLZT switch elements in the variable splitter mode, which controls the split ratio of the optical power considering the transmission distance from OLT to each ONU, in addition to PLZT switch elements in existing two modes, the switching mode and the splitter mode. The proposed network introduces the flexible multicast slot allocation according to the transmission distance from OLT to each user and the number of required users using three modes, while keeping the advantages of ActiON, which are to support scalable and secure access services. Numerical results show that the proposed network dramatically reduces the required number of slots and supports high bandwidth efficiency services and extends the coverage of access network, compared to the previous ActiON, and the required computation time for selecting multicast users is less than 30 msec, which is acceptable for on-demand broadcast services.

Fast Optimal Replica Placement with Exhaustive Search Using Dynamically Reconfigurable Processor

Hidetoshi Takeshita, Sho Shimizu, Hiroyuki Ishikawa, Akifumi Watanabe, Yutaka Arakawa, NAOAKI YAMANAKA, Kosuke Shiba

Journal of Computer Networks and Communications 2011 ( Article ID 707592 ) 1-11 2011.12

Research paper (conference, symposium, etc.), Joint Work

This paper proposes a new replica placement algorithm that expands the exhaustive search limit with reasonable calculation time.
It combines a new type of parallel data-flow processor with an architecture tuned for fast calculation. The replica placement
problem is to find a replica-server set satisfying service constraints in a content delivery network (CDN). It is derived from the
set cover problem which is known to be NP-hard. It is impractical to use exhaustive search to obtain optimal replica placement in
large-scale networks, because calculation time increases with the number of combinations. To reduce calculation time, heuristic
algorithms have been proposed, but it is known that no heuristic algorithm is assured of finding the optimal solution. The proposed
algorithm suits parallel processing and pipeline execution and is implemented on DAPDNA-2, a dynamically reconfigurable
processor. Experiments show that the proposed algorithm expands the exhaustive search limit by the factor of 18.8 compared
to the conventional algorithm search limit running on a Neumann-type processor.

A Design Method High-Reliability and Low-Optical-Loss Optical Aggregation Network Using 2×2 Optical Switch

Takehiro SATO, Kunitaka ASHIZAWA, Kazumasa TOKUHASHI, Daisuke ISHII, Satoru OKAMOTO, Eiji OKI, NAOAKI YAMANAKA

IEICE TRANSACTIONS on Communications J94-B ( 11 ) 1508-1512 2011.11

Research paper (conference, symposium, etc.), Joint Work

Fast Fault Recovery Method with Preestablished Recovery Table for ReliableWide Area Layer-2 Network

Takashi Kurimoto, Midori Terasawa, Sho Shimizu, Satoru Okamoto,NAOAKI YAMANAKA

International Scholarly Research Network(ISRN) Communications and Networking 2011 ( 941605 ) 1-8 2011.10

Research paper (conference, symposium, etc.), Joint Work

Recently, wide area Ethernet, which provides virtual connections between company branches by using Ethernet technology, has become wide spread. Ethernet originally lacked fault recovery mechanisms required in wide area networks (WANs) since it originated as local area network (LAN) technology. Protection mechanism against link or node failure is proposed in Ethernet network, but many frame losses are inevitable during the switch over to the backup path. Therefore, to improve reliability of wide area Ethernet, a fault recovery method with few frame losses is required. This paper proposes a fast fault recovery method for reducing frame losses during the switching over to another route. To achieve fast recovery, a pre-established forwarding table is introduced, which is searched when a fault occurs and frames are forwarded. This paper also proposes a bandwidth control function to guarantee the quality of service of connections that do not use the failed link when a fault occurs. A computer simulation showed that by adding the proposed fault recovery method to the conventional protection method, frame losses can be decreased. The proposed fault recovery method was implemented on a software switch framework to confirm its effectiveness.

Energy Optimal Topology Calculation Method for Self Organized Network MiDORi

Haruka Yonezu, Daisuke Ishii, Satoru Okamoto, Eiji Oki, NAOAKI YAMANAKA

IEICE TRANSACTIONS on Communications J94-B ( 10 ) 1323-1331 2011.10

Research paper (conference, symposium, etc.), Joint Work

In order to reduce the energy consumption of transport/data center networks, MiDORi network technology is introduced. This network is based on the concept of aggregating traffic into specific links, and powering off interfaces of routers/switches that do not convey traffic. In this paper, a practical energy-optimal topology calculation method is proposed for the MiDORi PCE. The proposal can adjust the link reduction rate and the calculation time by setting different values for the depth. Moreover, two failure management methods are proposed in order to reduce the risk of traffic aggregation. By computer simulation, it is shown that the proposed method is effective from several perspectives. Lastly, a prototype system of MiDORi network is described to observe the aspect of self organization.

High Density Short-Term Forecasting Photovoltic Output Power Architecture without Meteorological Observations in Smart Grid

Jun Matsumoto, Daisuke Ishii, Satoru Okamoto, Eiji Oki, NAOAKI YAMANAKA

IEICE TRANSACTIONS on Communications J94-B ( 10 ) 1373-1382 2011.10

Research paper (conference, symposium, etc.), Joint Work

近年日本では家庭用ソーラーパネルやマイクロCHPが急速に普及しており, それらの分散化された発電エネルギーの利用法が日本におけるスマートグリッド研究課題の一つである. 効率的な発電エネルギー利用のため消費デバイスとのスケジューリング連携が有効であり, 太陽光発電出力量の短期的な予測が重要となる. 従来の太陽光発電出力予測手法は主に中長期的な規則性を伴う出力変動について議論しており, 気候による不規則な変動の激しい短期的な予測には適さない. また既存の短期的な予測手法についても特別な気象観測機器が必要であるという課題が残る. そこで本論文では, 気象観測情報を用いずに各ソーラーパネルの発電出力情報のみを用いて予測する手法を提案する. 本手法では, ネットワークに接続されたスマートメータから各地点の発電出力情報をサンプリングし, データ補間及びオプティカルフロー推定技術を用いて, 各地点における将来の発電出力量を予測する. その際, 過去のサンプリングデータを仮想的に補間元データとして用いるバーチャルサンプリングにより, 少ないサンプリング数でも高精度な予測を可能とする. コンピュータシミュレーションにより, 本予測手法の有効性及びバーチャルサンプリングによる予測精度の改善を示す.

Performance Evaluation of TCP/IP over SCTP/IP Parallel Networking with Parallel Route Transmission

Shota YAMADA, Daisuke ISHII, Satoru OKAMOTO,NAOAKI YAMANAKA

IEICE TRANSACTIONS on Communications E94-B ( 8 ) 2394-2396 2011.08

Research paper (conference, symposium, etc.), Joint Work

In this paper, Transmission Control Protocol/Intemet Protocol(TCP/IP) over Stream Control Transmission Protocol (SCTP)/IP parallel transmission system is proposed to realize large TCP/IP throughput. The proposed system enables SCTP/IP connection between switches by protocol stacking. The proposed system is implemented on a software switch to evaluate its performance. The evaluation result indicates that proposed system can achieve 90% throughput compared with serial transmission when the delay difference among parallel routes is 20 msec.

通信技術が生むスマートネットワークの新しいビジネスチャンス

NAOAKI YAMANAKA

CIAJ Journal ( 6月 ) 12-17 2011.06

Research paper (scientific journal), Single Work

On-Demand Multicast Slot Allocaton Scheme For Active Optical Access Network Using PLZT High-Speed Optical Switches

Kunitaka Ashizawa, Takehiro Sato, Kazumasa Tokuhashi, Daisuke Ishii, Naoaki Yamanaka, Eiji Oki

Cyber Journals: Multidisciplinary Journals in Science and Technlogy, Journal of Selected Areas in Telecommunications JSAT ( May 2011 Edition ) 19-27 2011.05

Research paper (scientific journal), Joint Work

This paper proposes an on-demand multicast slot allocation scheme for an active optical access network that uses Mach-Zehnder-type high-speed optical switches, which are achieved by the Plumbum Lanthanum Zirconate Titanate (PLZT) switching technology. The Active Optical Network, called ActiON, is based on slot-based switching. Compared to the Passive Optical Network (PON), ActiON quadruples the number of subscribers (128 users) per optical line terminal (OLT) and doubles the maximum transmission distance (40 km) between OLT and optical network units (ONUs). However, as ActiON uses slot-based switching, it needs a large number of slots to deliver multicast contents to the requesting users. This greatly lowers network utilization rates. The proposed multicast slot allocation scheme overcomes this problem to provide on-demand multicast services, while keeping the advantages of ActiON. Multicast delivery is realized by running the Mach-Zehnder-type high-speed optical switch elements in distribution mode, which forces the switch to behave as an optical splitter. The proposed scheme iteratively solves the integer linear programming (ILP) problem to associate multicast users with slots. Numerical results show that the proposed scheme dramatically reduces the required number of slots, compared to non-multicast ActiON and provides comparable the performance of bandwidth efficiency to 10 G-EPON, and the required computation time of the proposed scheme is less than 0.3 sec, which is feasible for on-demand services.

Highly Energy Efficient Layer-3 Network Architecture Based on Service Cloud and Optical Aggregation Network

Hidetoshi TAKESHITA, Daisuke ISHII, Satoru OKAMOTO, Eiji OKI,NAOAKI YAMANAKA

IEICE Transactions on Communications E94-B ( 4 ) 894-903 2011.04

Research paper (conference, symposium, etc.), Joint Work

The Internet is an extremely convenient network and has become one of the key infrastructures for daily life. However, it suffers from three serious problems; its structure does not suit traffic centralization, its power consumption is rapidly increasing, and its round-trip time (RTT) and delay jitter are large. This paper proposes an extremely energy efficient layer-3 network architecture for the future Internet. It combines the Service Cloud with the Cloud Router and application servers, with the Optical Aggregation Network realized by optical circuit switches, wavelength-converters, and wavelength-multiplexers/demultiplexers. User IP packets are aggregated and transferred through the Optical Aggregation Network to Cloud transparently. The proposed network scheme realizes a network structure well suited to traffic centralization, reduces the power consumption to 1/20-1/30 compared to the existing Internet, reduces the RTT and delay jitter due to its simplicity, and offers easy migration from the existing Internet.

光スイッチを用いた10ギガビット／秒アクティブ光アクセスシステムの研究開発

Koji Wakayama, NAOAKI YAMANAKA

Electronics Product Digest 27 ( 12 ) 17 2010.12

Research paper (conference, symposium, etc.), Joint Work

50th Anniversary of Birth of Lasers

Hiromichi SHINOHARA, NAOAKI YAMANAKA

THE JOURNAL OF THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATIONS ENGINEERS 93 ( 12 ) 1057-1059 2010.12

Research paper (conference, symposium, etc.), Joint Work

1960年にT.H.Maimanがヒューズ・リサーチ・ラボラトリで初めてレ-ザ光の発振に成功してから50年を迎えた.電子情報通信学会東京支部では,記念すべきこの年に,レ-ザの発展に多大な貢献をされた霜田光一,末松安晴両博士の講演会を7月1日に開催した.レ-ザ研究の経緯や発見・発明のエピソード,開発の苦労,その後の応用について,当時を知る両氏からしか聞くことのできない貴重な話を伺った.講演会の後,両氏の厚意により, 50年前の古い資料を拝見するアーカイブズ展示会を実施した. Maiman,Javan, Lambら,メ-ザ・レ-ザのれい明期の論文や手書き原稿,当時の写真,レ-ザ発明当時の製造機器,世界をリードしてきた日本国内各社のレ-ザ製品,関連するノーベル賞受賞者と講師の交流の記録などに多くの参加者が見入った.今日,情報,通信,映像などのICT産業のみならず, 医療,加工,分析などあらゆる分野においてレ-ザが果たしている役割の大きさは計り知れない.講演会,展示会とも,レ-ザ発明の歴史的偉業とその後の発展の歴史のみならず,日本の進むべき技術立国のビジョンに対して勇気と活力を与えられるものであった.講演会当日は, 200名を超える聴衆が会場を埋め尽くしたが,このような貴重な講演は,聴講者だけでなく,その一端だけでも広く会員に紹介すべきとの意見を多数頂だいしたため,本誌に寄稿するものである.

Dynamic Packet (Frame) Based Ranging Method for Active Optical Access Network

Kazumasa Tokuhashi, Kunitaka Ashizawa, Daisuke Ishii, Yutaka Arakawa, Satoru Okamoto,NAOAKI YAMANAKA

IEICE Trans. On Communications J93-B ( 8 ) 1087-1091 2010.08

Research paper (conference, symposium, etc.), Joint Work

High-energy Efficient Layer-3 Network Architecture based on Solitary Universal Cloud Router and Optical Aggregation Network

Hidetoshi Takeshita, Daisuke Ishii, NAOAKI YAMANAKA

9th International Conference on Optical Internet 2010(COIN2010) 2010.07

Research paper (conference, symposium, etc.), Joint Work

Network Designing Algorithm for Low Power Consumption under QoS restriction

Haruka Yonezu, Yutaka Arakawa, NAOAKI YAMANAKA

SCAT TECHNICAL JOURNAL TELECOM FRONTIER NO.67 2010 SPRING ( 67 ) 19-31 2010.05

Research paper (conference, symposium, etc.), Joint Work

Green ITとよばれ近年, 地球環境に配慮した技術開発が重視されつつある. 情報ネットワークの分野においてもネットワークの広帯域化とサービスの質の向上による増え続ける需要をさばくためのネットワークリソースは急増し, それによる看過できない電力消費の伸びが指摘され始めるなどており, ネットワークの省電力化は今後重視すべき課題である. 装置やデバイスのみではなく, 運用方法やアーキテクチャを組み合わせた検討が必要である. 本提案は, いままであまりアプローチされていなかった, 通信ネットワークの消費電力を通信品質を保証しながら最適に制御する方法を, すべての組み合わせを計算する方法を研究した. いままでは計算時間が膨大過ぎて現実的ではないと思われていた集合被覆問題に帰着させ, リコンフィギャラブルプロセッサデバイスを用いて高速に解き, さまざまなネットワークリソースを, もっとも省電力で使用する構成を動的に求めることを可能にするものである. 具体的にはネットワークリンクを必要最小数のみパワーオンし, またルートも必要最少とするような省電力ルータの制御を行うことができる計算エンジンを提案する. また, エンジンによって計算した結果を実ネットワークに反映させ, リンクをon/offするプロトコルをGMPLSを拡張して実現し, また, プロトタイプシステムで実験的に確認した.

Active Optical Access Network (ActiON) based on newly developed 10-ns High-speed PLZT Optical Switch

NAOAKI YAMANAKA

NewBreeze 22 ( 2 ) 16-17 2010.04

Research paper (scientific journal), Single Work

A new optical access network architecture called called Active Optical Network (ActiON) is proposed which uses a newly-developed 10 nsec PLZT((Pb, La)(Zr, Ti)O3) high-speed optical switch. ActiON can handle four times the number of subscribers(128) that GEPON can handle as well as doubling the transmission distance(to 40 km). Moreover, users can enjoy secure communication in ActiON because it is a switch-based system. However, ActiON has to overcome a Discovery-Ranging process issue because an optical switch cannot broadcast signals. In this paper, the architecture of ActiON and a novel Discovery-Ranging process technique is proposed. The proposed access system architecture and high-speed PLZT switch will be able to be applied to next generation broadband access systems.
Keywords

Dynamic Packet (Frame) Based Ranging Method for Active Optical Access Network

Kazumasa TOKUHASHI, Kunitaka ASHIZAWA, Daisuke ISHII, Yutaka ARAKAWA, Satoru OKAMOTO, YAMANAKA NAOAKI

IEICE Transactions on Communications J93-B ( 8 ) 1087-1091 2010.03

Research paper (scientific journal), Joint Work

Interoperability Experiment of VLAN Tag Swapped Ethernet and Transmitting High Definition Video through the Layer-2 LSP between Japan and Belgium

Sho Shimizu, Wouter Tavernier, Kou Kikuta, Masahiro Nishida, Daisuke Ishii, Satoru Okamoto, Didier Colle, Mario Pickavet, Piet Demeester,YAMANAKA NAOAKI

IEICE Transactions on Communications E93.B ( 3 ) 736-740 2010.03

Research paper (scientific journal), Joint Work

Evaluation of prototype for 10Gbps active optical access system

Wakayama Koji, Hasegawa Chie, Ishii Daisuke, Yamanaka Naoaki

436 - 437 2010

Resource Minimization Method Satisfying Delay Constraint for Replicating Large Contents

Sho Shimizu, Hiroyuki Ishikawa, Yutaka Arakawa, Kosuke ShibaYAMANAKA NAOAKI

IEICE Transactions on Communications E92-B ( 10 ) 3102-3110 2009.10

Research paper (scientific journal), Joint Work

How to minimize the number of mirroring resources under a QoS constraint (resource minimization problem) is an important issue in content delivery networks. This paper proposes a novel approach that takes advantage of the parallelism of dynamically reconfigurable processors (DRPs) to solve the resource minimization problem, which is NP-hard. Our proposal obtains the optimal solution by running an exhaustive search algorithm suitable for DRP. Greedy algorithms, which have been widely studied for tackling the resource minimization problem, cannot always obtain the optimal solution. The proposed method is implemented on an actual DRP and in experiments reduces the execution time by a factor of 40 compared to the conventional exhaustive search algorithm on a Pentium 4 (2.8 GHz).

Multi-Domain VLAN Path Signaling Method having Tag Swapping Function for GMPLS controlled Wide Area Layer-2 Network

Kou KIKUTA, Masahiro NISHIDA, Daisuke ISHII, Satoru OKAMOTO, YAMANAKA NAOAKI

IEICE Transactions on Communications E92-B ( 04 ) 2009.04

Research paper (scientific journal), Single Work

Frame Loss Evaluation of Optical Layer 10 Gigabit Ethernet Protection Switching using PLZT Optical Switch System

Satoru Okamoto, Sho Shimizu, Yutaka Arakawa,YAMANAKA NAOAKI

IEICE Transactions on Communications E92-B ( 3 ) 2009.03

Research paper (scientific journal), Joint Work

Performance Evaluation of Grid Computing with Parallel Routes Transmission

Hiroyuki MIYAGI, Yusuke OKAZAKI, Ryota USUI, Yutaka ARAKAWA, Satoru OKAMOTO, YAMANAKA NAOAKI

IEICE Transactions on Communications E91-B ( 12 ) 3882-3885 2008.12

Research paper (scientific journal), Joint Work

GMPLS-based optical slot switching access-distribution network with a 10 ns high-speed PLZT optical switch

Masahiro Hayashitani, Teruo Kasahara, Daisuke Ishii, Yutaka Arakawa, Satoru Okamoto, YAMANAKA NAOAKI, Naganori Takezawa, Keiichi Nashimoto

JOURNAL OF OPTICAL NETWORKING 7 ( 8 ) 744-758 2008.08

Research paper (scientific journal), Joint Work

Multi-ASON and GMPLS Network Domain Interworking Challenges

Satoru Okamoto, Hideki Otsuki, Tomohiro Otani

IEEE Communications Magazine 46 ( 6 ) 2008.06

Research paper (scientific journal), Joint Work

10ns High-speed PLZT optical content distribution system having slot-switch and GMPLS controller

Masahiro Hayashitani, Teruo Kasahara, Daisuke Ishii, Yutaka Arakawa, Satoru Okamoto, YAMANAKA NAOAKI, Naganori Takezawa, Keiichi Nashimoto

IEICE Electronics Express 5 ( 6 ) 181-186 2008.03

Research paper (scientific journal), Joint Work

Advanced Wavelength Reservation Method Based on Deadline-Aware Scheduling for Lambda Grid Networks

Hiroyuki Miyagi, Masahiro Hayashitani, Daisuke Ishii, Yutaka Arakawa, YAMANAKA NAOAKI

IEEE/OSA Journal of Lightwave Technology 25 ( 10 ) 2904-2910 2007.10

Research paper (scientific journal), Joint Work

Optical burst switched ring network with upstream prioritized switching and distributed fairness control

Arakawa Yutaka, Yamanaka Naoaki, Sasase Iwao

Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi) 90 ( 8 ) 30 - 39 2007.08

ISSN 8756-6621

With a view to constructing a metropolitan network that can flexibly handle highly bursty traffic, an optical burst switched ring network with upstream prioritized switching and distributed fairness control is proposed. In optical burst switching, high burst drop rates at intermediate nodes constitute a problem. In the proposed system, burst signal dropping at the relay nodes is eliminated by means of upstream prioritized switching. At the same time, by using distributed fairness control, the problem of upstream prioritized switching-related unfairness, in which positional priority provides higher priority to more distant transmission nodes, is resolved. Further, by modifying the reservation of downstream nodes by using the trailer packet after disconnection of the transmission, unnecessary bandwidth is eliminated and the throughput is improved. By computer simulation, the throughput and the fairness with regard to the throughput are evaluated. It is shown that the proposed architecture exhibits excellent characteristics even in cases of hot-spot traffic, in which concentrated traffic occurs at a particular destination. © 2007 Wiley Periodicals, Inc.

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GMPLS interoperability tests in Kei-han-na Info-Communication Open Laboratory on JGN II network

Satoru Okamoto, Wataru Imajuku, Tomohiro Otani, Itaru Nishioka, Akira Nagata, Mikako Nanba, Hideki Otsuki, Masatoshi Suzuki, YAMANAKA NAOAKI

IEICE Transactions on Communications VOL.E90-B ( No.8 ) 1936-1943 2007.08

Research paper (conference, symposium, etc.), Joint Work

QoS differentiation scheme with multiple burst transmission and virtual resource reservation for optical burst switching networks

Yutaka Arakawa and YAMANAKA NAOAKI

JOURNAL OF OPTICAL NETWORKING 6 ( 8 ) 1003-1013 2007.08

Research paper (scientific journal), Joint Work

Special section on feature topics on latest trends in optical networks

Murata Masayuki, Shiomoto Kohei, Nakano Yoshiaki, Namiki Shu, Sato Ken Ichi, Yamanaka Naoaki

IEICE Transactions on Communications E90-B ( 8 ) 1889 2007.08

ISSN 0916-8516

Access to Document (DOI)

Standardization and Practical Use Trends of Generalized Multi-Protocol Label Switching Technologies

OKAMOTO SATORU, YAMANAKA NAOAKI

電子情報通信学会誌 89 ( 8 ) 752-757 2006.08

Research paper (scientific journal), Joint Work

Wavelength assignment scheme for WDM networks with limited-range wavelength converters

Sho Shimizu, Yutaka Arakawa, YAMANAKA NAOAKI

Journal of Optical Networking 5 ( 5 ) 410-421 2006.05

Research paper (scientific journal), Joint Work

Optical Burst Switched Ring Network with Upstream Prioritized Switching and Distributed Fairness Control

Yutaka ARAKAWA, Naoaki YAMANAKA, Iwao SASASE

IEICE TRANSACTION on Communication(JAPANESE EDITION) vol.J89-B ( No.2 ) 242-252 2006.02

Research paper (conference, symposium, etc.), Joint Work

Self-learning route selection scheme using multipath searching packets in an OBS Network

ISHII DAISUKE, YAMANAKA NAOAKI, SASASE IWAO

Journal of Optical Networking Vol.4 ( No.7 ) 432-445 2005.07

Research paper (scientific journal), Joint Work

A 10Gb/s Firewall System for Network Security in Photonic Era

M. Katayama, H. Kai, J.Yoshida, M.Inami, H.Yamada, K.Shiomoto, N.Yamanaka

IEICE TRANSACTIONS on Communications VOL.E88-B ( NO.5 ) 1914-1920 2005.05

Research paper (conference, symposium, etc.), Joint Work

Dynamic multilayer routing schemes in GMPLS-based IP+optical networks

Oki Eiji, Shiomoto Kohei, Shimazaki Daisaku, Yamanaka Naoaki, Imajuku Wataru, Takigawa Yoshihiro

IEEE Communications Magazine 43 ( 1 ) 108 - 114 2005.01

ISSN 0163-6804

This article presents two dynamic multilayer routing policies implemented in the photonic MPLS router developed by NTT for IP+optical generalized MPLS networks. According to IP traffic requests, wavelength paths called lambda label switched paths are set up and released in a distributed manner based on GMPLS routing and signaling protocols. Both dynamic routing policies first try to allocate a newly requested electrical path to an existing optical path that directly connects the source and destination nodes. If such a path is not available, the two policies employ different procedures. Policy 1 tries to find available existing optical paths with two or more hops that connect the source and destination nodes. Policy 2 tries to establish a new one-hop optical path between source and destination nodes. The performances of the two routing policies are evaluated. Simulation results suggest that policy 2 outperforms policy 1 if p is large, where p is the number of packet-switching-capable ports; the reverse is true only if p is small. We observe that p is the key factor in choosing the most appropriate routing policy. We also describe items that need to be standardized in the IETF to effectively achieve multilayer traffic engineering. © 2005 IEEE.

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Scalable multi-layer GMPLS networks based on hierarchical cloud-routers

Shimazaki Daisaku, Oki Eiji, Shiomoto Kohei, Yamanaka Naoaki

IEICE Transactions on Communications E88-B ( 3 ) 1119 - 1127 2005

ISSN 0916-8516

This paper proposes the hierarchical cloud-router network (HCRN) to overcome the scalability limit in a multi-layer generalized multi-protocol label switching (GMPLS) network. We define a group of nodes as a virtual node, called the cloud-router (CR). A CR consists of several nodes or lower-level CRs. A CR is modeled as a multiple switching capability (SC) node when it includes more than one kind of SC, which is fiber SC, lambda SC, time-division multiplexing (TDM) SC, packet SC, even if there are no actual multiple switching capability nodes in the CR. The CR advertises its abstracted CR internal structure, which is abstracted link state information inside the CR. A large-scale, multi-layer network can then achieve scalability by advertising the CR internal structure throughout the whole network. In this scheme, the ends of a link connecting two CRs are defined as interfaces of the CRs. We adopt the CR internal cost scheme between CR interfaces to abstract the network. This CR internal cost is advertised outside the CR via the interfaces. Our performance evaluation has shown that HCRN can handle a larger number of nodes than a normal GMPLS network. It can also bear more frequent network topology changes than a normal GMPLS network. Copyright © 2005 The Institute of Electronics, Information and Communication Engineers.

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A scheduling algorithm for reducing unused timeslots by considering head gap and tail gap in Time Sliced Optical Burst Switched networks

Ito Takanori, Ishii Daisuke, Okazaki Kohei, Yamanaka Naoaki, Sasase Iwao

IFIP Advances in Information and Communication Technology (IFIP) 164 79 - 86 2005

Research paper (scientific journal), Joint Work

We propose a scheduling algorithm for reducing unused timeslots by considering head gap and tail gap newly generated by assigning a data burst in order to improve the burst loss probability and the throughput performances in Time Sliced Optical Burst Switched (TSOBS) networks. The proposed scheduling algorithm selects the timeslot in which either head gap or tail gap newly generated becomes the minimum. We show that the proposed scheduling algorithm can improve the burst loss probability and the throughput performances as compared with the conventional one. © 2005 by International Federation for Information Processing.

A 10Gb/s wire-speed firewall system using reconfigurable processors

Katayama M., Kai H., Yoshida J., Yamada H., Shiomoto K., Yamanaka N.

IEEE International Conference on Communication ICC2005 300 - 305 2005

Research paper (international conference proceedings)

Although the Internet is playing an increasingly significant role in global communication, it remains vulnerable to malicious traffic such as worms and DoS/DDoS attacks. In the last few years, the emergence of high speed active worms, such as Code Red II, Nimda, SQL Slammer and MS Blaster, has become a serious issue. These worms cause serious damage to communication networks throughout the world by using up network bandwidth. In addition, since conventional firewall systems are located just in front of the server and do not prevent malicious traffic from entering the network, they cannot prevent such network congestion. We have developed a proto-type system of a network firewall using reconfigurable processors. In this paper, we overview the developed system and present its evaluation results. © 2005 IEEE.

Photonic-GMPLS Leading Edge Code Research Consortium: Photonic Internet Lab.(PIL)

A. Misawa, N. Yamanaka

China Communications vol.1 ( No.1 ) 106-112 2004.12

Research paper (conference, symposium, etc.), Joint Work, Accepted

ConSet: Hierarchical Concurrent Path Setup Scheme in Multi-Layer GMPLS Networks

E. Oki, D. Shimazaki, K. Shiomoto,N. Yamanaka

IEICE TRANSACTION on Communication vol.E87-B ( No.10 ) 3107-3110 2004.10

Research paper (conference, symposium, etc.), Joint Work, Accepted

Bidirectional Path Setup Scheme Using on Upstream Label Set in Optical GMPLS Networks

Eiji Oki, Kohei Shiomoto, Masaru Katayama, Wataru Imajyuku、Naoaki Yamanaka, and Yoshihiro Takigawa

IEICE Transactions vol.E87-B ( No,6 ) 1569-1576 2004.06

Research paper (conference, symposium, etc.), Joint Work, Accepted

Performance Evaluation of Dynamic Multi-layer Routing Schemes in Optical IP Networks

Eiji Oki, Kohei Shiomoto, Masaru Katayama, Wataru Imajyuku,　Naoaki Yamanaka, and Yoshihiro Takigawa

IEICE Transactions vol.E87-B ( No,6 ) 1577-1583 2004.06

Research paper (conference, symposium, etc.), Joint Work

Photonic Internet Lab.: Breakthrough for Leading Edge Photonic-GMPLS

YAMANAKA NAOAKI

IEICE Transactions vol.E87-B ( No,3 ) 573-578 2004.03

Research paper (conference, symposium, etc.), Single Work, Accepted

Photonic Internet Lab. (PIL) is shooting for the leading edge photonic-GMPLS (Generalized Multi-protocol Label Switching) that utilizes wide-band, cost-effective photonic technology to implement IP-centric managed networks. PIL is a consortium for researching the GMPLS protocol and advancing a de facto standard in this area. Members make leading edge GMPLS code modules and test them at the lab site. The experimental results, new ideas, and protocols are contributed to standardization bodies such as IETF and OIF. This paper also describes the world's first trial of GMPLS multi-region (multi-layer), multi-route, multi-vender signaling.

Proomotion of Next-generation Photonic Network Protocol Standardization by Photonic Internet Lab (PIL)

A. Misawa, K. Shiomoto, S. Okamoto, N. Yamanaka

NTT Technical Review vol,2 ( No.2 ) 2004.02

Research paper (bulletin of university, research institution), Joint Work

GMPLS and IP+MPLS interworking technologies - Routing and signaling

Shimazaki Daisaku, Oki Eiji, Shiomoto Kohei, Yamanaka Naoaki

2004 Workshop on High-performance Switching and Routing, 2004 HPSR 27 - 31 2004

Research paper (international conference proceedings)

When nodes that support generalized multi-protocol label switching (GMPLS) are introduced into existing networks, the GMPLS nodes co-exist with conventional Internet protocol (IP) and multi-protocol label switching (MPLS) (IP+MPLS) nodes that do not support GMPLS. In this case, the GMPLS nodes must Interwork with IP+MPLS nodes. This paper proposes an architecture for GMPLS and IP+MPLS inter-working based on extended routing and signaling. In the extended routing, information about some nodes and links in a GMPLS network emulates information that can be understood by IP+MPLS nodes. The emulated information is advertised to the IP+MPLS network. In the extended signaling, MPLS signaling packets are forwarded to the GMPLS data plane. An MPLS label switched path (LSP) is established through a GMPLS LSP tunnel. As a result, the IP+MPLS network can interwork with the GMPLS network without upgrading the IP+MPLS nodes. We developed GMPLS prototype nodes that support this interworking architecture and show interworking experimental results.

Photonic Internet Labにおける次世代フォトニックネットワークプロトコル標準化の推進

A. Misawa, K. Shiomoto, S. Okamoto, N. Yamanaka

NTT技術ジャーナル vol.15 ( No.12 ) 66-67 2003.12

Research paper (bulletin of university, research institution), Joint Work

Traffic Engineering Techniques in Photonic Networks

S. Okamoto,N. Yamanaka

NTT Technical Review vol.1 ( No.8 ) 24-35 2003.11

Research paper (bulletin of university, research institution), Joint Work

Distributed Virtual Network Topology Control Mechanism in GMPLS-Based Multiregion Networks

K. Shiomoto, E. Oki, W. Imajuku, S. Okamoto, N. Yamanaka

IEEE Journal on selected areas in communications Vol.21 ( No,8 ) 1254-1262 2003.10

Research paper (conference, symposium, etc.), Joint Work, Accepted

Multi-Stage Switching System Using Optical WDM Grouped Links Based on Dynamic Bandwidth Sharing

E. Oki, N. Yamanaka, K. Nakai, N. Matsuura

IEEE Communications Magazine Vol.41 ( No.10 ) 56-63 2003.10

Research paper (conference, symposium, etc.), Joint Work, Accepted

A Disjoint Path Selection Scheme with Shared Risk Link Group Constraints in GMPLS Networks

E. Oki, N. Matsuura, K. Shiomoto, N. Yamanaka

IEICE TRANS. COMMUN. Vol.E86-B ( No.8 ) 2455-2462 2003.08

Research paper (conference, symposium, etc.), Joint Work

Traffic engineering Techniques in the Photonic Networks

S. Okamoto, N. Yamanaka

NTT R&D Vol.52 182-191 2003.03

Research paper (bulletin of university, research institution), Joint Work

WDM Optical Interconnection Modules for Tb/s-Class Electro-Optical Switching System

N. Matsuura, T. Ohyama, E. Oki, N. Yamanaka, K. Yamakoshi, Y. Akahori

Japan Institute of Electronics Packaging Vol.6 ( No.2 ) 168-172 2003.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

Photonic MPLS network architecture based on Hikari-router

Yamanaka N.

Fourth International Workshop on Design of reliable Communication Networks, 2003(DRCN2003) 152 - 161 2003

Research paper (international conference proceedings), Single Work

This paper describes multilayer traffic engineering and signaling technologies in the photonic-GMPLS-router (Hikari-router) network. Multilayer traffic engineering, which yields the dynamic cooperation of IP and photonic layers, is described with the goal of providing IP services cost-effectively. The establishment of photonic cut-through paths is triggered when the Layer 3 traffic loads become excessive which better uses the optical layer (LI) resources. Data on traffic volumes are exchanged among edge photonic router using an extended IBGP. To realize multilayer traffic engineering, we propose an OSPF extension that advertises both the number of total wavelengths and the number of unreserved wavelengths, and an RSVP-TE extension that minimizes the number of wavelength conversions needed. In addition, this paper presents a heuristic-based multilayer topology design scheme in which IP traffic measurements are performed in generalized multiprotocol label switches (GMPLSs). Our design scheme yields the optical label switch path (OLSP) network topology, i.e. OLSP placement that minimizes network cost in the face of fluctuations in IP traffic demand. In other words, the OLSP network topology is dynamically reconfigured to match IP traffic demand. Networks are reconfigured by the proposed scheme so as to utilize the network resources cost-effectively.

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Scalable Multi-Layer GMPLS Networks Based on Hierarchical Cloud-Routers

Shimazaki Daisaku, Oki Eiji, Shiomoto Kohei, Yamanaka Naoaki

IEEE Global Telecommunication Conference GLOBECOM'03 3792 - 3796 2003

Research paper (international conference proceedings), Joint Work

This paper proposes the hierarchical cloud-router network (HCRN) to solve the problem of overcoming the scal-ability limit in a multi-layer generalized multi-protocol label switching (GMPLS) network. We define a group of nodes as a virtual node, called cloud-router (CR). A CR consists of some number of nodes or lower-level CRs. A CR is modeled as a multiple switching capability (SC) node when it includes more than one kind of SC, which is fiber SC, lambda SC, time-division multiplexing (TDM) SC, packet SC, even if there are no actual multiple-SC nodes in the CR. The CR advertises its abstracted CR internal structure which is abstracted link state information inside the CR. A large-scale, multi-layer network can then achieve scalability by advertising the CR internal structure throughout the whole network. In this scheme, the ends of a link connecting between two CRs are defined as interfaces of the CRs. We adopt the CR internal cost scheme between CR's interfaces to abstract the network. This CR internal cost is advertised outside the CRs via the interfaces. Our performance evaluation has shown that HCRN can operate a larger number of nodes than a normal GMPLS network. It can also bear more frequent network topology changes than a normal GMPLS network.

Performance of dynamic multi-layer routing schemes in IP+optical networks

Oki E., Shiomoto K., Katayama M., Imajuku W., Yamanaka N.

Workshop on High performance Switching and Routing, 2003, HPSR 233 - 238 2003

Research paper (international conference proceedings), Joint Work

This paper presents two dynamic multi-layer routing policies for optical IP networks. Both policies first try to allocate a newly requested electrical path to an existing optical path that directly connects the source and destination nodes. If such a path is not available, the two policies employ different procedures. Policy 1, which has been published already, tries to find available existing optical paths with two or more hops that connect the source and destination nodes. Policy 2, which is proposed in this paper, tries to establish a new one-hop optical path between source and destination nodes. The performance of the two routing policies is evaluated. Simulation results suggest that policy 2 outperforms policy 1 if p is large, where p is the number of packet-switching-capable ports p; the reverse is true only if p is small. We observe that p is the key factor in choosing the most appropriate routing policy. © 2003 IEEE.

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Scalable shared-risk group management in shared mesh restorable wavelength routed networks

Shiomoto K., Imajuku W., Oki E., Okamoto S., Yamanaka N.

2003 Workshop on High-performance Switching and Routing, 2003 HPSR 189 - 194 2003

Research paper (international conference proceedings), Joint Work

The paper proposes a scaleable SRG-based restoration method in shared mesh wavelength-routed networks. We introduce a backup-SRG concept to identify which SRG is backed up by individual links. We have developed an admission control method for the backup path using the backup-SRG concept to achieve 100% recovery performance. The proposed method is extended to support networks with a large number of SRGs by introducing a hierarchical SRG assignment technique. Through computer simulation on the NSF network model, we confirmed that the proposed method achieves 100% recovery performance assuming a single link failure at the expense of 28.6% extra wavelength resource compared to the non-backup method. The proposed method requires less than 56.3% wavelength resource than that of the protection scheme while keeping 100% recovery performance. The hierarchical SRG assignment technique reduces the number of backup-SRGs to be used in admission control at each node at the expense of very little throughput degradation. © 2003 IEEE.

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Trends in high-performance switching and routing technologies

Yamanaka Naoaki, Chen Thomas M., Stuttgen Heinrich J.

IEEE Communications Magazine 40 ( 11 ) 36 - 37 2002.11

ISSN 0163-6804

Demonstration of the Highly Reliable HIKARI Router Network Based on a Newly Developed Disjoint Path Selection Scheme

S. Okamoto, E. Oki, K. Shimano, A. Sahara, N. Yamanaka

IEEE Communication Magazine (IEEE Workshop on High Performance Switching and Routing) Vol.40 ( No.11 ) 52-59 2002.11

Research paper (international conference proceedings), Joint Work, Accepted

A Disjoint Path Selection Scheme With Shared Risk Link Groups in GMPLS Networks

YAMANAKA NAOAKI E. Oki, N. Matsuura, K. Shiomoto, N. Yamanaka

IEEE COMMUNICATIONS LETTER Vol.6 ( No.9 ) 406-408 2002.09

Research paper (conference, symposium, etc.), Joint Work, Accepted

A buffer management mechanism for achieving approximately fair bandwidth allocation in high-speed networks

Miyamura Takashi, Kurimoto Takashi, Nakagawa Kenji, Dhananjaya Prasad, Aoki Michihiro, Yamanaka Naoaki

IEICE Transactions on Communications E85-B ( 8 ) 1434 - 1441 2002.08

Research paper (scientific journal), Joint Work, ISSN 0916-8516

We propose a buffer management mechanism, called V-WFQ (Virtual Weighted Fair Queueing), for achieving an approximately fair allocation of bandwidth with a small amount of hardware in a high-speed network. The basic process for the allocation of bandwidth uses selective packet dropping that compares the measured input rate of the flow with an estimated fair share of bandwidth. Although V-WFQ is a hardware-efficient FIFO-based algorithm, it achieves almost ideal fairness in bandwidth allocation. V-WFQ can be implemented in the high-speed core routers of today's IP backbone networks to provide various high-quality services. We have investigated V-WFQ's performance in terms of fairness and link utilization through extensive simulation. The results of simulation show that V-WFQ achieves a good balance between fairness and link utilization under various simulation conditions.

Experimental 5-Tb/s Packet-by-Packet Wavelength Switching System Using 2.5-Gb/s x 8-l WDM Links

K. Yamakoshi, N. Matsuura, K. Nakai, E. Oki, N. Yamanaka, T. Ohyama, Y. Akahori

IEICE TRANSACTIONS on Communication Vol.E85-B ( No.7 ) 1293-1301 2002.07

Research paper (conference, symposium, etc.), Joint Work, Accepted

GMPLS-Based Photonic Multilayer Router (Hikari Router) Architecture: An Overview of Traffic Engineering and Signaling Technology

K. Sato, N. Yamanaka, Y. Takigawa, M. Koga, S. Okamoto, K. Shiomoto, E. Oki, W. Imajuku

IEEE Communication Magazine Vol.40 ( No.3 ) 96-101 2002.03

Research paper (conference, symposium, etc.), Joint Work, Accepted

Dynamic deficit roung-robin scheduling scheme for variable-length packets

YAMANAKA NAOAKI K. Yamakoshi, N. Nakai, E. Oki, N. Yamanaka

ELECTRONIC LETTERS Vol.38 ( No.3 ) 2002.01

Research paper (conference, symposium, etc.), Joint Work, Accepted

Packet-by-packet wavelength-routing interconnect technique for 5 Tbit/s switching system

N. Matsuura, K. Yamakoshi, E. Oki, N. Yamanaka , T. Ohyama, Y. Akahori

ELECTRONIC LETTERS Vol.38 ( No.2 ) 82-83 2002.01

Research paper (conference, symposium, etc.), Joint Work, Accepted

Next generation carriers internet backbone node architecture (MSN type-X)

Aoki M., Yamanaka N., Kurimoto T., Miyamura T., Nishikido J.

2002 Workshop on High-performance Switching and Routing, 2002 HPSR 156 - 160 2002

Research paper (international conference proceedings), Joint Work

Next generation carriers Internet backbone node architecture are proposed that offer sophisticated QoS support including real time voice, video streaming, and VPN. The backbone core node, MSN (multi-service network) Type-X, has 320 Gb/s throughput and IP V4/V6 dual stack forwarding capability and OC-192C full wire-rate forwarding performance. In addition, sophisticated DiffServ having 4096 virtual queue realizing full hardware is also proposed. In addition, Type-X has ATM emulation technique. Finally, the paper describes a high-reliability technique such as a newly structured non-stop software and firmware upgrade technique. This newly proposed technique and system offers the next generation, real time, high-QoS capability. © 2002 IEICE.

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An 80 Gb/s Optical I/O Interface ATM Switch MCM

R. Kawano, N. Yamanaka, E. Oki, K. Okazaki, A. Ohki

Electronics and Communications in Japan, Part 1 Vol.85 ( No.2 ) 61-68 2002

Research paper (conference, symposium, etc.), Joint Work

A heuristic multi-layer optimum topology design scheme based on traffic measurement for IP + photonic networks

Oki Eiji, Shiomoto Kohei, Okamoto Satoru, Imajuku Wataru, Yamanaka Naoaki

Optical Fiber Communication Conference 2022 104 - 105 2002

Research paper (international conference proceedings), Joint Work

On performance prediction of address lookup algorithms of IP routers through simulation and analysis techniques

Kawabe Ryo, Ata Shingo, Murata Masayuki, Uga Masanori, Shiomoto Kohei, Yamanaka Naoaki

2146 - 2151 2002

Many address lookup methods on the IP routers have been recently proposed to improve the packet forwarding capability; nevertheless, their performance prediction is very limited because of lack of considering actual traffic characteristics in their evaluations. It is necessary to consider actual traffic to predict more realistic performances on routers, specially in case of layers 3 and 4 switches whose performances are more influenced by flow characteristic. In this paper, we propose new methods for predicting the router's performance based on the statistical analysis of the Internet traffic. We also present an example of its application to the existing table lookup algorithm, and show that simulation results based on our method can provide accurate performance prediction.

Traffic engineering and signaling technologies in photonic-GMPLS-router networks

Yamanaka N., Okamoto S., Shiomoto K., Oki E., Imajuku W.

142 - 146 2002

This paper describes multilayer traffic engineering and signaling technologies in a photonic-GMPLS-router network. Multilayer traffic engineering, which yields the dynamic cooperation of IP and photonic layers, is described to provide IP services cost-effectively. To realize multilayer traffic engineering, we propose the OSPF extension, which advertises both the number of total wavelengths and the number of unreserved wavelengths, and the RSVP-TE extension, which realizes the least number of wavelength conversions. In addition, this paper presents a heuristic-based multilayer topology design scheme that uses IP traffic measurements in a generalized multiprotocol label switch (GMPLS). Our design scheme yields the optical label switch path (OLSP) network topology, i.e. OLSP placement, that minimizes network cost, in response to fluctuations in IP traffic demand. In other words, the OLSP network topology is dynamically reconfigured to match IP traffic demand. Networks are reconfigured by the proposed scheme so as to utilize the network resources cost-effectively. © 2002 IEICE.

Access to Document (DOI)

Active queue control scheme for achieving approximately fair bandwidth allocation

Miyamura Takashi, Kurimoto Takashi, Nakagawa Kenji, Dhananjaya Prasad, Aoki Michihiro, Yamanaka Naoaki

1269 - 1273 2002

We propose a buffer management mechanism, called V-WFQ (Virtual Weighted Fair Queueing), for achieving approximately fair bandwidth allocation with a small hardware amount in high-speed networks. The basic process for allocating bandwidth fairly uses selective packet dropping to compare the measured input rate of the flow with an estimated fair bandwidth share. Though V-WFQ is a hardware-efficient FIFO-based algorithm, it can achieve almost ideal fairness in bandwidth allocation. Simulation results show that V-WFQ achieves a good balance between fairness and link utilization under various simulation conditions.

MSN Type-X

Yamanaka Naoaki, Kurimoto Takashi, Miyamura Takashi, Aoki Michihiko

2095 - 2099 2002

Next generation Internet backbone node architectures are proposed that offer sophisticated QoS support including real time voice, videostreaming, and VPN. The backbone core node, named MSN (Multi-service network) Type-X, has 320 Gb/s throughput and IP V.4/V.6 dual stack forwarding capability. Note that, through the employment of state-of-the art VLSI technology, both V.4 and V.6, OC-192C full wire-rate forwarding performance is achieved for the first time. In addition, sophisticated DiffServ with programmable thousands of virtual queues is also proposed to realize a complete set of hardware. In addition, Type-X uses an ATM emulation technique that can into allow the new packet centric backbone to support conventional services. Finally, the paper describes high-reliability techniques such as newly structured service non-stop software and a firmware upgrade technique. These newly proposed techniques and systems will realize the next generation, real time, high-QoS capability, and VPN IP backbone network to be realized.

5-Tb/S electro-optical ATM switching system hardware components using small optical WDM packet-switched interconnection modules

Matsuura Nobuaki, Yamakoshi Kimihiro, Oki Eiji, Yamanaka Naoaki, Ohyama Takaharu, Akahori Yuji

300 - 304 2002

A 5-Tb/s asynchronous transfer mode (ATM) switching system called OPTIMA-2 (optically interconnected multi-stage ATM switch architecture ) that uses optical packet-by-packet switched wavelength division multiplexing (WDM) links for the intraswitch interconnections was experimentally described. The design, fabrication, and evaluation of the optical WDM interconnection modules for OPTIMA-2 were discussed. The feasibility of a multi Tb/s switching system was successfully demonstrated.

Multi-layer traffic engineering in photonic-GMPLS-router networks

Yamanaka Naoaki, Katayama Masaru, Shiomoto Kohei, Oki Eiji, Matsuura Nobuaki

2731 - 2735 2002

This paper describes multi-layer traffic engineering and signaling technologies in photonic-GMPLS-router networks. Multi-layer traffic engineering, which yields the dynamic cooperation of IP and photonic layers for providing IP services cost-effectively, is described. To realize multi-layer traffic engineering, we propose an OSPF extension that advertises both the number of total wavelengths and the number of unused wavelengths, and an RSVP-TE extension that minimizes the number of wavelength conversions needed. In addition, this paper presents a heuristic-based multi-layer topology design scheme that uses IP traffic measurements in a generalized multi-protocol label switch (GMPLS). Our design scheme yields the optical label switch path (OLSP) network topology, i.e. OLSP placement, that minimizes network cost, in response to fluctuations in IP traffic demand. In other words, the OLSP network topology is dynamically reconfigured to match IP traffic demand. Networks are reconfigured by the proposed scheme so as to utilize the network resources in the most cost-effective manner.

Performance prediction method for IP lookup algorithms

Kawabe R., Ata S., Murata M., Uga M., Shiomoto K., Yamanaka N.

111 - 115 2002

Many address lookup methods for use on IP routers to improve their packet-forwarding capability have been proposed. However, their performance prediction ability is poor because actual traffic characteristics are not considered in their evaluation processes. The actual traffic must be considered in order to predict router performance more accurately, especially for layer 3 and 4 address lookups, whose performances are more affected by the flow characteristics. We describe a method for predicting IP lookup algorithm performance that is based on statistical analysis of the Internet traffic. We present an example of its application to an existing IP lookup algorithm and show, based on simulation results, that our method can provide accurate performance prediction for IP lookup algorithms. © 2002 IEICE.

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Dynamic deficit round-robin scheduler for 5-Tb/s switch using wavelength routing

Yamakoshi K., Oki E., Yamanaka N.

204 - 208 2002

A dynamic deficit round-robin (DDRR) scheduling scheme for a 5-Tb/s switch is proposed. DDRR is a DRR-based packet scheduler and it can satisfy the max-min fair share. However, DRR cannot satisfy both high throughput and delay requirements. DDRR resolves the problem by changing the granularity for deficit counters according to the packet lengths at queue heads. Simulation results showing the efficiency of DDRR are presented and an implementation of DDRR for the switch is also described. © 2002 IEICE.

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A disjoint path selection scheme with SRLG in GMPLS networks

Oki E., Matsuura N., Shiomoto K., Yamanaka N.

88 - 92 2002

This paper proposes a disjoint path selection scheme for generalized multiprotocol label switching (GMPLS) networks with shared risk link group (SRLG) constraints. It is called the weighted-SRLG (WSRLG) scheme. It treats the number of SRLG members related to a link as part of the link cost when the k-shortest path algorithm is executed. In WSRLG, a link that has many SRLG members is rarely selected as the shortest path. Simulation results show that WSRLG finds more disjoint paths than the conventional k-shortest path algorithm. In addition, since WSRLG searches for the weight of the SRLG factor by using a binary search algorithm while satisfying the required number of disjoint paths between source and destination nodes so that the cost of a path set can be minimized, it can find the most cost-effective disjoint paths. © 2002 IEICE.

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A 100-Gb/s Throughput ATM Switch MCM with a 320-Channel Parallel Optical I/O Interface

YAMANAKA NAOAKI R. Kawano, N. Yamanaka, E. Oki, S. Yasukawa, K. Okazaki, A. Ohki, M. Usui, N. Sato, K. Katsura, Y. Ando, T. Kagawa, M. Hikita

IEEE TRANSACTIONS ON ADVANCED PACKAGEING Vol.24 ( No.1 ) 91-98 2001.02

Research paper (conference, symposium, etc.), Joint Work

次世代コアネットワークのメディアゲートウェイおよびコアノード技術

K. Kogure, N. Yamanaka, A Hayakawa

NTT技術ジャーナル ( No.64-68 ) 2001.01

Research paper (bulletin of university, research institution), Joint Work

Effective switching scheduling algorithm using concatenated data block to reduce guard-time for opt-electronic packet switch

Kurimoto T., Oki E., Nakai K., Yamanaka N.

985 - 989 2001

A new scheduling algorithm that concatenates data blocks to increase switching throughput is proposed. The algorithm controls the degree of concatenation and reduces the number of switching instances to improve switch utilization. The switch architecture uses a virtual output queue switching architecture where the core switch fabric is an optical matrix switch. The optical matrix switch requires the guard-time overhead needed for optical switch control. By reducing the number of switching instances, guard-time overhead can be reduced and switch utilization can be improved. Computer simulations show that efficiency is dramatically increased and that fairness in terms of data throughput among output ports is achieved.

5-Tb/s frame-based ATM switching system using 2.5-Gb/s × 8-λ optical switching technique

Yamakoshi Kimihiro, Nakai Kohei, Matsuura Nobuaki, Oki Eiji, Yamanaka Nabuaki

88 - 92 2001

This paper describes the hardware architecture and performance of a 5-Tb/s frame-based (FB) ATM switching system OPTIMA-2 (OPTically Interconnected Distributed Multi-stage TB/s-ATM switching Network Architecture -2). First, we describe the switch architecture, which is a non-blocking 3-stage switch using optical wavelength division multiplexing (WDM) and dynamic bandwidth sharing technique. Variable-length FB-ATM cells, which can encapsulate IP packets, can be switched while keeping throughput fairness. Second, we propose a scheduling technique for variable-length packets used in the WDM system which selects packets from the eight wavelengths. We show that the scheduling technique can keep fairness and a small delay for variable-length packets. A pipelined-scheduling technique for variable-length packets is also proposed for a high-speed and large-capacity switching system.

WDM optical switching to achieve 5 Tb/s throughput

Matsuura Nobuaki, Yamakoshi Kimihiro, Oki Eiji, Nakai Kohei, Yamanaka Naoaki, Ohyama Takaharu, Akahori Yuji

2083 - 2087 2001

This paper describes a Wavelength-Division-Multiplexing (WDM) optical switching technique that achieves 5-Tb/s switch throughput. This technique is employed in our previously described OPTically Interconnected Distributed Multi-stage Tb/s-ATM switching Network Architecture, called OPTIMA-2. This is a scalable and non-blocking 3-stage switch employing optical WDM and dynamic bandwidth sharing. An inter-stage, cell-based WDM switch is fabricated in combination with field programmable gate arrays (FPGAs) and 2.5-Gb/s 8-wavelength optical interconnection modules. Experimental results from a 5-Tb/s switching system are introduced.

5-Tbit/s frame-based ATM switching system using 2.5-Gbit/s × 8 optical WDM links

Yamakoshi K., Nakai K., Matsuura N., Oki E., Kawano R., Yamanaka N.

3117 - 3121 2001

The hardware architecture of a 5-Tbit/s FB (Frame-Based) ATM switching system OPTIMA-2 (OPTically Interconnected Distributed Multi-stage Tbit/s-ATM switching Network Architecture -2) is described. OPTIMA-2 has a non-blocking 3-stage switch architecture employing optical WDM links and dynamic bandwidth sharing. The WDM links are composed of a sender port, wavelength AWG router and receiver port. The sender port at the output port of a switch-element allocates a packet to one of eight WDM wavelengths and transmits it. The receiver port receives packets of all eight wavelengths via the wavelength AWG router and merges them at an input port of the next-stage switch-element. Total bandwidth is limited to 10 Gbit/s, but the maximum bandwidth of each wavelength is designed to be 2.5 Gbit/s to prevent the statistical multiplexing gain from falling. A scheduler, which selects variable-length packets from the eight wavelengths, can keep fairness and a small delay. The bandwidth of each wavelength is changed dynami cally by the system so that the traffic in each wavelength is equally distributed among the total bandwidth. In OPTIMA-2, variable-length FB-ATM cell, which is familiar with the IP packet, can be switched while keeping the throughput fairness.

次世代コアネットワークのメディアゲートウェイおよびコアノード技術

N. Yamanaka, K. Yamakoshi, R. Kawano

NTT R&D Vol.49 ( No.12 ) 698-705 2000.12

Research paper (bulletin of university, research institution), Joint Work

OPTIMA: Scalable, Multi-Stage, 640-Gbit/s ATM Switching System Based on Advanced Electronic and Optical WDM Technologies

N. Yamanaka, E. Oki, S. Yasukawa, R. Kawano, K. Okazaki

IEEE Trans on Communications Vol.E83 ( No.7 ) 1488-1496 2000.07

Research paper (conference, symposium, etc.), Joint Work, Accepted

An 80 Gb/s Optical I/O Interface ATM Switch MCM

R. Kawano, N. Yamanaka, E. Oki, K. Okazaki, and A. Ohki

Trans of IEICE of Japan Vol.J83-B ( No.4 ) 471-478 2000.04

Research paper (conference, symposium, etc.), Joint Work, Accepted

Very Compact Scalable 80 Gbit/s ATM Switching Module

E. Oki, N. Yamanaka, K. Okazaki, R. Kawano and Y. Ohtomo

Trans of IEICE of Japan Vol.J83-B ( No.4 ) 490-500 2000.04

Research paper (conference, symposium, etc.), Joint Work, Accepted

A Distributed Traffic Control Scheme for Large-Scale Multi-Stage ATM Switching System

K. Shiomoto, E. Oki, N. Yamanaka

IEICE TRANSACTIONS on Communication Vol.E83-B ( No.2 ) 231-237 2000.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

Performance of Scalable-Distributed-Arbitration ATM Switch Supporting Multiple QoS Classes

E. Oki, N. Yamanaka, M. Nabeshima

IEICE TRANSACTIONS on Communication Vol.E83-B ( No.2 ) 204-213 2000.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

The i-QOCF (Iterative Quasi-Oldest-Cell-First) Scheduling Algorithm for Input-Queued ATM Switches

M. Nabeshima, N. Yamanaka

IEICE TRANSACTIONS on Communication Vol.E83-B ( No.2 ) 182-189 2000.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

Scalable multi-stage cell-switching architecture

Yasukawa Seisho, Oki Eiji, Nakai Kohei, Yamanaka Naoaki

NTT R and D 49 ( 12 ) 706 - 712 2000

ISSN 0915-2326

An architecture is described for a switch that is suitable for future large-scale packet-convergence networks. This optically interconnected multi-stage ATM switch architecture (OPTIMA) is a multi-stage switch architecture, and an OPTIMA switch can perform two types of QoS switching. The architecture is scalable - switching capacity can be expanded by interconnecting identical unit switches, without causing degradation in switching performance, because of the switch's route-control mechanism for high-priority traffic and its self-load balancing mechanism for low-priority traffic. Analysis and simulation demonstrated that an OPTIMA switch has high-performance switching capability. Also described is the hardware architecture for the 640 Gbit/s OPTIMA switching system. The OPTIMA switch is suitable for use as a backbone node in future packet-convergence networks.

ATM flow control based on rate prediction with extrapolation under WAN environment

Hasegawa Haruhisa, Yamanaka Naoaki, Shiomoto Kohei

Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi) 83 ( 7 ) 1 - 14 2000

ISSN 8756-6621

The adaptive rate control technique AREX (Adaptive Remote rate control based on Extrapolation) is proposed, which realizes an access to a high-speed bandwidth and a high utilization rate without increase of required buffer amount and degradation of the transfer characteristics, even in an ATM (Asynchronous Transfer Mode) network with a long delay, by carrying out prediction of congestion based on periodically reported information on the utilization rate. In the AREX method, the downstream node (Obsv node) without a rate modification capability observes the utilization rate of the output link and informs the upstream node (Cntl node) with a rate control capability. Based on the information, the Cntl node controls the output rate dynamically. In the conventional feedback rate control, only past information can be obtained due to propagation delay, and the information is given only at an appropriate notification interval. Therefore, as the network size is increased, the necessary amount of buffers is increased, or the response speed for the bandwidth modification request from users needs to be reduced. However, since the worst traffic is estimated from the notification information in the AREX method, a safe rate control can be realized even if the notification is delayed and is given intermittently. Also, by regulating the rate enhancement ratio as an appropriate increasing function, quick access to a large bandwidth can be realized at low load, and a high congestion control effect is achieved at high load. © 2000 Scripta Technica.

High-speed switch system for multimedia service nodes

Yamanaka Naoaki, Yamakoshi Kimihiro, Kawano Ryusuke

NTT R and D 49 ( 12 ) 698 - 705 2000

ISSN 0915-2326

Breakthrough technologies are described for switching hardware and system integration that will enable the development of a Tbit/s-class switching system for multi-service backbone networks. Also described is a switching architecture that is familiar with IP traffic while retaining the advantages of a conventional ATM switch. Following papers describe the newly developed 640-Gbit/s OPTIMA (OPTically Interconnected Multi-stage ATM switch architecture) switching system, including the 640-Gbit/s switching system architecture, 80-Gbit/s switch-element architecture, hardware architecture, and packaging technique.

A 10-Gb/s (1.25 Gb/s x 8) 4 x 2 0.25-mm CMOS/SIMOX ATM Switch Based on Scalable Distributed Arbitration

E. Oki, N. Yamanaka, Y. Ohtomo, K. Okazaki, R. Kawano

EEE JOURNAL OF SOLID-STATE CIRCUITS Vol.34 ( No.12 ) 1921-1934 1999.12

Research paper (conference, symposium, etc.), Single Work, Accepted

80 Gbit/s ATM switch MCM based on multilayer ceramic technology

K. Okazaki, N. Sugiura, A. Harada, N. Yamanaka, and E. Oki

ELECTRONICS LETTERS Vol.35 ( No.24 ) 2074-2076 1999.11

Research paper (conference, symposium, etc.), Joint Work, Accepted

Scalable frame-synchronisation circuit for highly parallel optical interconnections

K. Yamakoshi, R. Kawano, N. Yamanaka

ELECTRONICS LETTERS Vol.35 ( No.24 ) 2117-2118 1999.11

Research paper (conference, symposium, etc.), Joint Work, Accepted

Dynamic Burst Transfer Time-Slot-Base Network

K. Shiomoto, N. Yamanaka

IEEE Communications Magazine Vol.37 ( No.10 ) 88-96 1999.10

Research paper (conference, symposium, etc.), Joint Work, Accepted

Integrated Physical and Logical Layer Design of Multimedia ATM Networks

S. D. Moitra, E. Oki, N Yamanaka

IEICE TRANSACTIONS on Communications Vol.E82-B ( No.9 ) 1531-1540 1999.09

Research paper (conference, symposium, etc.), Joint Work

New Scheduling Mechanisms for Achieving Fairness Criteria (MCR Plus Equal Share, Maximum of MCR or Max-Min Share

M. Naabeshima, N. Yamanaka

Trans of IECE of Japan Vol.E82-B ( No,6 ) 962-966 1999.06

Research paper (conference, symposium, etc.), Joint Work, Accepted

Scalable 10 Gbit/s 4 x 2 0.25μm CMOS/SIMOX ATM switch LSI circuit LSI circuit based on distributed contention control

E. Oki, . Yamanaka, K. Okazaki, Y. Ohtomo

ELECTRONIC LETTERS Vol.35 ( No.9 ) 1-2 1999.04

Research paper (conference, symposium, etc.), Joint Work

Performance Evaluation of High-Speed Admission Control in ATM Networks Based on Virtual Request Generation

E. Oki, N. Yamanaka

IEICE TRANSACTIONS on Communications Vol.E82-B ( No.3 ) 473-480 1999.03

Research paper (conference, symposium, etc.), Joint Work, Accepted

A Dynamic Reference Single-Ended ECL Input Interface Circuit for MCM-Based 80-Gbps ATM Switch

R. Kawano, N. Yamanaka, E. Oki, T. Kawamura

IEICE TRANSACTIONS on Communications vol.E82-c ( No.3 ) 519-525 1999.03

Research paper (conference, symposium, etc.), Joint Work, Accepted

Scalable 3-Stage ATM Switch Architecture Using Optical WDM Grouped Links Based on Dynamic Bandwidth Sharing

K. Nakai, E. Oki, N. Yamanaka

IEICE TRANSACTIONS on Communications E82-B ( 2 ) 265-270 1999.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

DTM: Dynamic Transfer Mode Based on Dynamically Assigned Short-Hold Time-Slot Relay

N. Yamanaka, K. Shiomoto

IEICE TRANSACTIONS on Communications Vol.E82-B ( No.2 ) 439-446 1999.02

Research paper (conference, symposium, etc.), Joint Work, Accepted

Integrated physical and logical layer design of multimedia ATM networks

Moitra Soumyo D., Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E82-B ( 9 ) 1531 - 1540 1999

ISSN 0916-8516

This letter proposes an integrated approach to multimedia ATM network design. An optimization model that combines the physical layer design with the logical layer design is developed. A key feature of the model is that the objective to be maximized is a profit function. It includes more comprehensive cost functions for the physical and logical layers. A simple heuristic algorithm to solve the model is presented. It should be useful in practice for network designers and operators. Some numerical examples are given to illustrate the application of the model and the algorithm.

A Very-Compact 10-Gb/s Optical Module for 640-Gb/s WDM Interconnection

R. Kawano, S. Yasukawa, N. Yamanaka

Japan Institute of Electronics Packaging Vol.2 ( No.7 ) 552-555 1999

Research paper (conference, symposium, etc.), Joint Work, Accepted

An 80-Gbit/s ATM Switch MCM

K. Okazaki, N. Sugiura, A. Harada, T. Kishimoto, E. Oki, N. Yamanaka

Japan Institute of Electronics Packaging Vol.2 ( No.7 ) 556-560 1999

Research paper (conference, symposium, etc.), Joint Work, Accepted

Scalable 640-Gbit/s ATM switching system with self-load balancing mechanism

Yasukawa S., Yamanaka N., Oki E., Kawano R., Okazaki K., Santoso D.

1412 - 1417 1999

A T-bit/s ATM switching system architecture, called the OPTIMA switch, is proposed. This system is scalable and quasi-non-blocking by virtue of its self-load-balancing mechanism and high-speed interconnection effect. The self-load-balancing mechanism prevents overloading in the switch by automatically checking and balancing the internal load. An experimental 640-Gbit/s ATM switching system was developed and tested; the basic parts of switching function are demonstrated. The switching system was fabricated using advanced 0.25 mm-CMOS devices, high-density MCM technologies, and optical WDM interconnection technologies. The WDM interconnection system, a key part of the scalable 640-Gbit/s OPTIMA switching system, interconnects 80-Gbit/s switching modules using WDM routing technology. The developed 640-Gbit/s switching system can be applied in the creation of a platform for future high-speed multimedia network.

100-Gb/s throughput ATM switch MCM with a 320-channel parallel optical I/O interface

Kawano Ryusuke, Yamanaka Naoaki, Oki Eiji, Yasukawa Seisho, Okazaki Katsuhiko, Ohki Akira, Usui Mitsuo, Sato Nobuo, Katsura Kosuke, Ando Yasuhiro, Kagawa Toshiaki, Hikita Makoto

753 - 758 1999

For an ATM switch system, we have developed a 100-Gb/s I/O throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25 μm CMOS ATM switch LSIs and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using 8 optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from DC to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface.

New transfer methods for client-server traffic in ATM networks

Lecumberri David, Siu Kai Yeung, Narvaez Paolo, Nabeshima Masayoshi, Yamanaka Naoaki

1345 - 1349 1999

This paper presents new transfer schemes for client-server traffic over ATM networks, with the objective of achieving a bounded transmission time of about one second for as many connection requests as possible. We evaluate via simulations the performance of these new schemes in terms of network utilization, cell loss ratio, and transmission time. The simulation results show that these schemes provide effective means of supporting client-server traffic with quasi-real time requirements.

OPTIMA

Yamanaka Naoaki, Kawano Ryusuke, Oki Eiji, Yasukawa Seisho, Okazaki Katsuhiko

26 - 33 1999

A 640 Gb/s high-speed ATM Switching System that is based on the technologies of advanced MCM-C, 0.25μm CMOS and optical WDM interconnection is fabricated for future B-ISDN services. A 40-layer, 160 mm × 114 mm Ceramic MCM realizes the basic ATM switch module with 80 Gb/s throughput. The basic unit ATM switch MCM-C consists of an 8-chip advanced 0.25 μm CMOS VLSI and 32 chip I/O bipolar VLSIs. The MCM employs a 40 layer, very-thin-layer ceramic MCM and a uniquely structured closed loop type liquid cooling system is adopted to cope with the MCM's high-power dissipation of 230 W. The MCM is mounted on a 32 cm × 50 cm mother board. A three-stage ATM switch is realized by optical WDM interconnection between the high-performance MCMs. For WDM interconnection, newly developed compact size 10 Gb/s, 8 WDM optical transmitters and receivers are used. An optical WDM router based on an AWG (Arrayed Waveguide Router) is used for mesh interconnection of boards. The optical WDM interconnect has 640 Gb/s throughput and easy, simple interconnection. The system, MCM, and Optical WDM interconnection will be applied to future B-ISDN backbone networks.

Scalable-distributed-arbitration ATM switch supporting multiple QoS classes

Oki Eiji, Yamanaka Naoaki, Nabeshima Masayoshi

319 - 324 1999

This paper proposes a multi-QoS scalable-distributed-arbitration (MSDA) ATM switch that supports both the high-priority class and the low-priority class under the head-of-line-priority discipline. It has a crosspoint buffer and a transit buffer, each consisting of a high-priority buffer and a low-priority buffer. Arbitration is executed between the crosspoint buffer and the transit buffer in a distributed manner. The MSDA switch extends the advantage of our previously proposed single-QoS scalable-distributed-arbitration (SSDA) switch. It is expandable while permitting high output-line speeds due to the distributed arbitration. The SSDA switch has a problem when its delay-time-based cell selection mechanism is applied to the low-priority class due to the limitation of the number of bits for the delay measure in the cell overhead. We solved this problem by introducing a distributed-ring-arbiter-based cell selection mechanism at each crosspoint for the low-priority class. The low-priority transit buffer at each crosspoint has virtual queues in accordance with the upper input ports. Cells for the low-priority class are selected by distributed ring arbitration among the low-priority crosspoint buffer and the virtual queues at the low-priority transit buffer. Simulations confirm that the MSDA switch ensures fairness in terms of delay time for the high-priority class, while it ensures fairness in terms of throughput for the low-priority class.

Distributed traffic control method for Tbit/s multi-stage ATM switching systems

Nakai Kohei, Oki Eiji, Yamanaka Naoaki

109 - 114 1999

This paper proposes a distributed traffic control method for large multi-stage ATM switching systems. In the proposed switching system, each port of the basic switches has its own traffic monitor, and each line unit (LU) periodically obtains congestion information about available paths from OAM cells in order to route a new virtual circuit independently. The performance of the proposed system depends on the interval between OAM cells. We show how an appropriate interval can be determined in order to maximize the number of user cells that each LU can send.

Nonblocking multi-stage ATM switch using cell-based routing with a hierarchical cell sorting mechanism

Santoso David, Yasukawa Seisho, Yamanaka Naoaki, Miki Tetsuya

265 - 270 1999

A multi-stage switching architecture is a key technology for budding a high-speed ATM switching system. An effective way to make a multi-stage switch nonblocking is to use cell-based routing. However, cell-based routing may cause cell-sequence disorder at the output of the switching fabric. This paper proposes a hierarchical cell-sorting (HCS) switch architecture, which is a nonblocking multi-stage AIM switch using cell-based routing technology. Each basic HCS switch performs cell sorting at every crosspoint, based on timestamp information in the cell-header. This arranges the cells in sequence at the output of each basic HCS switch, since the crosspoints are hierarchically interconnected from the input port to the output port of a basic HCS switch. A multi-stage HCS switch is constructed by interconnecting the input and output lines of these basic HCS switches in a hierarchical manner. Thus, the cell sequence in each final output of the multi-stage switch is preserved in a hierarchical manner. In this way, cell-based routing with 100% throughput is achieved, with no need for internal speed-up techniques.

i-QOCF (iterative quasi-oldest-cell-first) algorithm for input-queued ATM switches

Nabeshima Masayoshi, Yamanaka Naoaki

25 - 30 1999

This paper proposes a new scheduling algorithm for input-queued ATM switch, called iterative quasi-oldest-cell-first (i-QOCF) algorithm. In i-QOCF, each input port and each output port maintains its own list. The length of the list can be N, 2×N, ..., B×N, where B is the size of the buffer that queues cells destined for an output port. The list maintained by an input port contains the identifiers of those output ports to which that input port will send a cell. The list maintained by an output port contains the identifiers of input ports which have a cell destined for that output port. We show the performance of i-QOCF and results in which we compare i-QOCF with i-OCF in terms of cell delay time. We find that an input-queued ATM switch with i-QOCF and virtual output queue (VOQ) can achieve 100% throughput for independent arrival processes. The 3-QOCF is enough to achieve convergence during one cell time. If we use a 3-QOCF in which the list length is 3×N, then its cell delay time performance is almost the same as that of a 4-OCF.

A dynamic reference single-ended ECL input interface circuit for MCM-Based 80-Gbps ATM switch

Kawano Ryusuke, Yamanaka Naoaki, Oki Eiji, Kawamura Tomoaki

IEICE Transactions on Electronics E82-C ( 3 ) 519 - 524 1999

ISSN 0916-8524

A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.

80-Gbit/s MCM-C technologies for high-speed ATM switching systems

Okazaki Katsuhiko, Sugiura Nobuaki, Harada Akio, Yamanaka Naoaki, Oki Eiji

284 - 288 1999

Breakthrough technologies for the high-performance electrical ATM switching system

Yamanaka N.

Journal of Lightwave Technology 16 ( 12 ) 2181 - 2190 1998.12

ISSN 0733-8724

A high-performance electrical asynchronous transfer mode (ATM) switching system is described with the goal of Tb/s ATM switching. The flrst step system was to use advanced Si-Bipolar very large scale integrated (VLSI) technologies and the multichip technique. 1.0 μm Bipolar SST technologies and Cu-Polyimide multilayer MCM realized a 160 Gb/s through-put ATM system. The performance limitations of the 160 Gb/s system were power supply/cooling and module interconnection. The new ATM switching system, named OPTIMA-1, adopted optical interconnection/distribution to overcome the limitations and achieve 640 Gb/s. The system uses high-performance complementary metal-oxide-semiconductor (CMOS) devices and optical wavelength division multiplexing (WDM) interconnection. Combining OPTIMA-1 with optical cell-by-cell routing functions, i.e., photonic packet routing, can realize variable bandwidth links for 5 Tb/s ATM systems. This paper flrst reviews high-performance electrical ATM (packet) switching system architecture and hardware technologies. In addition, system limitations are described. Next, the important breakthrough technology of optical WDM interconnection is highlighted. These technologies are adopted to form OPTIMA-1, a prototype of which is demonstrated. The key technologies of the system are advanced 80 Gb/s CMOS/MCM, electrical technologies, and 10 Gb/s, 8 WDM, 8 × 8 optical interconnection. Details of implementation technologies are also described. Optical cell-by-cell (packet-by-packet) routing is now being studied. From the architectural viewpoint, dynamic link bandwidth sharing will be adopted. In addition, an AWG that performs cell-by-cell routing and a distributed large scale ATM system are realized. Optical routing achieves the 5 Tb/s needed in future B-ISDN ATM backbone systems.

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An admission control scheme based on measurements of instantaneous utilization

Shiomoto Kohei, Yamanaka Naoaki

Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi) 81 ( 11 ) 1 - 12 1998.11

ISSN 8756-6621

We propose a lightweight measurement-based admission control method. The instantaneous rate estimated with a low-pass filter (LPF) and the maximum instantaneous rate (MIR) observed during the monitoring period is used to determine the residual bandwidth. Hence, we call this the MIR method. We demonstrate the use of the LPF design method to obtain the instantaneous rate accurately. We develop an analytical model and investigate the performance of the MIR method. We compare the MIR method to a conventional measurement-based admission control method with respect to bandwidth efficiency and implementation complexity. We demonstrate that the MIR method can be implemented with a simple circuit while achieving a bandwidth efficiency that is comparable to the conventional method. © 1998 Scripta Technica.

Compact 10Gbit/s optical transceiver/receiver set with novel cooling structure for 640Gbit/s WDM interconnection

Kawano R., Yamanaka N., Yasukawa S., Okazaki K.

Electronics Letters 34 ( 19 ) 1876 - 1877 1998.09

ISSN 0013-5194

Dynamic reference single-ended ECL input interface circuit for 80Gbit/s MCMs

Kawano R., Yamanaka N., Oki E., Kawamura T.

Electronics Letters 34 ( 17 ) 1641 - 1643 1998.08

ISSN 0013-5194

ALPEN

Yamanaka Naoaki, Shiomoto Kohei, Hasegawa Haruhisa

Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi) 81 ( 8 ) 19 - 30 1998.08

ISSN 8756-6621

This paper proposes a new network architecture, ALPEN (ATM multi-protocol emulation network), based on a new concept for realizing full-scale multimedia communication networks. In ALPEN, various communication protocols, such as ABR (available bit rate), FRM (fast resource management), or SHM (short hold mode), can be handled using a single, simple transit network. Each protocol is emulated at the edge node of the WAN (wide area network), and the status of the transit network is checked by periodically examining the residual bandwidth information of each route. ALPEN is a cost-effective and flexible network architecture because it enables us to implement new services or protocols easily by modifying only the edge nodes. In ALPEN, since individual edge nodes periodically obtain the bandwidth information, it is possible to respond promptly to a user's request to change his bandwidth. In particular, when the network's RTT (round trip time) is long, as in a WAN, ALPEN is a promising way to resolve the problem of performance responsibility. Although each edge node periodically checks the disperse information to all destination edge nodes on a residual bandwidth, the information might be old, or it might be necessary to process it independently at the multiple edge nodes. There-fore, the parameter of "effective residual bandwidth" is estimated by a statistical method; the estimation also considers that bandwidth resources may be overbooked by multiple edge nodes. The statistical method is described in this paper. The ALPEN introduced in this paper is an effective architecture that makes it possible to implement new or various unforeseeable network services in the future multimedia era, in which various services and protocols may exist simultaneously. © 1998 Scripta Technica.

Feedback rate control with congestion prediction by edge nodes in ATM-WAN

Hasegawa Haruhisa, Yamanaka Naoaki, Shiomoto Kohei

1541 - 1546 1998

This paper proposes a new adaptive remote rate control based on extrapolation called AREX. AREX does not require a high-speed switching node to have high calculation load. Consequently, transit switches with high-speed interface do not always need to have high calculation power. As a result rate control can be implemented easily in a WAN. AREX reduces the major problems of feedback rate control, inaccuracy of feedback information and large necessary buffer space caused by long propagation delay. In AREX, a high-speed transit switching node only observes the link utilization ratio of the output VP and notifies it to upstream nodes. Local switching nodes with spare calculation power calculate and control the output rate of each VC. Because the admissible cell rate of each VC is calculated by local switches, ABR service can be emulated there. This paper describes the mechanisms of AREX and discusses the function form that determines its characteristics. AREX tries to converge utilization to the target value. The relationship between target value and overload probability is clarified for network management. The performance of ABR emulated by AREX is evaluated by computer simulation. The results show that AREX provides high throughput and requires less buffer capacity even in a network with long propagation delay.

New scheduling mechanisms which efficiently utilize policing for GFR service

Nabeshima Masayoshi, Yamanaka Naoaki, Hasegawa Haruhisa

80 - 85 1998

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10-Gb/s palm-size optical transceiver/receiver set with novel cooling structure for WDM sub-Tb/s ATM switch system

Kawano Ryuusuke, Yamanaka Naoaki, Yasukawa Seishou, Okazaki Katsuhiko

839 - 843 1998

We have developed compact 10-Gb/s optical transceiver and receiver modules for a WDM sub-Tb/s ATM switch system. Each module has a cooling part whose structure is based on a high-performance heat transfer device and micro-fans. Instead of a conventional radiation fin, a high-performance device is used to conduct heat from heat sources, such as a laser, to the fin inside the duct on the end of the module, where it is radiated by push-pull micro-fans. Because the conventional cooling structure based on straight fin occupies a larger volume, it is not suitable for high-density arrangement. Our cooling system achieved a heat resistance value of 1.8 °C/W, which was sufficient to stabilize the operation of the laser unit. This cooling structure enables a compact structure to handle high-density heat generation. The power dissipations of the TX and RX are 9.65 and 22.5 W, respectively. The TX and RX modules are the same size: 80×120×20 mm. Measurements show that these optical modules can operate stably without any additional cooling systems even in the switching unit.

Tandem-crosspoint ATM switch with input and output buffers

Oki Eiji, Yamanaka Naoaki

IEEE Communications Letters 2 ( 7 ) 189 - 191 1998

ISSN 1089-7798

This letter proposes a high-speed input and output buffering asynchronous transfer mode (ATM) switch, named the tandem-crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes, which are connected in tandem at every crosspoint. The TDXP switch does not increase the internal line speed in eliminating head-of-line (HOL) blocking. In addition, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. It is shown that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput.

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Advanced atm switching system hardware technologies based on mcm-d for atm line interface circuits

Kawamura Tomoaki, Yamanaka Naoaki, Kaizu Katsumi

IEICE Transactions on Communications E81-B ( 2 ) 482 - 487 1998

ISSN 0916-8516

This paper describes advanced ATM switching system hardware that uses a high-performance and cost-effective MCM-D module as an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size is reduced to 50.8mm x 50.8mm. This is 40% ofthat (100mm x 65mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a highperformance ASIC with a high-speed (access time 20ns) and large-capacity (l MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module is mounted on an ATM line interface circuit, and realizes 150 Mbit/s throughput ATM-layer functions (header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to advanced ATM switching systems.

Architectural choices in large scale ATM switches

Turner Jonathan, Yamanaka Naoaki

IEICE Transactions on Communications E81-B ( 2 ) 120 - 136 1998

ISSN 0916-8516

The rapid development of Asynchronous Transfer Mode technology in the last 10-15 years has stimulated renewed interest in the design and analysis of switching systems, leading to new ideas for system designs and new insights into the performance and evaluation of such systems. As ATM moves closer to realizing the vision of ubiquitous broadband ISDN services, the design of switching systems takes on growing importance. This paper seeks to clarify the key architectural issues for ATM switching system design and provides a survey of the current state-of-the-art.

Tb/s WDM interconnection system with pocket-size 10 Gb/s transmitter/receiver module and AWG router

Yasukawa S., Yamanaka N., Kawano R., Takeuchi H., Kuwano S.

575 - 576 1998

A Tb/s WDM interconnection system has been developed that utilizes a newly developed pocket-size 10-Gb/s transmitter/receiver module and wide-channel-spacing arrayed waveguide filter (AWGF). This system has 622-Mb/s ATM cell formats and can be applied to a Tb/s ATM switching system. The developed system uses eight different wavelength 10-Gb/s multiple quantum well modulator (MQW) integrated DFB lasers and one 8×8 optical router AWGF with 525-GHz-channel spacing. High-speed response and stable performance over a wide temperature range have been confirmed.

User-programmable flexible ATM network architecture, active-ATM

Yamanaka Naoaki, Oki Eiji, Hasegawa Haruhisa, Chen Thomas M.

IEICE Transactions on Communications E81-B ( 11 ) 2233 - 2236 1998

ISSN 0916-8516

This article proposes active-ATM, a flexible, simple and cost-effective ATM-WAN architecture that can handle multiple user-customized ATM-layer protocols, such as ABR and ABT, by using a simple universal ATM transit network. The proposed active-ATM architecture enables the construction of flexible networks that can evolve easily. With active-ATM and the ATM multi-protocol emulation network architecture called ALPEN, it is easy to implement new ATM-layer protocols by using user-created programs called active-program capsules that modify only the edge nodes. Because these user-sent program capsules can be used to quickly customize the edge nodes, there is no waiting for standardization and implementation of new services. The ATM-layer protocols are emulated only at the edge nodes, making the transit network independent of customer ATM-layer protocols. The active-ATM edge node is based on the flexible programmable node architecture called PUN (programmable unified node). The PUN is a platform for user-programmable ATM-layer services; it is achieved by using programmable devices, such as FPGAs and DSPs. An prototype system has demonstrated the flexibility of the resulting ATM network. The active-ATM architecture is an efficient approach to implementing multimedia, multi-protocol ATM services in an ATM WAN.

Impact of Multimedia Traffic Characteristics on ATM Network Configuration

Oki Eiji, Yamanaka Naoaki

Journal of Network and Systems Management 6 ( 4 ) 377 - 398 1998

ISSN 1064-7570

This paper proposes a new topological design method, named BXCQ, which optimizes logical network configuration while guaranteeing Quality-of-Service (QoS) requirements for each service class in an ATM network. The BXCQ method determines the optimum logical network topology associated with each service class so as to minimize network cost. In our previously proposed Full-Net architecture these different logical topologies can be suitably mapped at the same time on the same ATM physical network by using the Virtual Channel Handler (VCH) to create different logical interconnection networks. The BXCQ method allows us to clarify the relations between multimedia traffic characteristics and desirable logical network configurations in Full-Net. Evaluation results suggest that a service class that is bursty, delay tolerant, and cell loss sensitive with small demand should be supported by a loop-like topology. This study will be useful for designing flexible and cost-effective multimedia networks that can also adapt to not-yet-known services.

Flexible hardware design methodology for high-performance atm switching system using real-time emulation technique

Matsumura Tsuneo, Yamanaka Naoaki, Yamaguchi Ryoichi, Ishikawa Keiji

IEICE Transactions on Communications E81-B ( 2 ) 466 - 471 1998

ISSN 0916-8516

In the first stage of ATM switching system development, the specifications are sometimes changed in order to match revisions in ITU standards. Fatal problems due to specification changes and unexpected bugs force ASIC redesign and subsequent debugging is seriously restricted. These situations demand the introduction of new hardware design methodologies. This paper proposes a flexible hardware design methodology, based on a novel real-time emulation technique, suitable for large-scale high-speed communication switching systems. The emulation technique offers desirable system performance without Application Specific Integrated Circuit (ASIC) fabrication by using commercial Field Programmable Gate Arrays (FPGAs) along with many simply-structured high-speed interconnect switch devices for multiple FPGA connection. This technique suits line interface units (LUs) that have ASICs operating at about 20 MHz; each LU employs an LU board and emulation boards, both of which have hierarchical structures with sub-boards. The emulation boards are indispensable for realizing prototype systems rapidly and dealing with specification changes. Different types of LUs can be realized by mounting different sub-boards to the common LU board. Each emulation board is attached to the LU board by the same connector used for LU sub-board mounting. Therefore, the proposed structure has the advantage of utilizing a common LU board for system emulation as well as permitting the development of practical systems. To suppress undesirable multiple FPGA partitioning, we propose the emulation board architecture that has two types of sub-boards, each of which carries a different type of FPGA. We produced some portions of the proposed LU and tested the nearly 20 MHz real-time emulation of a complicated ASIC designed to realize ATM cell header conversion functions. The results of multiple FPGA partitioning on the emulation board suggest that the proposed design methodology will yield economic systems that can be freely modified to overcome hardware bugs and comply with future ITU standards.

High-speed connection admission control in ATM networks by generating virtual requests for connection

Oki Eiji, Yamanaka Naoaki

295 - 299 1998

This paper proposes a high-speed connection admission control scheme, named PERB CAC (CAC based on Prior Estimation for Residual Bandwidth). This scheme estimates the residual bandwidth in advance by generating a series of virtual requests for connection. When an actual connection request occurs, PERB CAC can instantaneously judge if the required bandwidth is larger than the estimated residual bandwidth, so the connection set-up time can be greatly reduced. Therefore, PERB CAC can realize high-speed connection set-up.

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A simple bandwidth management strategy based on measurements of instantaneous virtual path utilization in ATM networks

Shiomoto Kohei, Chaki Shinichiro, Yamanaka Naoaki

IEEE/ACM Transactions on Networking 6 ( 5 ) 625 - 634 1998

ISSN 1063-6692

A new connection admission control method based on actual virtual path traffic measurements is proposed to achieve high bandwidth efficiency for various types of traffic. The proposed method is based on the measurement of instantaneous virtual path utilization, which is defined as the total cell rate of the active virtual channels normalized by the virtual path capacity. A low-pass filter is used to determine the instantaneous virtual path utilization from crude measurements. A smoothing coefficient formula is derived as a function of peak rate of the virtual channel. The residual bandwidth is derived from the maximum instantaneous utilization observed during a monitoring period. Simulation shows that the proposed method achieves statistical multiplexing gains of up to 80% of the limit possible with optimum control for similar traffic sources. It can be implemented with very simple hardware. The admission decision is simple: the requested bandwidth is compared with the residual bandwidth. This method is therefore well suited for practical asynchronous transfer mode switching systems. © 1998 IEEE.

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DTM: Dynamic Transfer Mode Based on Dynamically Assigned Short-Hold Time-Slot Relay

Yamanaka Naoaki, Shiomoto Kohei

IEICE TRANSACTIONS on Communications E82-B ( 2 ) 375 - 380 1998

This paper proposes a new high-speed network architecture called Dynamic Transfer Mode, DTM. At the entrance of the DTM network, destination addresses such as IP addresses are converted into DTM routing information and attached to the packet header. In a DTM network, a connection is set up on-the-fly by sending a series of routing link identifiers to the destination, so burst data transfers like WWW traffic are efficiently carried. A connection between adjacent nodes is created and released dynamically within the burst transfer period. This yields higher statistical multiplexing gain and improved bandwidth efficiency compared to with conventional STM. Time division multiplexing is utilized so there is no delay jitter or cell loss, which are major drawbacks of Asynchronous Transfer Mode. This paper analyzes the performance of a DTM network and describes an implemented switching system. Because a DTM network uses source-routing and passive STM switching, it simplifies the core transit switch while localizing intelligence to edge nodes. A simplified core transit switch is well suited for future high-speed backbone networks.

Advanced ATM switching system hardware technology using MCM-D, stacking RAM micro-processor module

Yamanaka Naoaki, Kawamura Tomoaki, Kaizu Katsumi, Harada Akio

884 - 888 1998

This paper describes newly developed advanced ATM switching system hardware structures based on MCM-D micro-processor modules. The Si-Substrate MCM-D technology which integrates micro-processor, interface control and peripheral control custom VLSIs, high-speed S-RAMs, and FPGAs (Field Programmable Gate Arrays) is employed. An MCM-D micro-processor module is realized by combining a Motorola 68030, high-performance ASICs, and high-speed S-RAM caches. This is made possible by high density packaging and high-speed 4M-byte with parity cache using 25 ns access to 4-Mbit of S-RAM memory. The MCM employs 12 S-RAMs, possible with the stacked RAM technique, to reduce the module size by 7/8 compared to conventional surface mounting modules. This micro-processor module technology and MCM technology will advance the development of practical B-ISDN ATM switching systems.

Development of plastic chip scale package for ATM switching systems

Harada Akio, Kaizu Katsumi, Yamanaka Naoaki, Kawamura Tomoaki

30 - 35 1998

A plastic chip-scale package (CSP) smaller than conventional ones has been developed and applied to ATM switching systems. It uses a low-cost glass-epoxy substrate. Because glass epoxy is widely used in the printed circuit boards (PCBs) of ATM switching systems, its use in the CSPs mounted on a PCB reduces the difference in thermal expansion between the PCB and CSPs, thus lengthening CSP life. The power plane, ground plane, and thermal vias of the CSP are designed to offset the increased thermal resistance due to the CSP's smaller size. Simulation showed a thermal resistance for this CSP with copper layers and thermal vias of as much as 22% less than that of one with no copper layers or thermal vias. A six-layer test board mounting four CSPs was used to simulate a sub-board for ATM switching systems. The thermal resistance of the two CSPs located downstream was about 10% higher than that of the two located upstream. Two CSPs were developed for two types of application-specific ICs: a bus interface controller (BIC) and a peripheral interface circuit (PIC). Both CSPs were 18 mm square with a 0.8-mm outer solder-ball pitch and 256 outer balls. These CSPs occupied areas about 87% and 68% smaller than those of a conventional pin grid array (PGA) and quad flat package (QFP), respectively. The junction temperature of both CSPs satisfied the thermal condition. These high-performance CSPs are thus attractive for use in ATM switching systems.

A high-speed tandem-crosspoint ATM switch architecture with input and output buffers

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E81-B ( 2 ) 215 - 222 1998

ISSN 0916-8516

This paper proposes a high-speed input and output buffering ATM switch, named Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at every crosspoint. Even if a cell can not be transmitted to an output port on the first plane, it has a chance to be transmitted on the next plane. Cell transmission is executed on each switch plane in a pipeline manner. Therefore, more than one cell can be transmitted to the same output port within one cell time slot, although the internal line speed of each switch is equal to the input /output line speed. The TDXP switch architecture has several advantages in implementation. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require to rebuild the cell sequences at output buffers using time stamps, as is required by a parallel switch. These merits make implementing the high-speed ATM switch easy. Numerical results show that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput both for unicasting and multicasting traffic. This switch architecture is expected to enable the development of high-speed ATM switching systems that can realize over 1 Tb/s throughput in a cost-effective way.

A high-speed CAC scheme in ATM networks by using virtual requests for connection

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E81-B ( 10 ) 1927 - 1930 1998

ISSN 0916-8516

A new multiple QoS control scheme with equivalent-window CAC in ATM networks

Oki Eiji, Yamanaka Naoaki, Shiomoto Kohei, Moitra Soumyo D.

IEICE Transactions on Communications E81-B ( 7 ) 1462 - 1473 1998

ISSN 0916-8516

This paper proposes a multiple QoS control scheme that combines the head-of-line priority (HOLP) discipline with equivalent-window connection admission control (CAC). The proposed scheme can support the different cell loss ratios of both delay-sensitive traffic in high-priority buffers and delay-tolerant traffic in low-priority buffers. The CAC scheme extends a measurement-based CAC algorithm for a single buffer to the low-priority buffer with the HOLP discipline to provide the cell loss ratio objective. We introduce an equivalent window for monitoring low-priority cell streams. The equivalent window size equals the period within which the number of times the low-priority buffer is scanned to read cells is constant. Thus the equivalent window size varies with the high-priority queueing state. Numerical results indicate that the proposed QoS control scheme using the equivalent-window CAC can utilize network resources more effectively than the conventional control scheme which is Virtual Path (VP) separation for different cell loss requirement services. In addition, it is confirmed that the proposed scheme provides conservative admissible loads. Thus, this proposed scheme can achieve large statistical gains while providing both high-priority and low-priority cell loss ratio objectives. The proposed scheme will be very useful for cost-effective multimedia services that have different QoS requirements.

Advanced MCM-D micro-processor module for ATM wide-area network switching systems

Kawamura Tomoaki, Yamanaka Naoaki, Kaizu Katsumi, Harada Akio, Yashiro Zenichi

21 - 26 1998

This paper describes an advanced MCM-D micro-processor module and its high-performance cooling technologies for an ATM-WAN (Wide-Area Network) switching system. The MCM-D module is fabricated on 2 Si-substrates using the stacking RAM technique to reduce module size. The MCM has 4-layer Si substrates, a micro-processor LSI, 4 ASIC-LSIs, 12 high-speed SRAMs, an FPGA and bus-driver ICs. By using the stacking RAM technique, MCM-D module size was reduced to 65 mm×85 mm. This is 14% of that (200 mm×200 mm) of assembly area of a conventional circuit using conventional packaging technologies. The MCM-D module was mounted on an ATM line interface circuit board, and realized 25 MHz micro-processor functions with high-speed (access time 25 ns) and large-capacity (4 MBytes) SRAM cache and ATM line interface circuit functions in an ATM-WAN switching system. The line interface circuit board mounted the MCM-D module has high-performance cooling architecture without fin-structure. The MCM-D module is mounted on a sub-board and has thermal contact to the main board through a rubber with low thermal resistance. By using this high-performance cooling architecture, the MCM-D micro-processor module and the ATM line interface circuit board operate under conventional forced air cooling condition without fin-structure. This MCM technology and high-performance cooling technology can be applied to ATM-WAN switching systems and future B-ISDN ATM switching systems.

A 160 GB/s ATM switch using internal speed-up crossbar switch architecture

Genda Kouichi, Yamanaka Naoaki, Doi Yukihiro, Endo Kenichi

Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi) 80 ( 9 ) 68 - 79 1997.09

ISSN 8756-6621

As an architecture for a large-scale tera bit/s class ATM switch system, a building-block structure combining multiple small-scale switches (AHM: ATM circuit handling module) and interconnection switches (AMC: ATM intermodule connector) is proposed in this paper. In this proposed structure, mesh-like VP connections are made between AHMs by AMCs. Resource management is not done inside the AMC, but is simply executed inside AHMs which interconnect the AMCs. Resources are managed by the total capacity of connectivity (GVP: grouped virtual path) between the AHM and the input/output side AHM. It is shown theoretically that, with this proposed structure, it is possible to increase effectively the switching capacity in proportion to the number of AHMs connected. A new switch architecture with 160 Gb/s switch throughput is also proposed for application to the large-scale ATM switch system proposed in this paper. The proposed switch is an internal speed-up crossbar ATM switch which is suitable for switching high-speed cells. In order to avoid loss of QoS (Quality Of Service) of cells switched by AMC, it accommodates cells which are accelerated up to 10 Gb/s at the output port of the input side AHM. A new high-speed arbitration control algorithm which is distributed to each output line is adopted in this structure. The proposed control algorithm, in which a logical ring is composed of three buses, has a capability twice that of a conventional ring arbiter can realize very high switching throughput above 160 Gb/s. It is shown that a prototype ATM switch has been developed successfully using a combination of new technologies such as a new switch architecture, high-speed Si-bipolar LSI, and a sophisticated multi-chip module technology, and its functions and performance were satisfactorily confirmed. © 1997 Scripta Technica, Inc.

TORUS

Genda Kouichi, Yamanaka Naoaki

IEEE Journal on Selected Areas in Communications 15 ( 5 ) 817 - 828 1997.06

ISSN 0733-8716

A high-speed and distributed ATM switch architecture, called the TORUS switch, is proposed with the aim of achieving a terabit-per-second ATM switching system. The switch is a distributed and scalable internal speed-up crossbar-type ATM switch with cylindrical structure. The self-bit-synchronization technique and optical interconnection technology are combined to achieve gigabit-rate cell transmission, where high-density implementation technologies such as multichip module technology are not required at all. Also, distributed contention control based on the fixed output-precedence scheme is newly adopted. This control is very suitable for high-speed devices because its circuit is achieved with only one gate in each crosspoint. A TORUS switch is fabricated as a 4 × 2 switch module using optical interconnection technology and very high-speed crosspoint LSI's, constructed using an advanced Si-bipolar process. Measured results confirm that the TORUS switch can be used to realize an expandable terabit-rate ATM switch.

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Flexible multi-QoS logical ATM network (full-net)

Yamanaka Naoaki, Oki Eiji

Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi) 80 ( 6 ) 47 - 57 1997.06

ISSN 8756-6621

This paper proposes Full-Net (Flexible Multi-QoS Logical ATM Network), a simple, flexible, and cost-effective network architecture that will enable the development of an advanced multimedia communications network. The backbone of this Full-Net is a VP (virtual path) network where mesh interconnection is made possible between all VCH (virtual channel handler) switches. End-to-end QoS (quality of service) control is executed at access points to the VP network to map out each optimum VC (virtual channel) according to the VCs' respective service characteristics. This is done independently and simultaneously on the same physical ATM network. In the proposed network, a relatively small size switching system is utilized as a transit switch or a local switch depending on the service request. That is, the logical topology of the VC network is altered in response to individual service requests, and multiple VC networks are realized by overlapping them on the same physical network. In order to assure high QoS and construct an optimum VC network, two parameters which characterize the VC network topology are introduced; one is the disjoint route D and the other is the hop limit H. Traffic reliability is the most important QoS factor, and it is shown that an optimum disjoint number D can be determined to maximize the network resource. In the Full-Net, it is clearly shown that it is possible to control easily the end-to-end delay characteristic, also a critical QoS factor, at one or two VCH access points to VP network. The flexible node system PUN (programmable unified node) used in the Full-Net is also described in this paper. The Full-Net described is proposed as an efficient solution for sophisticated network architectures which will satisfy the demand for new services and will flexibly meet the varying demands of the future multimedia age. © 1997 Scripta Technica, Inc.

Very-high-speed ATM switching system technologies

Yamanaka Naoaki, Doi Yukihiro, Fukuda Hideki, Takenaka Toyofumi, Yashiro Zen Ichi

NTT Review 9 ( 2 ) 12 - 19 1997.03

ISSN 0915-2334

High-performance packaging technology for very-high-speed ATM switching systems

Kaizu Katsumi, Kishimoto Tohru, Sasaki Shin Ichi, Yamanaka Naoaki, Genda Kouichi

NTT Review 9 ( 2 ) 36 - 45 1997.03

ISSN 0915-2334

This paper describes high-performance, high-density multichip modules (MCMs) using a copper polymide multi-layer substrate and innovative heat-pipe cooling for high-speed ATM switching systems. High-speed ATM link wires are interconnected on the top surface of the MCMs by the newly developed flexible printed circuit cables and con-nectors to reduce the rear-side I/O count and achieve 620-Mbit/s 32-bit parallel interconnections. A heat-pipe is attached to the back surface of each MCM to cool the power dissipation, which is 30 W per MCM. With a 2-m/s forced air flow, a prototype ATM switch system operated at 320 Gbit/s (with 8 × 8 MCMs) with a maximum junction temperature of less than 85 °C. These results indicate that this technology is suitable for future B-ISDN high-speed switching systems.

A very-high-speed ATM switch architecture using internal speed-up technique

Genda Kouichi, Doi Yukihiro, Endo Ken Ichi, Yamanaka Naoaki

NTT Review 9 ( 2 ) 20 - 27 1997.03

ISSN 0915-2334

An internal speed-up crossbar-type ATM switch architecture is proposed. This switch accommodates 10 Gbit/s cell streams from AHMs in order to guarantee the QoS of switched cells. A new high-speed arbitration algorithm using three buses on each output line, called the bi-directional arbiter, is used. It handles output contention about twice as fast as the conventional ring-arbiter and has the same fairness function. It increases the switch throughput to 160 Gbit/s efficiently. By combining the high-speed switch and AHMs, it will be able to make a sub-terabit/s ATM switching system for future Broadband ISDN networks.

160 Gbit/s high speed ATM switching system

Yamanaka Naoaki, Kaizu Katsumi, Kishimoto Tohru, Genda Kouichi

NTT Review 9 ( 2 ) 28 - 35 1997.03

ISSN 0915-2334

This paper describes a 160 Gbit/s high speed multi-chip ATM switching system for broadband ISDN. This system uses a Copper/Polyimide MCM with 4-layer copper-polyimide signal transmission layers and 11-layers ceramic power supply layers. It uses 64 MCMs that are interconnected by a 98-high-way flexible printed circuit connector. Si-bipolar VLSIs are mounted on a Multi-Chip Module (MCM) using the 15-μm very thin pitch outer lead TAB technique. The system switches ATM cells at a throughput of up to 320 Gbit/s and it is applicable for future B-ISDN.

Advanced ATM-layer function MCM-D module for ATM wide-area network

Kawamura Tomoaki, Yamanaka Naoaki, Kaizu Katsumi

486 - 490 1997

This paper describes a high-performance and cost-effective MCM-D module for an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size was reduced to 50.8 mm×50.8 mm. This is 40% of that (100 mm×65 mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a high-performance ASIC with high-speed (access time 20 ns) and large-capacity (1 MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module was mounted on an ATM line interface circuit, and realized 150 Mbit/s throughput ATM-layer functions(header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM-WAN (wide-area network) switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to ATM-WAN switching systems and future B-ISDN ATM switching systems.

OPTIMA

Yamanaka Naoaki, Yasukawa Seisho, Oki Eiji, Kurimoto Takashi

691 - 696 1997

A Tb/s throughput ATM switching Architecture, OPTIMA, is proposed for a quasi-non-blocking large switch. The switch uses hardware self-rearrangement with a three stage network, that is traffic control is automatically performed by hardware. The switch thus acts as a non-blocking switch. In addition, optical wavelength routing is used to avoid interconnection limitations. An 8×8 interconnection is realized that uses 8 wavelengths to transfer 10 Gb/s signals. A 640 Gb/s OPTIMA prototype is described. The proposed OPTIMA architecture and 640 Gb/s system can be applied to realize future broadband ATM networks.

Scalable crosspoint buffering ATM switch architecture using distributed arbitration scheme

Oki Eiji, Yamanaka Naoaki

28 - 35 1997

This paper proposes a high-speed crosspoint-buffer-type ATM switch, named Scalable -Distributed-Arbitration (SDA) switch. The SDA switch employs a new arbitration that is enable the switch to have scalability. The SDA switch has a crosspoint buffer and transit buffer at every crosspoint. The arbitration is executed between the crosspoint buffer and the transit buffer. The arbitration selects a cell based on delay time using a synchronous counter. The selected cell is transferred from a crosspoint buffer by way of several transit buffers, then to the output port. Since the arbitration is executed distributedly at each crosspoint and the arbitration time does not depend on the switch size, the SDA switch is able to be expandable and have large throughput. Numerical results show that the SDA switch keeps fairness on delay time. In addition. the maximum delay time and the required crosspoint buffer size in the SDA switch was reduced, compared with that in the conventional switch based on the ring arbitration. Thus, the proposed SDA switch based on the new arbitration scheme is a simple and expandable architecture, and it will be suitable for the future high-speed multimedia ATM networks.

640 Gb/s ultra-high-speed optical interconnection system using wide-channel-spacing Wavelength Division Multiplexing

Yasukawa Seisho, Yamanaka Naoaki

101 - 105 1997

A 640 Gb/s ultra-high speed optical switch interconnection system based on Wavelength Division Multiplexing (WDM) is proposed as a Tbit/s ATM switch interconnection system for future B-ISDN. Proposed optical interconnection system uses WDM in switch interconnection to avoid interconnection limitation. The system consists of 8 wavelengths (each carrying a 10 Gb/s signal), eight optical Transmitter modules (Tx), and an 8×8 Arrayed Wave Guide (AWG) optical router which interconnects the 8×8 80 Gb/s WDM signal and 8 wavelengths Receiver modules (Rx). Using a highly statistical WDM optical link, proposed system can attain nearly non-blocking ATM switch interconnection. There are several advantages to the proposed optical interconnection system. First, by adopting a arrayed waveguide filter with wide channel spacing (525 GHz), the system has the wide temperature margin of 10 degree. Second, by setting a Clock Data Recovery circuit in each Rx module, each 10 Gb/s highway interconnect unit switch can function independently. As a result, the proposed system is highly scalable. We fabricate an optical interconnection prototype system and succeed in demonstrating 640 Gb/s optical interconnection. The proposed optical interconnection system can be applied to realize future broadband ATM networks.

Rate control for high-speed burst transmission with quick response in universal ATM-WAN, ALPEN

Hasegawa Haruhisa, Yamanaka Naoaki, Shiomoto Kohei

1734 - 1738 1997

This paper proposes a rate control technique for high-speed burst transmission with quick response in ALPEN, an ATM Multi-protocol Emulation Network. Under lower load, it is desirable for the network to allow very quick burst access to a lot of bandwidth, like UBR. Under higher load, a mechanism for congestion avoidance or recovery is required, like ABR. The rate control technique proposed in this paper provides both properties. In ALPEN, the transit switch sends only information about the residual bandwidth to the source side edge switch. The edge switch responds to user requests quickly because it knows route status. This is very effective because long delay in ATM-WAN reduces response performance. The proposed technique improves ATM-WAN performance because it has a algorithm to collect the information about route status without using any knowledge about delay length. Its performance is confirmed by simulations.

Adaptive remote rate control using extrapolation and correction mechanism for periodic notification of link utilization ratio

Hasegawa Haruhisa, Yamanaka Naoaki, Shiomoto Kohei

IEICE Transactions on Communications E80-B ( 10 ) 1576 - 1580 1997

ISSN 0916-8516

Some new suvivability measures for network analysis and design

Moitra Soumyo D., Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E80-B ( 4 ) 625 - 631 1997

ISSN 0916-8516

A simple cell spacer architecture regenerating source cell interval for multiple traffic classes

Shiomoto Kohci, Yamanaka Naoaki

IEICE Transactions on Communications E80-B ( 1 ) 187 - 191 1997

ISSN 0916-8516

A new simple cell spacing architecture that guarantees the peak cell interval and realizes preferential contention resolution is proposed. Scheduling the cell emission on departure of the previous cell not arrival allows the source peak cell interval to be regenerated without clumping. Priority control is also realized in the proposed spacer. A connection is scheduled either at the head or tail of the contention chain depending on its priority. The proposed method is applied to realize the UPC function. The proposed cell spacer eliminates the clumping effects of CDV completely and achieves high bandwidth efficiency.

Advanced ATM switching system line interface hardware technologies based on MCM-D integrated with ASIC and S-RAMS

Yamanaka Naoaki, Kawamura Tomoaki, Kaizu Katsumi

286 - 289 1997

This paper describes newly developed advanced ATM switching system hardware structures. They are based on the Si-Substrate MCM-D technology which integrates ASIC custom VLSIs, high-speed S-RAMs and FPGAs (Field Programmable Gate Arrays). The MCM-D module realizes the ATM layer function by combining a high-performance ASIC with high-speed S-RAM cache. This is made possible by high density packaging and high-speed (20 ns) access to 1-Mbit of memory. The MCM employs 8 S-RAMs, possible with the stacked RAM technique, to reduce module size. This sub-module technology and MCM technology will advance the development of practical B-ISDN ATM switching systems.

Tandem-crosspoint ATM switch architecture and its cost-effective expansion

Oki Eiji, Yamanaka Naoaki, Yasukawa Seisho

45 - 51 1997

This paper proposes a high-speed input and output buffering ATM switch, named the Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at all crosspoints. The TDXP switch architecture offers several advantages. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. These merits make it easy to implement a high-speed ATM switch. Numerical results show that the TDXP switch can effectively eliminate HOL blocking and achieve high throughput. In addition, we discuss how TDXP switches can be combined to form larger switches in a cost-effective way. We clarify the relative advantages of the crossbar switch configuration and the three-stage Clos switch configuration in achieving a specific throughput. Because the three-stage Clos switch configuration is not strictly non-blocking, we introduce a nearly non-blocking condition and evaluate switch throughput under the condition. The evaluation shows that crossbar switch configuration becomes more cost effective as the throughput of individual switch LSIs, which depends on device technologies, increases.

Extended multicasting technique to allow multiple destinations per output port in ATM switches

Agrawal Jagan P., Yamanaka Naoaki

IEEE Communications Letters 1 ( 4 ) 117 - 118 1997

ISSN 1089-7798

When a multicast cell at an aynchronous transfer mode (ATM) switch requires distribution of its copies to the multiple users and/or outgoing sub-rate links served by one of its output ports, multiple cell copies at that output port are required. The conventional copy approach and broadcast approach of multicasting either cannot handle such situations or handles at the cost of switch performance. In this letter we propose a technique to enhance the ability of the copy and broadcast approaches to multicasting to enable them to handle such situations efficiently and economically.

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A high-speed ATM switch based on scalable distributed arbitration

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E80-B ( 9 ) 1372 - 1376 1997

ISSN 0916-8516

This paper proposes a high-speed crosspoint-buffer-type ATM switch, named Scalable-Distributed-Arbitration (SDA) switch. The SDA switch employs a new arbitration scheme that allows the switch to be scalable. The SDA switch has a crosspoint buffer and a transit buffer at every crosspoint. Arbitration is executed between the crosspoint buffer and the transit buffer. The arbitration selects a cell based on delay time using a synchronous counter. The selected cell is transferred from a crosspoint buffer to the output port by way of several transit buffers. Since arbitration is executed in a distributed manner at each crosspoint and the arbitration time does not depend on the switch size, the SDA switch can be expanded to realize large throughput. Numerical results show that the SDA switch ensures fairness in terms of delay time. In addition, the maximum delay time and the required crosspoint buffer size of the SDA switch are reduced, compared with those in the conventional switch based on ring arbitration. Thus, the proposed SDA switch based on the new arbitration scheme has a simple and expandable architecture, and will be suitable for future high-speed multimedia ATM networks.

An expandable time-division circuit switching LSI and network architecture for broadband ISDN

Kikuchi Shiro, Yamanaka Naoaki

IEEE Journal on Selected Areas in Communications 14 ( 2 ) 328 - 336 1996.02

ISSN 0733-8716

A broadband network architecture is proposed that integrates multimedia services, such as data, video, and telephony information, using 52-Mb/s based STM-paths at the user network interface (UNI). The user can access any new service via the STM-based access network via either synchronous transfer mode (STM) switching or asynchronous transfer mode (ATM) switching. STM circuit switching supports long duration, constant bandwidth data transfer services such as video and high-definition television (HDTV) distribution and will also be used for the crossconnect system. Circuit switching can provide transparent transmission during long connection periods. This paper also proposes an expandable time-division switch architecture, an expandable time-division switching LSI, and an expandable switching module for small to large size system applications. The proposed time-division switching LSI, module, and system handle 52-Mb/s bearer signals and have throughputs of 2.4 Gb/s, 10 Gb/s, and 40 Gb/s, respectively. The time-division switch realizes video distribution with 1:n connections. Finally, a local switching node that features an expandable 52-Mb/s time-division circuit switching network is shown for multimedia access networking.

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A very high-speed ATM switch architecture using internal speed-up technique

Genda Kouichi, Doi Yukihiro, Endo Kenichi, Yamanaka Naoaki

NTT R and D 45 ( 9 ) 847 - 853 1996

ISSN 0915-2326

As a switch architecture of the AMC with switch throughput of 160 Gbit/s, we proposed an internal speed-up crossbar-type ATM switch architecture. This switch accommodates 10-Gbit/s cell streams from AHMs in order to guarantee the QoS of switched cells. A new high-speed arbitration algorithm using three buses on each output line, called the bidirectional arbiter, is used. This handles output contention about twice as fast as the conventional ring-arbiter and has the same fairness function. This increases the switch throughput to 160 Gbit/s efficiently. By combining our high-speed switch and AHMs, we should be able to make a sub-terabit/s ATM switching system for the future Broadband ISDN network.

An optimum design scheme for flexible multi-QoS logical ATM networks

Oki Eiji, Yamanaka Naoaki

NTT R and D 45 ( 7 ) 673 - 678 1996

ISSN 0915-2326

An optimum design scheme is proposed for VC network topologies on a Flexible Multi-QoS Logical ATM Network, named Full-Net. Full-Net offers high-quality Virtual-Path (VP) networks and controls end-to-end QoS only at the VP-networks access points. To develop the optimum network topology for multimedia traffic in a single ATM network, a logically configured Virtual Channel Handler (VCH) interconnection network is associated with each QoS class. To achieve an optimum design scheme for VC networks, the number of disjoint routes is introduced as the parameter used to optimize VC network topology. The number of disjoint routes is chosen so as to maximize total network efficiency. The optimum number of disjoint routes depends on the required QoS, VC-traffic characteristics, and traffic demand.

High-speed ATM switching system technologies

Yamanaka Naoaki, Doi Yukihiro, Fukuda Hideki, Takenaka Toyofumi, Yashiro Zenichi

NTT R and D 45 ( 9 ) 839 - 846 1996

ISSN 0915-2326

ATM network resource management techniques for CBR virtual paths/channels

Sato Youichi, Yamanaka Naoaki, Sato Ken Ichi

IEICE Transactions on Communications E79-B ( 5 ) 684 - 691 1996

ISSN 0916-8516

SUMMARY The benefits of ATM techniques have been widely recognized and many organizations envisage the introduction of ATM techniques into their telecommunication networks. The ATM benefits can, however, be fully exploited only after effective network resource management techniques have been developed. This paper focuses on CBR-VP management techniques. The ATM transport network architecture and VP roles are summarized. Next, the issues of VP accommodation design are described. The point is how to create a design that accommodates cell loss and cell delay jitter, both of which depend on various network parameters and conditions. For this purpose, analytical procedures based on an M/D/1 queueing model are adopted. The approximation method is shown to be very effective in practical use through computer analysis. The method guarantees conservative QOSs. Finally, the proposed method is applied to several design examples to illustrate VP management issues. The proposed method will enable ATM techniques to be introduced to our telecommunication networks by the mid.

Simple multi-QoS ATM buffer management scheme based on adaptive admission control

Shiomoto Kohei, Yamanaka Naoaki

447 - 451 1996

This paper proposes simple and effective multi-QoS ATM buffer management scheme with admission control. The proposed scheme supports three QoS-service classes by two separate buffers with strict priority and measurement-based as well as individual CLR-based admission control. Two guaranteed classes for video and reliable data are multiplexed into a high priority buffer and individual CLR management is employed. We show that the proposed individual CLR management is simple and effective compared to separate buffers with WRR (weighted round robin). One best-effort class is assigned to the low priority buffer, and includes LAN intercommunication using upper-layer congestion control mechanism. Since measurement-based adaptive admission control is employed for best-effort service, the proposed adaptive admission control achieves high bandwidth efficiency while keeping the target CLR. This multi-QoS management scheme can be applied to future multimedia ATM networks that integrate video, data, and other services.

160 Gbit/s high-speed ATM switching system

Yamanaka Naoaki, Kaizu Katsumi, Kishimoto Tohru, Genda Kouichi

NTT R and D 45 ( 9 ) 855 - 862 1996

ISSN 0915-2326

This paper describes a 160-Gbit/s high-speed multi-chip ATM switching system for broadband ISDN. This system uses a copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 11-layer ceramic power supply layers. It uses 64 MCMs that are interconnected by a 98-high-way flexible printed circuit connector. Si-bipolar VLSIs are mounted on a MCM using the 15-μ m very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is used. The system switches ATM cells at a thoughtput of up to 320 Gbit/s and it is applicable for future B-ISDN.

ALPEN

Yamanaka Naoaki, Shiomoto Kohei, Hasegawa Haruhisa

392 - 397 1996

This paper proposes ALPEN, a simple, flexible and cost-effective ATM-WAN architecture that can emulate multiple ATM-layer protocols such as ABR, FRM, and SHM, using a simple ATM transit network. With ALPEN, it is easy to implement any new ATM-layer protocol by modifying only the edge nodes. Edge nodes are directly responsible for the management of the users' bandwidth, eliminating the long round trip delays of conventional networks. The transit network does not support multi ATM-layer protocols and ALPEN's transit switches do not need large computational power. Flexible, adaptive and sophisticated protocols for an efficient use of resources can be easily supported by the network's edge node. Users can then send as much traffic as permitted by the network's available bandwidth.

ALPEN

Yamanaka Naoaki, Shiomoto Kohei, Hasegawai Haruhisa

IEICE Transactions on Communications E79-B ( 4 ) 611 - 615 1996

ISSN 0916-8516

Real-time emulation method for ATM switching systems in broadband ISDN

Matsumura Tsuneo, Yamanaka Naoaki, Yamaguchi Ryoichi, Ishikawa Keiji

55 - 60 1996

This paper describes a real-time emulation method based on the use of commercial FPGAs, high-speed interconnect switch devices and software tools (gate array LSI to/from FPGA netlist migration and multi-FPGA partitioning tools) to emulate large scale high-speed communication switching system without the need for conventional specific wiring structures between FPGAs and timing control circuit insertion. This method is applied to line interface units (LUs) that have 20 MHz operation; we employ the LU board and emulation boards, both of which have hierarchical structures with small sub-boards. The proposed LU board structure has the advantage of utilizing a common LU board for rapid prototyping as well as developing cost effective, practical high-performance Asynchronous Transfer Mode (ATM) switching systems for broadband ISDN (Integrated Services Digital Networks). The results of multiple FPGA partitioning on the emulation board suggest that the proposed method will yield economic systems that are also practical.

Performance evaluation of an ATM connection with several cell flow components

Yamanaka Naoaki, Pitcho Francis, Sato Hiroaki

IEICE Transactions on Communications E79-B ( 5 ) 716 - 718 1996

ISSN 0916-8516

SUMMARY This letter studies the Peak Cell Rate (PCR) policing of ATM connections that consist of multiple cell flow components. It is shown that the conventional methods proposed for policing the aggregate flow do not use the network's resources efficiently. This letter proposes a simple and efficient UPC (Usage Parameter Control) mechanism based on a tandem leaky bucket for multi-component ATM connections. The results show that network resource requirements can be minimized, with reasonable hardware complexity.

High-performance packaging technology for ultra-high-speed ATM switching system

Kaizu Katsumi, Kishimoto Tohru, Sasaki Shinich, Yamanaka Naoaki, Genda Kouichi

NTT R and D 45 ( 9 ) 863 - 871 1996

ISSN 0915-2326

This paper describes high-performance, high-density multichip modules (MCMs) using a copper polyimide multi-layer substrate and innovative heat-pipe cooling for high-speed ATM switching system. High-speed ATM link wires are interconnected on the top surface of the MCMs by the newly developed flexible printed circuit cables and connectors to reduce the rear-side I/O count and achieve 620-Mbit/s 32-bit parallel interconnection. A heat-pipe is attached to the back surface of each MCM to cool the power dissipation, which is 30 W per MCM. With a 2-m/s forced airflow, a prototype ATM switch system operated at 320 Gbit/s (with 8×8 MCMs) with a maximum junction temperature of less than 85 °C. These results indicate that this technology is suitable for future B-ISDN high-speed swithing systems.

An expandable multicast ATM switch based on copy-trunk with new delay control and cell spacing functions

Kurimoto Takashi, Genda Kouichi, Yamanaka Naoaki

IEICE Transactions on Communications E79-B ( 8 ) 1061 - 1067 1996

ISSN 0916-8516

A multicast ATM switch with a new external copy module is proposed. The copy module, called copy-trunk, has two new functions to guarantee the QoS of P-MP cells: The delay priority control function and the output-cell-spacing control function. By using the delay priority control function, copied cells with high-priority are always released earlier than those with low-priority so as to avoid increasing the delay time of real-time traffic. The output-cell-spacing control function is used to reduce the burstiness of the output traffic. The output pattern is adaptively controlled by measuring the input load. The effects of these two controls are quantitatively described. The copy-trunk allows the multicast capability of a switch to be efficiently and economically increased to satisfy future traffic volume and services.

SAM

Pitcho Francis, Yamanaka Naoaki

IEICE Transactions on Communications E78-B ( 9 ) 1330 - 1332 1995.09

ISSN 0916-8516

Multiple-availability-level ATM network architecture

Oki Eiji, Yamanaka Naoaki, Pitcho Francis

IEEE Communications Magazine 33 ( 9 ) 80 - 88 1995.09

ISSN 0163-6804

ATM networks have the potential to achieve switch cost reduction and multi-level network availability because of their high flexibility. For that purpose, this article proposes to use Virtual Circuit (VC) route self-healing schemes to achieve a multiple-availability-level ATM network. First, the advantages of VC route restoration for ATM networks are presented; Virtual Path level and physical level restoration strategies are then compared. The concept of Full-Net is explained, and the self-healing scheme of a VC route is proposed. Finally, the impact of the logical network configurations on network survivability and resource management is presented.

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Performance limitation of the leaky bucket algorithm for ATM networks

Yamanaka Naoaki, Sato Youichi, Sato Ken Ichi

IEEE Transactions on Communications 43 ( 8 ) 2298 - 2300 1995.08

ISSN 0090-6778

The performance limitation of the 'Leaky Bucket algorithm' is analyzed for usage parameter control and traffic management in Asynchronous Transfer Mode (ATM) networks. Simulation results show that the conventional statistical bandwidth allocation method, which uses 'the worst pattern derived from the cell interarrival time moments' permitted by the Leaky Bucket algorithm, can not guarantee the QOS. As a result, this paper proves that the VC/VP bandwidth allocation method based on the Leaky Bucket algorithm is unsatisfactory.

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Optimum logical-design scheme for flexible multi-QoS ATM networks guaranteeing reliability

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E78-B ( 7 ) 1016 - 1024 1995.07

ISSN 0916-8516

An optimum design scheme for logical network topologies on a Flexible Multi-QoS Logical ATM Network, named Full-Net, is proposed. Full-Net offers high-quality Virtual-Path (VP) networks and controls end-to-end QoS only at the VP-network's access points. To develop the optimum network topology for multimedia traffic in a single ATM network, a logically configured Virtual Channel Handler (VCH) interconnection network is associated with each QoS class. Many logical networks can be mapped at the same time on the same network, because mapping is independent of the network's physical implementation. To achieve an optimum design scheme for logical networks, the number of disjoint routes is introduced as the parameter used to optimize logical network topology. The number of disjoint routes is chosen so as to maximize total network efficiency. The optimum number of disjoint routes depends on the required QoS, VC-traffic characteristics, and traffic demand. By choosing the relevant cost characteristics, the network operator can easily maximize network efficiency and provide customers with the QoS they request at minimum cost. The proposed optimum multi-QoS network design scheme on a Full-Net architecture is an efficient solution to implementing multi-QoS control in an ATM network.

Recursive matrix-calculation method for disjoint path search with hop link number constraints

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E78-B ( 5 ) 769 - 774 1995.05

ISSN 0916-8516

A new approximation calculation method, named the Recursive Matrix-calculation (RM) method, is proposed. It uses matrix calculation to determine the number of link disjoint paths under a hop link number constraint, i.e. hop limit. The RM method does not overestimate the number of link disjoint paths. When networks are designed by this method, network reliability is perfectly guaranteed. Moreover, the RM method is based on matrix calculation, so CPU time can be reduced by using super-computers equipped with vector processors. Simulation results confirm that the RM method yields rapid approximations that are conservative. Thus the proposed method is very useful for designing reliable multimedia networks.

Jitter tolerant usage parameter control method for ATM-based B-ISDN

Yamanaka Naoaki, Takenaka Toyofumi, Sato Youichi, Sato Ken ichi

IEICE Transactions on Communications E78-B ( 4 ) 485 - 493 1995.04

ISSN 0916-8516

A uniquely-structured Usage Parameter Control (UPC) method named Virtual-shaping is proposed which considers cell arrival time jitter between user and UPC point. The method uses a modified Dangerous Bridge UPC circuit (Sliding window type) and virtually (logically) shapes cell traffic using cell arrival time compensation to offset cell delay variation (CDV). In addition, the proposed method is based on a cell-buffer-less structure and can be realized with reasonable hardware. The method yields precise and accurate monitoring. Computer simulations show that the method offers higher network utilization than the conventional Leaky Bucket based UPC method. The proposed method will make it possible to create more effective B-ISDNs, and more cost-effective broadband VBR services.

320 Gb/s high-speed ATM switching system hardware technologies based on copper-polyimide MCM

Yamanaka Naoaki, Endo Ken ichi, Genda Kouichi, Fukuda Hideki, Kishimoto Tohru, Sasaki Shin ichi

IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging 18 ( 1 ) 83 - 91 1995.02

ISSN 1070-9894

This paper describes a 320 Gb/s high-speed multichip ATM switching system for broadband ISDN. This system employs a copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 15-layer ceramic power supply layers. The system uses 64 MCM's that are interconnected by 98-highway flexible printed circuit connector. Si-bipolar VLSI's are mounted on MCM's using the 150 μm very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is adopted. The system switches ATM cells up to 320 Gb/s throughput, which is applicable for future B-ISDN.

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TORUS-switch

Genda K., Yamanaka N.

Electronics Letters 31 ( 11 ) 906 - 908 1995.01

ISSN 0013-5194

A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient.

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Optimum logical ATM network design method guaranteeing multimedia QoS requirements

Oki Eiji, Yamanaka Naoaki

263 - 269 1995

This paper proposes a new topological design method, named BXCQ, which optimizes logical network configuration while guaranteeing QoS requirements for each service class in an ATM network. The BXCQ method determines the optimum logical network topology associated with each service class so as to minimize network cost. In our previously proposed Full-Net architecture[1], these different logical topologies can be suitably mapped at the same time on the same ATM physical network by using VCHs logical interconnection networks. According to the BXCQ method, the results quantitatively clarify the relations between multimedia traffic characteristics and desirable logical network configurations in the Full-Net. Evaluation results suggest that a service class that is bursty, delay tolerant and cell loss sensitive with small demand should be supported by a loop-like topology. Furthermore, the results also show that suitably changing logical configurations in accordance with traffic demand fluctuations leads to a dramatic reduction of 8.8% in network cost. This study will be useful for designing flexible and cost-effective multimedia networks that can also adapt to not-yet-known services.

Sub-T bit/s large-capacity ATM MCM switching system design and modules with new low-power Gbit/s I/O circuits

Kawamura Tomoaki, Yamanaka Naoaki, Matsumura Tsuneo, Ichino Haruhiko, Yamaguchi Chikara, Kobayashi Yoshiji

44 - 47 1995

This paper presents a low-power large-capacity ATM switching system design and modules (LSI and MCM). The design uses MCM technology with a copper-polyimide substrate, 150-μm pitch outer lead TAB and 98-highway flexible printed circuit cables for high-density packaging and high-speed operation. Using these technologies, a 160 Gbit/s ATM switching system with a power dissipation of about 1.3 kW can be achieved for future Broadband ISDN systems. This power is 65% of that of the reported system which uses ECL I/Os, and can be cooled by forced air with conventional fin-structures.

TORUS-switch

Genda Kouichi, Yamanaka Naoaki

1738 - 1745 1995

An over 1 Tb/s scalable ATM switching system architecture is proposed suitable for the mature B-ISDN environment. Two kinds of switch modules are combined, the small-scale switch with VC and VP-level management named AHM having 10 to 20 Gb/s throughput, and the high-speed and simple routing switch named AMC offering simple ATM layer management for AHMs-interconnection. AMC resource management employs the Grouped VP resource management scheme only at AHM. The proposed system architecture gives high statistical multiplexing gain from small-size switches to over 1 Tb/s switches and easy management; switching capacity can be efficiently expanded. As the switch architecture of the AMC, a high-speed and scalable ATM switch architecture, named TORUS-switch, is proposed. The switch is an internal speed-up crossbar-type switch with cylindrical configuration. The self-bit-synchronization technique is adopted to achieve high-speed cell transmission without requiring high-density implementation technology. Also, distributed contention-control based on the fixed output-precedence scheme is newly adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultra-high-speed crosspoint LSI using the advanced Si-bipolar process to confirm its feasibility. Measured results confirm that the TORUS-switch can be used to realize a expandable tera-bit-rate ATM switch that is also efficient.

New traffic shaping mechanism for ATM networks

Pitcho Francis, Yamanaka Naoaki

IEICE Transactions on Communications E77-B ( 12 ) 1628 - 1631 1994.12

ISSN 0916-8516

High-speed-retry banyan switch architecture for giga-bit-rate BISDN networks

Genda Kouichi, Yamanaka Naoaki, Arai Yoshimitsu, Kataoka Hideki

International Journal of Communication Systems 7 ( 3 ) 223 - 229 1994.07

ISSN 1074-5351

This paper proposes a high-speed ATM switch architecture for handling cell rates of several Gb/s in a broadband communication switching system or cross-connect system. The proposed switch architecture, named the high-speed-retry banyan switch, employs a bufferless banyan network between input and output buffers: a cell is repeatedly transmitted from an input buffer until it can be successfully transmitted to the desired output buffer. A simple cell-retransmission algorithm, is employed as is a ring-arbitration algorithm for cell conflict. They are suitable for FIFO type buffers and bufferless high-speed devices. Good traffic characteristics which are independent of switch size are achieved for an internal speed ratio of only four times the input line speed. A prototype system with the internal speed of 1·2 Gb/s is constructed in order to confirm the basic operation of the high-speed-retry banyan switch. The prototype system, even in its present state, could be used to realize a giga-bit-rate BISDN switching system.

320 Gb/s high-speed ATM switching system hardware technologies based on copper-polyimide MCM

Yamanaka Naoaki, Endo Ken ichi, Genda Kouichi, Fukuda Hideki, Kishimoto Tohru, Sasaki Shin ichi

776 - 785 1994

This paper describes a 320 Gb/s high-speed multi-chip ATM switching system for broadband ISDN. This system employs a Copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 15-layer ceramic power supply layers. The system uses 64 MCMs that are interconnected by 98-highway flexible printed circuit connector. Si-bipolar VLSIs are mounted on MCM using the 150 μm very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is adopted. The system switches ATM cells up to 320 Gb/s throughput and it is applicable for future B-ISDN.

High-speed ATM switching architecture using small shared switch blocks

Endo Ken ichi, Yamanaka Naoaki

IEICE Transactions on Communications E76-B ( 7 ) 736 - 740 1993.07

ISSN 0916-8516

This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The N × N matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N^-2 to (N/D)². Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10^-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.

Wavelength path network management scheme for multimedia photonic network

Yamanaka Naoaki, Chaki Shin ichiro

IEICE Transactions on Communications E76-B ( 7 ) 731 - 735 1993.07

ISSN 0916-8516

A wavelength path (WP) network management scheme is proposed for a photonic network. Multimedia data streams are integrated into a single-mode fiber using wave-length division WP multiplexing, both analog/digital and STM/ATM communications are handled. The WP management scheme using WP blocks (WPBs) with guard bands is described. An initially assigned WP does not use the guard band and most bandwidth changes made to accommodate WP changes occur within the original WPB using the guard band. An effective WP assignment method based on a recursive packing scheme is also proposed. The proposed WP packing scheme with guard band realizes a maximum network efficiency of 98%, and the probability of WP reassignment is under 10%. The techniques introduced in this paper permit the realization of flexible and effective multimedia services with a multimedia photonic network.

High-speed ATM switch that uses a simple retry algorithm and small input buffers

Genda Kouichi, Yamanaka Naoaki, Doi Yukihiro

IEICE Transactions on Communications E76-B ( 7 ) 726 - 730 1993.07

ISSN 0916-8516

This letter describes the High-speed Statistical Retry switch (HSR switch) for high-speed ATM switching systems. The HSR switch uses a new matrix-shaped switching structure with buffers at input and output ports, and a simple retry algorithm. The input buffers are very small, and no complicated arbitration function is employed. A cell is repeatedly transmitted from each input buffer at 'm' times the input line speed until the input buffer receives an acknowledge signal from the intended output buffer. A maximum of one cell can be transmitted from each input buffer during the cell transmission time. The internal ratio (m) is decided according to the probability of cell conflict in the output line. Simulation results show that just a 10-cell buffer at each input port and a 50-cell buffer at each output port are required when m=4 to achieve a cell loss probability of better than 10^-8, irrespective of the switch size. At each crosspoint, cells on the horizontal input line take precedence over those on the vertical input line. Only a very simple retry algorithm is employed, no complex arbitration is needed, and the arbitration circuit at the crosspoint can be reduced by about 90% in size. The proposed ATM switch architecture is applicable to high-speed (Gbit/s) ATM switches for B-ISDN because of its simplicity.

Usage parameter control and bandwidth allocation methods considering cell delay variation in ATM networks

Yamanaka Naoaki, Sato Youichi, Sato Ken ichi

IEICE Transactions on Communications E76-B ( 3 ) 270 - 279 1993.03

ISSN 0916-8516

This paper proposes an ATM traffic management method that utilizes a deterministic source traffic descriptor, a deterministic Usage Parameter Control (UPC) algorithm and a conservative statistical bandwidth allocation method all of which were developed considering the Cell Delay Variation (CDV) typically experienced in ATM networks. For the source traffic descriptor, sliding time interval-type descriptors are proposed. A newly-structured UPC method which combines a sliding window-type circuit and a 2-phase credit window type circuit is proposed. The method is precise and accurate and requires only a small amount of hardware. The proposed parameter conversion method considers the CDV generated between User and UPC point. A bandwidth allocation method based on the worst clumping pattern and UPC output pattern is proposed. The network efficiency degradation caused by CDV is calculated. This traffic management method not only guarantees the QOS of all connections but also allows for large statistical multiplexing gains. The proposed method will, therefore, make it possible to create a more effective B-ISDN, one that can offer cost-effective broadband VBR services.

High-speed ATM switch with input and cross-point buffers

Doi Yukihiro, Yamanaka Naoaki

IEICE Transactions on Communications E76-B ( 3 ) 310 - 314 1993.03

ISSN 0916-8516

This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1 Gbit/s.

Network resource management techniques for VP-based B-ISDN

Sato Ken ichi, Sato Youichi, Yamanaka Naoaki, Hayashi Kazuhiro

NTT R and D 42 ( 3 ) 343 - 356 1993

ISSN 0915-2326

This paper describes network resource management techniques which are the key to exploiting the benefits of VP-based ATM networks. In ATM networks, the Virtual Path (VP) concept has been established which enables separation of the logical path capability from the physical interface structure. This is an inherent benefit of VPs and will greatly enhance network flexibility and performance. However, the benefits of ATM can only be utilized through a new network resource management technique and a Usage Parameter Control technique, which are described in this paper.

A 1.8-Gb/s GaAs optoelectronic universal switch LSI with monolithically integrated photodetector and laser driver

Yamanaka Naoki, Kikuchi Shiro, Takada Tohru

Journal of Lightwave Technology 10 ( 8 ) 1162 - 1166 1992.08

ISSN 0733-8724

A high-speed monolithic optical interface switch LSI is developed using a GaAs MSM photodetector and large-scale integrated electric circuits. This LSI operates universally as a 1.8-Gb/s optical-input/optical-output four-channel time-division switch, a 1.8-Gb/s optical-input/electrical-output 1:4 demultiplexer, a 2.0-Gb/s electrical-output 4:1 multiplexer, and a 2.8-Gb/s electrical-input/electrical-output 4 × 4 space-division switch. It uses a new multistage 2 × 2 switch block with small hardware and high-speed operation. It can be expanded to a 16 × 16 optical-input/optical-output time-division switch operating at up to 1.8 Gb/s for broadband-ISDN.

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A gigabit-rate five-highway GaAs OE-LSI chipset for high-speed optical interconnections between modules or VLSI's

Yamanaka Naoaki, Sasaki Masaharu, Kikuchi Shiro, Takada Thoru, Idda Masao

IEEE Journal on Selected Areas in Communications 9 ( 5 ) 689 - 697 1991.06

ISSN 0733-8716

A gigabit-rate five highway interface GaAs optoelectronic LSI chipset has been fabricated for the 0.85 μm wavelength range optical interconnections between modules or VLSIs. The optical sender consists of a high-speed laser driver array LSI having 2 Gb/s maximum operation speed and a tiny laser array. The optical receiver in a GaAs high-speed optical receiver array LSI with a monolithically integrated metal-semiconductor-metal (MSM) photodetector, a high-speed preamplifier, and a decision circuit that has a maximum operation speed of 1.8 Gb/s. The receiver LSI is provided with a new bit-synchronizing circuit and an automatic threshold determination circuit.

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2.2 Gbit/s Si bipolar 8 × 8 crosspoint switching LSI

Yamanaka Naoaki, Kikuchi Shiro, Suzuki Masao, Hirata Michihiro

Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi) 74 ( 2 ) 100 - 110 1991.02

ISSN 8756-663X

A high-speed 8 × 8 space-division switching LSI has been developed for video and HDTV switching and broadcasting applications in the future B-ISDN. The LSI employs a new circuit design and super self-aligned process technology (SST-1A), and is switched successfully with a bit error rate of less than 10^-9 at 2.5 Gbit/s using a 2⁹-1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 70 ps at 2.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell. The LSI has an ECL-compatible interface, -4.0 V and -2.0 V power supply voltages, and power dissipation of less than 997 mW. High-speed address control memories (ACMs) are integrated monolithically into the LSI, which can operate both synchronously and asynchronously.

Experimental ATM transport system and virtual path management techniques

Sato Youichi, Yamanaka Naoaki, Sato Ken ichi, Tokura Nobuyuki

2110 - 2116 1991

The authors present the main points of a recently developed experimental ATM (asynchronous transfer mode) transport system and the key virtual path (VP) management techniques. The ATM network configuration and the developed ATM cross-connect and add/drop multiplexing (ADM) systems are outlined. They describe the design considerations of the VP management techniques, which include VP bandwidth specifying parameters. The newly developed usage parameter control techniques are then presented. An analytical method for evaluating cell multiplexing delay and cell loss characteristics for multimedia signal sources is developed. Next, by utilizing this method, a link capacity-design algorithm for accommodating VPs is proposed. Finally, the performance and application areas of the proposed algorithm are evaluated.

A 2 Gb/s expandable space-division switching LSI and network architecture for gigabit-rate broad-band circuit switching

Yamanaka Naoaki, Kikuchi Shiro, Suzuki Masao, Yoshioka Yukiharu

IEEE Journal on Selected Areas in Communications 8 ( 8 ) 1543 - 1550 1990.10

ISSN 0733-8716

An expandable space-division (SD) switch architecture and a bipolar circuit design for gigabit-per-second crosspoint-switch LSIs are described. An expandable 2-Gb/s 16 × 16 crosspoint switch LSI which employs a novel switch structure, a novel circuit design, and a super self-aligned process (SST-1A) is developed. A switching module and partial 1:n nonblock, full 1:1 nonblock switching network architecture are also presented. Using the LSI and the switching network architecture, an experimental 620-Mb/s network system is demonstrated.

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Circuit design for 2-Gbit/s Si bipolar crosspoint switch LSI's

Suzuki Masao, Yamanaka Naoaki, Hirata Michihiro, Kikuchi Shiro

IEEE Journal of Solid-State Circuits 25 ( 1 ) 155 - 159 1990.02

ISSN 0018-9200

An 8 × 8 and an expandable 16 × 16 crosspoint switch LSI utilizing a new circuit design and super self-aligned process technology (SST-1A) are discussed. The LSIs successfully switched with a bit error rate of less than 10^-9 at 2.5 Gb/s using a 2⁹ - 1 pseudorandom NRZ sequence. Pulse jitter was limited to less than 80 ps at 1.2 Gb/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSIs have an ECL-compatible interface, -4-V and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8 × 8 LSI and 2.8 W for the expandable 16 × 16 LSI.

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Newly structured expandable 52-Mbit/s, 48-channel time-division switching LSI with 2.4 Gbit/s throughput

Yamanaka N., Kikuchi S., Miyanaga H.

Electronics Letters 26 ( 8 ) 524 - 526 1990.01

ISSN 0013-5194

An expandable Si bipolar 2.4 Gbit/s throughput, 52 Mbit/s 48-channel time-division switching LSI system is described. A high-throughput of 2.4 Gbit/s and a power-dissipation of 5.3 W are achieved by adopting a low-voltage swing four-serial-gated differential bipolar circuit design and super self-aligned process (SST-1A) logic-in-memory LSI technology. This LSI is applicable to the digital video time-division switching and digital crossconnect systems ot future B-ISDN.

Multichip 1.8-Gb/s high-speed space-division switching module using copper-polyimide multilayer substrate

Yamanaka Naoaki, Kikuchi Shiro, Kon Taichi, Ohsaki Takaaki

562 - 570 1990

A high-speed multichip 32 × 32 space-division switching module for high-definition TV broadcasting and switching systems is described. This module employs a novel Si-bipolar SST (super self-aligned process technology) switching LSI and a multilayer substrate with a polyimide dielectric and a fine pattern of copper conductors. The substrate contains matrix-shaped thin-film resistors for terminated transmission and has a spiral via hole structure to increase fabrication reliability. The module has 50-Ω characteristic impedance transmission lines that have a small deviation of less than 2.5%. The multichip module can handle a signal speed of 1.8 Gb/s using 1:1 and 1:n connections. Performance results confirm that this module will be suitable for future B-ISDN (broadband integrated services digital network) communication systems.

1.5 Gbit/s GaAs four-channel selector LSI with monolithically integrated newly structured GaAs ohmic contact MSM photodetector and laser driver

Yamanaka Naoaki, Takada Tohru

IEEE Photonics Technology Letters 1 ( 10 ) 310 - 312 1989.10

ISSN 1041-1135

A monolithic integrated 1.5 Gb/s high-speed four-channel optoelectronic integrated circuit (OEIC) selector GaAs LSI circuit is discussed. This LSI circuit incorporates photodetectors, preamplifiers, a selector, a decision circuit, and a high-speed laser driver. To achieve high efficiency, a AuGe/Ni-GaAs structured ohmic contact metal-semiconductor-metal (OC-MSM) is used for the interdigitated structural photodetector. With this OC-MSM structure, photocurrent is approximately twice as effective as with the conventional Schottky contact MSM structure. The new LSI has a maximum operating speed of 1.5 Gb/s and exhibits low power dissipation of 927 mW.

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1 Gbit/s, 32 × 32 high-speed space-division switching module for broadband ISDN using SST LSIs

Yamanaka N., Kikuchi S., Yoshioka Y., Suzuki M.

Electronics Letters 25 ( 13 ) 831 - 833 1989.01

ISSN 0013-5194

2 Gbit/s, 16 × 16 expandable high-speed space-division-switch LSI using SST

Yamanaka N., Suzuki M., Kikuchi S.

Electronics Letters 25 ( 22 ) 1470 - 1471 1989.01

ISSN 0013-5194

Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs

Suzuki Masao, Yamanaka Naoaki, Hirata Michihiro, Kikuchi Shiro

65 - 66 1989

An Si bipolar circuit technology for gigabit-per-second crosspoint switch LSIs is described. A novel circuit design and a super-self-aligned process technology were adopted, and 8 × 8 and 16 × 16 (+16) crosspoint switch LSIs were fabricated. The LSIs successfully switched with a bit error rate of less than 10^-9 at 2.5 Gb/s using a 2⁹-1 pseudorandom NRZ sequence. Pulse jitters are made less than 76 ps at 2 Gb/s by utilizing a small internal voltage swing (225 mV) with a differential CML. The LSIs have full emitter-coupled logic (ECL)-compatible interfaces, -4/-2-V power supply voltages, and a power consumption of less than 0.9 W for an 8 × 8 LSI, and 2.8 W for a 16 × 16 (+16) LSI. These results confirm that the proposed technologies are applicable to future B-ISDN (broadband integrated services digital network) communication systems.

Novel structure for high-speed multihighway serial-to-parallel converter

Yamanaka Naoaki, Hirata Michihiro, Suzuki Masao, Yano Takao

IEEE Transactions on Communications 36 ( 11 ) 1221 - 1225 1988.11

ISSN 0096-1965

HIGH-SPEED TIME DIVISION SWITCH FOR 32-MBIT/S BEARER RATE SIGNALS.

Yamanaka Naoaki, Miyanaga Hiroshi, Yamamoto Yousuke

IEEE Journal on Selected Areas in Communications SAC-5 ( 8 ) 1249 - 1255 1987.10

ISSN 0733-8716

A high-speed time-division switch used in a 32-Mb/s bearer-signal communications system is described. System performance is realized by using three technologies. The first is a switch structure referred to as a 2-RAM 2-bank structure which ensures high-speed performance by increasing switching throughput four times over that of the basic structure. The second is the inclusion in the switch of two types of peripheral logic developed using Si-bipolar super-self-aligned process technology. The third is high-speed synchronous transmission of data. A large-channel-capacity time-division switching network is also discussed. In conjunction with the network, these technologies make it possible to realize the ISDN time-division switches necessary for such services as TV and high-definition TV communications.

HIGH-SPEED TIME-DIVISION SWITCH FOR BROADBAND ISDN.

Yamanaka Naoaki, Kikuchi Shiro

2010 - 2014 1987

NEWLY STRUCTURED 512 Mbit/s HIGH-SPEED TIME-DIVISION SWITCH.

Yamanaka N., Miyanaga H., Yamamoto Y.

Electronics Letters 22 ( 21 ) 1094 - 1096 1986.10

ISSN 0013-5194

The letter describes the recently developed fastest time-division switch experimental system operating at 512 Mbit/s. The system adopts a new switch structure which can increase switching throughput by four times over the basic structure to ensure high-speed performance. Also employed in the switch are two types of peripheral logic developed using Si bipolar super-self-aligned process technology. This switch makes possible the ISDN time-division switches necessary for TV and high-definition TV communication.

LOW-POWER Si-BIPOLAR MULTI-GBIT/S LOGICS HAVING THE SAME FUNCTION AS ECL100K FAMILY.

Yamanaka Naoaki, Miyanaga Hiroshi, Yamamoto Yousuke

Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E E69 ( 10 ) 1068 - 1071 1986.10

ISSN 0387-236X

A Novel Concept for High-Speed Time Switch Approaching Memory Read Cycle Limit

Yamamoto Yousuke, Miyanaga Hiroshi, Kobayashi Yoshiji, Terada Yasukazu, Yamanaka Naoaki

IEEE Transactions on Communications 34 ( 9 ) 953 - 955 1986

ISSN 0090-6778

A novel concept and structure for a high-speed time division switch operating in the gigabit/second range are presented. The basic concept is to use the high-speed memory in the time switch effectively by means of a slow writing/fast reading method. N numbers of speech data are written in parallel during N clock times and read serially during one clock time for one switched datum. By using the concept and high-speed memories that we have, a data switching system which approaches the memory and read cycle limit can be realized with a proper time margin. Copyright © 1986 by The Institute of Electrical and Electronics Engineers, Inc.

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BIPOLAR GBIT/S 8 multiplied by 8 BIT S/P, P/S CONVERTER LSI.

Hirata Michihiro, Suzuki Masao, Yamanaka Naoaki, Yamamoto Yousuke

271 - 274 1986

HIGH-SPEED TIME DIVISION SWITCH OPERATING AT 256Mb/s.

Yamanaka Naoaki, Kawakami Masaharu, Terada Yasukazu

Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E E68 ( 9 ) 570 - 571 1985.09

ISSN 0387-236X

FINE STRUCTURES IN THE BROADENED LINE OF DISTRIBUTED FEEDBACK LASERS UNDER HIGH-SPEED DIRECT MODULATION.

Yoshikuni Yuzo, Matsuoka Takashi, Motosugi George, Yamanaka Naoki

Applied Physics Letters 45 ( 8 ) 820 - 822 1984.01

ISSN 0003-6951

Precise observation of the single longitudinal mode spectrum for distributed feedback lasers revealed fine structures when the spectrum was broadened by high-speed modulation. A dynamic simulation can explain reasonably the above behavior if the model takes into account the carrier density modulation enhanced by the relaxation oscillation. In this work, experimental results where both modulation depth and speed were varied are described along with a calculated result.

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