研究者詳細 - 天野　英晴

論文 - 天野　英晴

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Refinements in Data Manipulation Method for Coarse Grained Reconfigurable Architectures

Kojima T., Amano H.

Proceedings - 2019 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2019 （Proceedings - 2019 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2019） 113 - 120 2019年07月

Coarse-grained reconfigurable architectures (CGRAs) is one of the suitable devices for IoT (Internet of Things) and edge-computing because of their high energy efficiency and programmability. The CGRAs process a compute-intensive part of an application program (especially a loop part) more efficiently than general purpose processors. CMA (Cool Mega Array) is an energy-conscious CGRA with a task-level reconfiguration instead of a cycle-level one. However, the CMA faces some limitations related to data management because of the aggressive pursuit of power saving. In this paper, we introduce a new CMA architecture VPCMA2 to relax the constraints and to improve energy efficiency. Then, we implement it with a 65-nm process technology to evaluate a hardware overhead due to the improvement. According to the evaluation results, the new design does not influence its maximum operating frequency. Although new functionalities brought about 17% power overhead and 10% area overhead, a remarkable improvement of application mappability and data handling was achieved.

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Acceleration of deep recurrent neural networks with an FPGA cluster

Sun Y., Ben Ahmed A., Amano H.

ACM International Conference Proceeding Series （ACM International Conference Proceeding Series） 2019年06月

In this paper, we propose an acceleration methodology for deep recurrent neural networks (RNNs) implemented on a multi-FPGA platform called Flow-in-Cloud (FiC). RNNs have been proven effective for modeling temporal sequences, such as human speech and written text. However, the implementation of RNNs on traditional hardware is inefficient due to their long-range dependence and irregular computation patterns. This inefficiency manifests itself in the proportional increase of run time with respect to the number of layers of deep RNNs when running on traditional hardware platforms such as a CPUs. Previous works have mostly focused on the optimization of a single RNN cell. In this work, we take advantage of the multi-FPGA system to demonstrate that we can reduce the run time of deep RNNs from O(k) to O(1).

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An ARM-based heterogeneous FPGA accelerator for hall thruster simulation

Noda H., Orsztynowicz M., Iizuka K., Miyajima T., Fujita N., Amano H.

ACM International Conference Proceeding Series （ACM International Conference Proceeding Series） 2019年06月

The Full Particle-In-Cell (Full-PIC) method is a numerical simulation technique used in the research and development of Hall-thrusters, a propulsion mechanism of satellites. The Japan Aerospace Exploration Agency (JAXA) has been developing a software package called NSRU-Full-PIC for the design of Hall thrusters. Since the numerical simulation of NSRU-Full-PIC requires a large computing power, energy efficient accelerators are essential. However, because of the frequent random memory access and Read-After-Write (RAW) hazard, acceleration with GPUs is difficult. In this paper, we tackle the problems by cooperating a CPU and an FPGA in an ARM-based heterogeneous FPGA accelerator. We use Intel’s mid-range SoC, Arria 10 which embeds floating point DSPs for high performance yet low power numerical computation. Intel FPGA SDK for OpenCL is available in the platform for easy offloading of complex tasks. Heavy load processes in NSRU-Full-PIC are implemented with a hardware/software co-design on Arria 10 SoC. Our implementation improved the power consumption by 5.66 times compared to the original code on a Xeon E5-2680 v2 2.8 GHz . The total energy consumption was reduced to 88.44% of the Xeon implementation. The target tasks become 3.48 times faster than the original code on an only ARM Cortex-A9 1.5 GHz in Arria 10 SoC, and 2.50 times faster than the implementation using atomic instructions on an NVIDIA K20c GPU.

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The evaluation of partial reconfiguration for a multi-board FPGA system FiCSW

Yamakura M., Hironaka K., Azegami K., Musha K., Amano H.

ACM International Conference Proceeding Series （ACM International Conference Proceeding Series） 2019年06月

FiC (Flow-in-Cloud) is a multi-FPGA system to realize a monolithic large FPGA image with multiple cost-efficient mid-range FPGAs connected withfl exible and high bandwidth interconnection network. The FPGA is used as both for computational resource and the network circuit switch, and separating FPGA regions by partial reconfiguration (PR) design technique. In this paper, we will introduce the FPGA design methodology with the PR technique for the FiC system. Evaluation result shows that the proposed design methodology reduces design and configuration time, and it enables to replace the region for computation without stopping the network running on the same FPGA.

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Sparse 3-D NoCs with inductive coupling

Koibuchi M., Leong L., Totoki T., Niwa N., Matsutani H., Amano H., Casanova H.

Proceedings - Design Automation Conference （Proceedings - Design Automation Conference） 2019年06月

ISSN 0738100X

Wireless interconnects based on inductive coupling technology are compelling propositions for designing 3-D integrated chips. This work addresses the heat dissipation problem on such systems. Although effective cooling technologies have been proposed for systems designed based on Through Silicon Via (TSV), their application to systems that use inductive coupling is problematic because of increased wireless-communication distance. For this reason, we propose two methods for designing sparse 3-D chips layouts and Networks on Chip (NoCs) based on inductive coupling. The first method computes an optimized 3-D chip layout and then generates a randomized network topology for this layout. The second method uses a standard stack chip layout with a standard network topology as a starting point, and then deterministically transforms it into either a "staircase" or a "checkerboard" layout. We quantitatively compare the designs produced by these two methods in terms of network and application performance. Our main finding is that the first method produces designs that ultimately lead to higher parallel application performance, as demonstrated for nine OpenMP applications in the NAS Parallel Benchmarks.

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Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud

Yamauchi Y., Musha K., Amano H.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings （IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings） 2019年05月

In order to cope with computation cost and energy required for the recent deep learning technology, domain specific systems have been used in the cloud computing so as to be shared by many application developers efficiently. Although GPU(Graphics Processing Unit)s and more specialized systems like TPU (Tensor Processing Unit)s have been popularly utilized, FPGAs have been receiving an attention especially for their power efficiency and flexibility. Since energy efficiency is one of the most important issues in recent cloud computing, a lot of researches to use FPGAs in the cloud have been asserted[3], and commercial systems including Amazon's F1 instance are available. However, the performance improvement in the FPGA is limited by the upper limit of the FPGA resource, even an FPGA in the cloud. Thus, in order to implement a large deep layer learning application, we must use an expensive high-end FPGA or adopt a lightweight algorithm sacrificing throughput and accuracy. To deal with this problem, in the project 'Power-saving AI engine and platform with heterogeneous engine integrated cloud' supported by NEDO started to develop a large-scale AI system called Flow-in-Cloud (FiC)[4]. FiC is consisting of a number of middle-scale economical FPGAs interconnected with high communication bandwidth network. From an HLS (High Level Synthesis) programmer, a lot of FPGAs can be handled as if they were a single large FPGA. The programmer can implement a large-scale deep learning model without caring resources on a single FPGA. FiC is managed by the Flow-OS, and shared efficiently by many users. Although FiC is designed to build a heterogeneous computing system, the current prototype is consisting of multiple FPGA boards called 'FiC-SW' each of which provides both the switching and computing capabilities. Here, as a case study of such an energy efficient multi-FPGA board computing, we implemented the inference part of Long Short Term Memory (LSTM) [1].

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Key-value Store Chip Design for Low Power Consumption

Tokusashi Y., Matsutani H., Amano H.

Low-power embedded systems often require simple but flexible functionality for data management. Key-value store is one of data stores, which provides simple API and is easy to scale-out. We developed a dedicated key-value store core as a low-power embedded storage. In this paper, key-value store chip is fabricated with Renesas SOTB 65-nm process technology. We evalute the real chip in terms of power consumption and operating frequency by tuning VDD and body bias voltage. The chip achieved 11.2mW as power consumption with 0.7V VDD if the target frequency is 40MHz. When data rate is low, the system can reduce power consumption by tuning VDD and body bias voltage.

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A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops

Ikezoe T., Amano H., Akaike J., Usami K., Kudo M., Hiraga K., Shuto Y., Yagami K.

2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018 （2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018） 2019年02月

Recent IoT devices are required to be an extremely low power in idle time, while a certain performance is required in active time. NVCMA (Non-volatile Cool Mega Array) is a coarse-grain reconfigurable accelerator (CGRA) providing memory elements with spin transfer torque type non-volatile memory technology to keep data when the power gating is applied. Here, in order to reduce the energy for storing data into non-volatile Flip Flops (NVFF)s, a verification mechanism is introduced. The data are written with a storing time much shorter than usual. If the verification result is not correct, the next trial is done until all results are verified. This approach can omit unnecessary energy for using long writing time with margin considering variation and temperature. For NVCMA, we propose a power manager which controls store, restore, verification, sleep-down and wake-up by extending micro-instructions of the original CMA. Sophisticated power management both for storing data into NVFFs and power gating is integrated into the application program, and the content of data memory can be stored in NVFFs as required as well as configuration data and micro-instructions. Total NVFFs are divided into 10 independent domains which can be controlled independently. Power management instructions are designed so as to reduce the number of instructions as possible by using the bit-map registers and compound instructions. By using the short store with verification, the energy for storing data was reduced by 30% in average. The ever-on leakage power is just about 4% of the total leakage which can be saved by the power gating. Compared with the hard-wired implementation, the proposed power manager increases the area by 17.7%, yet the total area overhead is only 4%.

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Designing High-Performance Interconnection Networks with Host-Switch Graphs

Yasudo R., Koibuchi M., Nakano K., Matsutani H., Amano H.

IEEE Transactions on Parallel and Distributed Systems （IEEE Transactions on Parallel and Distributed Systems） 30 （ 2 ） 315 - 330 2019年02月

ISSN 10459219

This paper aims at establishing a method for designing high-performance network topologies to bridge a gap between theoretical and practical studies. To this end, we present a novel graph called a host-switch graph, which consists of host vertices and switch vertices with maximum degree 1 and r, respectively. This graph represents a network topology of a practical parallel/distributed computer system with host computers connected by r-port switches. We discuss important metrics for designing high-performance interconnection networks: the host-to-host average shortest path length (h-ASPL) and the bisection width (BiW). In particular, we explore a method for constructing host-switch graphs with low h-ASPL and high BiW that connect the fixed number of hosts via any number of r-port switches. We demonstrate that the number of switches that provides the minimum h-ASPL can mathematically be approximated, and the minimum number of switches that provides a certain BiW can experimentally be approximated. On the basis of the approximations, we propose a randomized algorithm for searching host-switch graphs. We then apply the graphs to interconnection networks and compare them with typical network topologies. As compared with the torus, the dragonfly, and the fat-tree, our networks attain higher performance and smaller power and costs.

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A fine-grained multicasting of configuration data for coarse-grained reconfigurable architectures

Kojima T., Amano H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems） E102D （ 7 ） 1247 - 1256 2019年

ISSN 09168532

A novel configuration data compression technique for coarse-grained reconfigurable architectures (CGRAs) is proposed. Reducing the size of configuration data of CGRAs shortens the reconfiguration time especially when the communication bandwidth between a CGRA and a host CPU is limited. In addition, it saves energy consumption of configuration cache and controller. The proposed technique is based on a multicast configuration technique called RoMultiC, which reduces the configuration time by multicasting the same data to multiple PEs (Processing Elements) with two bit-maps. Scheduling algorithms for an optimizing the order of multicasting have been proposed. However, the multicasting is possible only if each PE has completely the same configuration. In general, configuration data for CGRAs can be divided into some fields like machine code formats of general perpose CPUs. The proposed scheme confines a part of fields for multicasting so that the possibility of multicasting more PEs can be increased. This paper analyzes algorithms to find a configuration pattern which maximizes the number of multicasted PEs. We implemented the proposed scheme to CMA (Cool Mega Array), a straight forward CGRA as a case study. Experimental results show that the proposed method achieves 40.0% smaller configuration than a previous method for an image processing application at maximum. The exploration of the multicasted grain size reveals the effective grain size for each algorithm. Furthermore, since both a dynamic power consumption of the configuration controller and a configuration time are improved, it achieves 50.1% reduction of the energy consumption for the configuration with a negligible area overhead.

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Level-Shifter-Less Approach for Multi-V<inf>DD</inf> SoC Design to Employ Body Bias Control in FD-SOI

Usami K., Kogure S., Yoshida Y., Magasaki R., Amano H.

IFIP Advances in Information and Communication Technology （IFIP Advances in Information and Communication Technology） 500 1 - 21 2019年

ISSN 18684238

Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) at pMOS transistors in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip showed that the chip applying the LSL approach correctly operates at VDDL = 0.6 V and VDDH = 1.2 V under 2 V pMOS RBB while suppressing the static dc current in the VDDH domain. We also demonstrate that adaptive RBB control for pMOS can maintain effectiveness of this approach under process and temperature variations.

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K-Optimized Path Routing for High-Throughput Data Center Networks

Kawano R., Yasudo R., Matsutani H., Amano H.

Proceedings - 2018 6th International Symposium on Computing and Networking, CANDAR 2018 （Proceedings - 2018 6th International Symposium on Computing and Networking, CANDAR 2018） 99 - 105 2018年12月

Network throughput has become an important issue for big-data analysis on Warehouse-Scale Computing (WSC) systems. It has been reported that randomly-connected inter-switch networks can enlarge the network throughput. For irregular networks, a multi-path routing method called k-shortest path routing is conventionally utilized. However, it cannot efficiently exploit longer-than-shortest paths that would be detour paths to avoid bottlenecks. In this work, a novel routing method called k-optimized path routing to achieve high throughput is proposed for irregular networks. We introduce a heuristic to select detour paths that can avoid bottlenecks in the network to improve the network throughput. Experimental results show that the proposed k-optimized path routing can improve the throughput by up to 133 % compared to the conventional k-shortest path routing. Moreover, it can improve the network bandwidth while maintaining the low network latency.

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An extension of a temperature modeling tool hotspot 6.0 for castle-of-chips stacking

Totoki T., Koibuchi M., Amano H.

Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018 （Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018） 363 - 369 2018年12月

HotSpot is an open source analysis tool for estimating temperature of both 2D and 3D chip stacks. It counts both the primary path of the heat transfer through the heat-sink and the secondary path through the print circuit board. It can estimate the temperature of chips. However, HotSpot-6.0 cannot treat a complicated chip stacking such as the castle of chips (CoC) with inductive wireless coupling through-chip interface (TCI). Therefore, in this report we have extended the HotSpot simulator and updated it in order to evaluate CoC. Compared to the original HotSpot, the extended version of HotSpot had an average execution time increase of about 6% when evaluating the same vertical stacking. The execution time of CoC with the same number of chips is shorter than when executing vertical stacking, but when the number of layers is the same, the execution time is almost equal. Moreover, our design considers high productivity, e.g. it can easily set air cooling, oil cooling, water cooling evaluation and chip rotation setting.

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C4: An FPGA-based compression algorithm for expether

Shimura H., Noda H., Amano H.

PCI Express (PCIe) has been widely used as an I/O bus connecting CPU and GPUs. In order to resolve the limitation of the number of PCIe ports, NEC Corporation developed ExpEther for expanding PCIe to Ethernet. Since Ethernet often becomes a bottleneck of communication, a conventional research proposed to implement a compression/decompression mechanism by using existing data compression mechanisms to reduce the size of data transferring on Ethernet. However, data compression mechanisms used in the research were only efficient for a limited input data pattern. In this paper, we proposed a novel data compression algorithm called C4, and implemented it on Xilinx Virtex-7 FPGA as an experimental environment of ExpEther. As a result, the proposed method can reduce the transfer time by 52.5%, superior to 49.7% with the conventional method. According to the evaluation of the hardware resource utilization rate, we showed that the proposed algorithm can be implemented in the FPGA used in the ExpEther NIC.

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An trace-driven performance prediction method for exploring noc design optimization

Niwa N., Totoki T., Matsutani H., Koibuchi M., Amano H.

The performance prediction for a NoC-based Chip Multi-Processor (CMP) is one of the main design concerns. Generally, there is a trade-off between accuracy and time overhead on the performance prediction of computer systems. In particular, the time overhead is proportional or exponential to the number of cores when using a cycle-accurate full-system simulation, such as gem5. In this study, we propose an accurate and scalable method to predict the influence of design NoC parameters on its performance. Our method counts the number of execution cycles when employing the target NoC based on the statistics of one-time execution of a full-system simulation using a fully-connected NoC. To evaluate the accuracy and execution time overhead, we use the case that randomly generates allocations of processors with 3D mesh topology NoC. Its Mean Absolute Percentage Error of the estimated cycles is about 4.7%, and the Maximum Absolute Percentage Error is about 8.5%.

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FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks

Wei K., Honda K., Amano H.

Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018 （Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018） 428 - 431 2018年12月

We propose an autonomous vehicle controlled by FPGAs. In our design, considering embedded systems, we apply the binarized neural networks (BNNs) which can realize a satis-fying result in high speed and accuracy to recognize pedestrians and some obstacles on a given road. To detect the traffic light, a passive camera-based pipeline is applied. Furthermore, the implementation of road lane detection is based on color selection algorithm, Canny Edge Detection, and Hough Transformation. The proposed design is realized by two Xilinx boards: PYNQ-Z1 and Zynq-Xc7Z010. These two FPGA boards cooperate with each other through a shared network cable. In the proposed design, the resource used by Zynq-Xc7Z010 can be greatly reduced and the inference time on the FPGA has been thousands times faster than the software implementation.

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Performance Estimation for Exascale Reconfigurable Dataflow Platforms

Yasudo R., Coutinho J., Varbanescu A., Luk W., Amano H., Becker T.

The next generation high-performance computing platforms will need to support exascale computing. A promising path in achieving exascale is to embrace heterogeneity and specialised computing in the form of reconfigurable accelerators. However, assessing the feasibility of heterogeneous exascale systems requires fast and accurate performance prediction. This paper proposes PERKS, a novel performance estimation frame-work for reconfigurable dataflow platforms (RDPs). PERKS uses machine and application parameters to build an analytical model for predicting the performance of multi-Accelerator systems. Moreover, model calibration is automatic, making the model flexible and usable for different machine configurations and applications. Our experimental results demonstrate that PERKS can predict the performance of current workloads and RDPs with an accuracy above 95%. We also demonstrate how the modelling scales to exascale workloads and exascale platforms.

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Adaptive body bias control scheme for ultra low-power network-on-chip systems

Ben Ahmed A., Okuhara H., Matsutani H., Koibuchi M., Amano H.

Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018 （Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018） 146 - 153 2018年11月

Over the past decade, the power consumption has been one of the main design challenges in Network-on-Chips (NoCs) as it significantly defines the performance of a given Chip-Multiprocessor (CMP). Body bias control is one of the solutions that provide an efficient trade-off between leakage power and performance. However, employing such a method is not straightforward since several factors should be taken into consideration, especially when adaptively implemented on-chip. In this paper, we propose a new router design and on-chip body bias control mechanism to adaptively control the body bias voltages supply in ultra low-power NoC systems. With the help of a light-weight monitoring circuit, the proposed router predicts the traffic load at each input-port and accordingly adjusts its pipeline depth in a fine-grained fashion. To satisfy the timing constraints, the router adaptively supplies each one of its input-ports with the appropriate body bias voltages to either boost the performance or to reduce the leakage power at the standby state. The evaluation results, using the SOTB 65nm Fully Depleted Silicon On Insulator (FD-SOI) technology, shows the ability of the proposed router in reducing both dynamic and static energies. When compared to two fixed-pipeline baseline routers (3-stages and 2-stages), the total energy reduction could reach up to 67% and 59%, respectively. At the same time, a reasonable performance tendency can be obtained with less than 6% area overhead.

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Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami K., Akaike J., Akiba S., Kudo M., Amano H., Ikezoe T., Hiraga K., Shuto Y., Yagami K.

Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018 （Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018） 91 - 98 2018年11月

A non-volatile flip-flop (NVFF) introducing MTJ has many strong points in high endurance and read/write performance, and hence is very attractive as a component to be used for power gating of sequential circuits. However, large write-energy to MTJ becomes a big obstacle in achieving low energy dissipation. This paper proposes a NVFF circuit enabling to verify the success of a store operation to MTJ and retry it by prolonging the store time. We designed a NVFF circuit with this feature and applied it to 20,000 flip-flops in a dynamically reconfigurable processor (DRP). We conducted simulations considering write time variations caused by various factors such as process variations and thermal fluctuations. The results demonstrated that the proposed approach reduces store energy by 35-36% at four image-processing applications and the break-even time (BET) for non-volatile power gating is 2.0-2.9us at the 0.004% write error rate, at which no failures occur for the total number of NVFFs in the DRP.

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A configuration data multicasting method for coarse-grained reconfigurable architectures

Kojima T., Amano H.

Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018 （Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018） 239 - 242 2018年11月

This paper proposes a novel configuration data compression technique for coarse-grained reconfigurable architectures (CGRAs). The proposed technique is based on a multicast configuration technique called RoMultiC, which reduces the configuration time by multicasting the same data to multiple PEs(Processing Elements) with two bit-maps. Scheduling algorithms for an optimizing the order of multicasting have been proposed. In general, configuration data for CGRAs can be divided into some fields like machine code formats. The proposed scheme confines a part of fields for multicasting so that the possibility of multicasting more PEs can be increased. This paper analyzes algorithms to find a configuration pattern which maximizes the number of multicasted PEs. We implemented the proposed scheme to CMA (Cool Mega Array), a straight forward CGRA as a case study. Experimental results show that the proposed method achieves 40.0% smaller configuration for an image processing application at maximum. Furthermore, it achieves 35.6% reduction of the power consumption for the configuration with a negligible area overhead.

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天野 英晴

論文 - 天野 英晴

天野　英晴

論文 - 天野　英晴