研究者詳細 - 天野　英晴

論文 - 天野　英晴

分割表示 243 件中 41 - 60 件目／全件表示 >>

A Method of Partitioning Convolutional Layer to Multiple FPGAs

Iizuka K., Ito K., Hironaka K., Amano H.

Proceedings - International SoC Design Conference, ISOCC 2020 （Proceedings - International SoC Design Conference, ISOCC 2020） 25 - 26 2020年10月

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Nishio S., Pan Y., Satoh T., Amano H., Meter R.V.

ACM Journal on Emerging Technologies in Computing Systems （ACM Journal on Emerging Technologies in Computing Systems） 16 （ 3 ） 2020年07月

ISSN 15504832

NISQ (Noisy, Intermediate-Scale Quantum) computing requires error mitigation to achieve meaningful computation. Our compilation tool development focuses on the fact that the error rates of individual qubits are not equal, with a goal of maximizing the success probability of real-world subroutines such as an adder circuit. We begin by establishing a metric for choosing among possible paths and circuit alternatives for executing gates between variables placed far apart within the processor, and test our approach on two IBM 20-qubit systems named Tokyo and Poughkeepsie. We find that a single-number metric describing the fidelity of individual gates is a useful but imperfect guide. Our compiler uses this subsystem and maps complete circuits onto the machine using a beam search-based heuristic that will scale as processor and program sizes grow. To evaluate the whole compilation process, we compiled and executed adder circuits, then calculated the Kullback-Leibler divergence (KL-divergence, a measure of the distance between two probability distributions). For a circuit within the capabilities of the hardware, our compilation increases estimated success probability and reduces KL-divergence relative to an error-oblivious placement.

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Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Usami K., Akiba S., Amano H., Ikezoe T., Hiraga K., Suzuki K., Kanda Y.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings （IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings） 2020年04月

Non-volatile power gating introducing MTJ into a flip-flop is an attractive technique for IoT devices. However, the time required for a successful store operation to MTJs varies at non-volatile flip-flops (NVFFs) due to process and voltage variation. This paper describes implementation and real-chip evaluation of a non-volatile Coarse Grained Reconfigurable Array employing verify-and-retryable NVFF (VR-NVFF) circuits and two-step store (TSS) control by instructions of a microcontroller. Test chips fabricated in a 40nm CMOS/MTJ hybrid technology have demonstrated that the TSS approach using both 30ns/100ns store operations reduces power by 37-42% when running an image processing program at 100MHz.

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Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch

Itsubo T., Koibuchi M., Amano H., Matsutani H.

Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020 （Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020） 102 - 109 2020年03月

A back-propagation algorithm following a gradient descent approach is used for training deep neural networks. Since it iteratively performs a large number of matrix operations to compute the gradients, GPUs (Graphics Processing Units) are efficient especially for the training phase. Thus, a cluster of computers each of which equips multiple GPUs can significantly accelerate the training phase. Although the gradient computation is still a major bottleneck of the training, gradient aggregation and parameter optimization impose both communication and computation overheads, which should also be reduced for further shortening the training time. To address this issue, in this paper, multiple GPUs are interconnected with a PCI Express (PCIe) over 10 Gbit Ethernet (10GbE) technology. Since these remote GPUs are interconnected via network switches, gradient aggregation and optimizers (e.g., SGD, Adagrad, Adam, and SMORMS3) are offloaded to an FPGA-based network switch between a host machine and remote GPUs; thus, the gradient aggregation and optimization are completed in the network. Evaluation results using four remote GPUs connected via the FPGA-based 10GbE switch that implements the four optimizers demonstrate that these optimization algorithms are accelerated by up to 3. 0x and 1. 25x compared to CPU and GPU implementations, respectively. Also, the gradient aggregation throughput by the FPGA-based switch achieves 98.3% of the 10GbE line rate.

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Body bias optimization for real-time systems

Torres C.C.C., Yasudo R., Amano H.

Journal of Low Power Electronics and Applications （Journal of Low Power Electronics and Applications） 10 （ 1 ） 2020年03月

The energy of real-time systems for embedded usage needs to be efficient without affecting the system’s ability to meet task deadlines. Dynamic body bias (BB) scaling is a promising approach to managing leakage energy and operational speed, especially for system-on-insulator devices. However, traditional energy models cannot deal with the overhead of adjusting the BB voltage; thus, the models are not accurate. This paper presents a more accurate model for calculating energy overhead using an analytical double exponential expression for dynamic BB scaling and an optimization method based on nonlinear programming with consideration of the real-chip parameter constraints. The use of the proposed model resulted in an energy reduction of about 32% at lower frequencies in comparison with the conventional model. Moreover, the energy overhead was reduced to approximately 14% of the total energy consumption. This methodology provides a framework and design guidelines for real-time systems and computer-aided design.

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Implementation of FM-Index Based Pattern Search on a Multi-FPGA System

Ullah M.M.I., Ben Ahmed A., Amano H.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) （Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)） 12083 LNCS 376 - 391 2020年

ISSN 03029743

Pattern matching is a versatile task which has a variety of applications including genome sequencing as a major application. During the analysis, short read mapping technique is used where short DNA sequences are mapped relative to a known reference sequence. This paper discusses the use of reconfigurable hardware to accelerate the short read mapping problem. The proposed design is based on the FM-index algorithm. Although several pattern matching techniques are available, FM-index based pattern search is perfectly suitable for genome sequencing due to the fastest mapping from known indices. In order to make use of inherent parallelism, a multi-FPGA system called Flow-in-Cloud (FiC) is used. FiC consists of multiple boards, mounting middle scale Xilinx’s FPGAs and SDRAMs, which are tightly coupled with high speed serial links. By distributing the input data transfer with I/O ring network and broadcasting I-Table, C-Table and Suffix-Array with the board-to-board interconnection network, about 10 times performance improvement was achieved when compared to the software implementation. Since the proposed method is scalable to the number of boards, we can obtain the required performance by increasing the number of boards.

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Designing low-diameter interconnection networks with multi-ported host-switch graphs

Yasudo R., Nakano K., Koibuchi M., Matsutani H., Amano H.

Concurrency Computation （Concurrency Computation） 2020年

ISSN 15320626

A host-switch graph was originally proposed as a graph that represents a network topology of a computer systems with 1-port host computers and (Formula presented.) -port switches. It has been studied from both theoretical and practical aspects in terms of the diameter, the average shortest path length, and the performance of real applications. In recent high-performance computing systems, however, a host computer is connected to multiple switches by using InfiniBand, NVSwitch, or Omni-Path, and consequently they provide high bandwidths. Since a host-switch graph cannot represent such systems, this article extends a host-switch graph so that it can represent such systems. As a result, a host-switch graph can include multi-ported hosts. Furthermore, we propose to use multi-port hosts for reducing the diameter. We show that the diameter minimization is equivalent to solving the degree diameter problem for bipartite graphs of diameter three. Our experimental results show that we can drastically reduce the diameter as well as increasing the bandwidth and improves performance of MPI applications by up to 162% as compared with networks with single-ported hosts.

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A generalized theory based on the turn model for deadlock-free irregular networks

Kawano R., Yasudo R., Matsutani H., Koibuchi M., Amano H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems） E103D （ 1 ） 101 - 110 2020年

ISSN 09168532

Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve the performance of parallel applications. However, these networks usually suffer from deadlocks in routing packets when using a naive minimal path routing algorithm. To solve this problem, we focus attention on a lately proposed theory that generalizes the turn model to maintain the network performance with deadlock-freedom. The theorems remain a challenge of applying themselves to arbitrary topologies including fully irregular networks. In this paper, we advance the theorems to completely general ones. Moreover, we provide a feasible implementation of a deadlock-free routing method based on our advanced theorem. Experimental results show that the routing method based on our proposed theorem can improve the network throughput by up to 138 % compared to a conventional deterministic minimal routing method. Moreover, when utilized as the escape path in Duato’s protocol, it can improve the throughput by up to 26.3 % compared with the conventional up*/down* routing.

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A coarse-grained reconfigurable architecture with a fault tolerant non-volatile configurable memory

Ikezoe T., Kojima T., Amano H.

Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019 （Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019） 2019-December 81 - 89 2019年12月

Recent IoT devices require extremely low standby power consumption, while a certain performance is needed during the active time, and Coarse Grain Reconfigurable Arrays (CGRAs) are suitable because of their high energy efficiency. However, even in CGRAs, the leakage power for its configuration memory must be reduced. Although the power gating is a popular technique, the data in flip-flops and memory are lost so they must be retrieved after the wake-up. Recovering everything requires numerous state transitions and considerable overhead both on its execution time and energy. To address the problem, Non-volatile Cool Mega Array (NVCMA), a CGRA providing non-volatile flip-flops (NVFFs) with spin transfer torque type non-volatile memory (NVM) technology has been developed. However, in general, non-volatile memory technologies have problems with reliability. Some NVFFs are stacked-at-0/1, and cannot store the data in a certain possibility. To improve the chip yield, we propose a mapping algorithm to avoid faulty processing elements of the CGRA caused by the erroneous configuration data. Then, we also propose a method to add an error-correcting code (ECC) mechanism to NVFFs used for the configuration and constant memory. The proposed method was applied to NVCMA to evaluate the availability rate and reduction of write time. By using both methods, the 99.4% availability ratio is achieved with 0.1% probability of faulty FFs, while almost no chips are available without using them. The energy for storing data becomes about 2.28 times because of the hardware overhead of ECC but the proposed method can save 11.1% of the storing energy on average.

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A rapid optimization method for visual indirect SLAM using a subset of feature points

Kazami R., Amano H.

Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019 （Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019） 275 - 279 2019年11月

In this paper, we propose a novel optimization method for indirect Simultaneous Localization And Mapping(SLAM). This method avoids error-intended map points using a random subset of extracted feature points. As a result, this method making the calculation time short at the cost of some accuracy. The published code of ORB-SLAM2 has longer calculation time compared to other systems such as Semi-direct odometry(SVO). This is due to feature extraction time of an indirect method, which makes the indirect methods robust. However, considering CPU performance on edge devices like MAVs, a lightweight system is welcome. ORB-SLAM2 is widely known as a robust and rapid visual Simultaneous-Localization-And-Mapping (vSLAM) method than before. It extracts FAST feature points from a given image and optimizes using all of these points for camera-posing estimation. However, some points disturb accurate estimation causing large reprojection error after optimization. Although these points are eliminated as outliers after optimization, they may be an obstacle for accurate pose estimation. To make this system more robust and more rapid, We suggest an improved method to estimate camera-posing, where we use a subset of extracted points for estimation, avoiding mixing large-reprojection-error points in bundle adjustment. The experimental results on the SLAM benchmark dataset KITTI odometry demonstrated that the proposed method outperformed the original implementation of ORB-SLAM2 from the viewpoint of calculation time.

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Deadlock-free layered routing for infiniband networks

Kawano R., Matsutani H., Amano H.

End-to-end network latency has become an important issue for big data processing on large-scale and heterogeneous data centers. To realize them, a low-latency inter-switch network is required. In recent years, a novel network based on a random regular graph such as Jellyfish has been proposed as a solution to these problems. To realize this network on Infiniband, we explore layered shortest path routing that guarantees deadlock freedom. Infiniband can avoid deadlocks by using Virtual Lane (VL), which is a QoS guarantee mechanism. However, the output VL is indirectly determined by using Service Level (SL) held by each packet. In this research, to minimize the number of consumed SLs, we propose an algorithm based on a graph coloring problem to assign SLs to all source-destination pairs. The proposed method can reduce the number of consumed SLs by up to 38%compared to the conventional SL mapping method.

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Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel

Okamoto Y., Amano H.

Radiation transfer (RT) is an important physical processes of energy transfer in the form of electromagnetic wave, and ART method is a ray-tracing for computing RT of re-connected photons in the simulation of protogalaxies formation. It requires a heavy computational power and complicated memory accesses which are not suitable to acceleration with GPUs. Here, for the future use of FPGA-in-Cloud, the acceleration of ART method with SDAccel on Xilinx's cost efficient FPGA board KCU1500 was tried. Although the execution time was not reduced compared with the host CPU with various combination of derivatives, the energy consumption was reduced to 1/3.35.

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Real chip performance evaluation on through chip interface IP for renesas SOTB 65nm process

Kayashima H., Kojima T., Okuhara H., Shidei T., Amano H.

The building block computing system can build various systems by connecting small-sized chips with inductive coupling wireless chip-to-chip connection TCI (Through Chip Interface). First, we have developed TCI IP by using the Renesas 65nm SOTB process and verified it with a simple TEG chip. Then several family chips have been developed with the IP; Geyser-TT (MIPS R3000 compatible processor), SNACC (neural network accelerator), CC-SOTB2 (improved CGRA), KVS (the accelerator for Key-Value-Store database), and SMTT (Shared Memory for Twin Tower). All of these chips worked alone without problems. However, when these chips were stacked to construct a system, problems were found on some combination of chips that TCI did not operate as designed. To investigate the cause of the trouble, we have developed a sophisticated tester chip called the TCI Tester. It provides three modes: RAW mode in which handshake lines can be directly controlled, CUBE mode in which the TCI Tester can write the data into the stacked target chips, and LOOP mode which allows continuous write and read operation for a long time working test. Through the evaluation by using a two-TCI Tester stacking system, the following appeared. (1) The maximum transfer frequency of the TCI IP is much lower than 50MHz which is the target value. Only 14MHz for the downward and 9MHz for the upward. (2) The performance of the upward transfer is lower than that of the downward. The poor upward data transfer performance comes from that the voltage drop on the power grid becomes large because of the location of the upward transmitter coil. We can improve it by increasing the number of power pads for the transmitter and enhancing the power grid. However, with the low transfer frequency, the TCI IP worked more than a day continuously.

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A Preliminary evaluation of building block computing systems

Terashima S., Kojima T., Okuhara H., Musha K., Amano H., Sakamoto R., Kondo M., Namiki M.

Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019 （Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019） 312 - 319 2019年10月

A building block computing system with inductive coupling Through Chip Interface (TCI) consists of 3-D chip stack, each of which is small dedicated chips. By changing the combination of stacked chips, various types of systems can be built. A MIPS R3000 compatible processor GeyserTT, a neural network accelerator SNACC and the shared memory for building the twin-Tower of chips SMTT have been developed with a Renesas 65nm low leakage CMOS process. They provide the TCI IP (Intellectual Property), and an escalator network is built just by stacking them. This paper shows each chip evaluation results and performance estimation of stacking them with the RTL simulator. The performance of the single-Tower and twin-Tower configuration is estimated by RTL simulation when a part of Alexnet is implemented. The evaluation results showed that the single-Tower configuration with GeyserTT+SNACC achieved about twice performance as the case with GeyserTT. Also, experimental results using each of the single real chip showed that all of them work at least 50MHz with extremely low power consumption. The twin-Tower configuration achieved about 2x of the single-Tower, that is about 6x of GeyserTT. The power consumption was about 276mW for the single-Tower and 496mW for the twin-Tower.

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Fpga/python co-design for lane line detection on a pynq-z1 board

Honda K., Wei K., Amano H.

This paper presents the implementation of lane line detection on FPGA and Python. Lane line detection consists of three functions, median blur, adaptive threshold, and Hough transform. We implemented only accumulation of Hough transform on FPGA. Although the Hough transform cannot be implemented on a low-end FPGA board if implemented directly, by reducing ρθ space, it was successfully implemented on a low-end FPGA board. The rest of the Hough transform was implemented using Python's NumPy and SciPy, and OpenCV. Although it was very easy to write, it did not become a bottleneck for the whole process because of its effectiveness. As a result, we could achieve a 3.9x speedup compared to OpenCV and kept the developing cost down. When implementing median blur and adaptive threshold on an FPGA, we could achieve a 6.34x speedup.

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A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration

Okuhara H., Kazami R., Amano H.

In this work, we present a low-overhead performance monitor which can emulate the maximum operational frequency of a target system by utilizing a delay chain so as to achieve efficient adaptive voltage control. The proposed monitor can be fully built by logic cells provided by general PDKs; thus, an automatic cell-based design flow can be used for its implementation. In addition, interconnect delay behaviors can also be imitated by exploiting wires which are automatically routed. In order to validate our concept, the proposed monitor is fabricated with a 65-nm Fully Depleted Silicon on Insulator (FD-SOI) technology. Real chip experiments reveal that the automated layout design can achieve the reasonable ability to delay emulation. Indeed, when the maximum operational frequency of a CNN accelerator is emulated, the proposed SDM achieved several percents of the performance tracking error. Also, its power overhead is only few percents.

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A Stdm (static time division multiplexing) switch on a multi-fpga system

Azegami K., Musha K., Hironaka K., Ben Ahmed A., Koibuch M., Hu Y., Amano H.

FPGAs can be a promising accelerator used for MEC (Multi-Access Edge Computing) which provides timing critical services for a number of terminals at the base stations near from edges. Although a high-end FPGA can support a fixed latency computation with a relatively small power consumption, they are expensive and the available acceleration circuits are limited into a size of single FPGA. FiC (Flow-in-Cloud) has been developed for building a virtual large FPGA from a number of middle-range economical FPGAs connected with high speed serial links. Although the current target of FiC is cloud computing, it is more suitable for the future MEC, because huge hardware resource can be supported with small cost. One of the problem to use such multi-FPGA systems for timing critical computation is network uncertainty. With a common packet switching, the computation speed is influenced with the network traffic. That is, the fixed latency computation which could be supported by a single FPGA is hard to be supported with multi-FPGA systems using common packet switching networks. In order to address this problem, we introduced STDM (Static Time Division Multiplexing) switch in the FiC system. Since the STDM always supports a constant communication latency, transfer time can be estimated beforehand. Through the implementation of the STDM switch on the FPGA board for FiC, it appeared that the utilization ratio of the LUTs for the STDM switch is smaller than 14%. The required number of slots is less than 16 even for a system with 256 nodes. We implemented the Conjugate Gradient method, which includes all-To-All communication, on 4x2 FiC system. It achieved 17.9 times performance improvement of Intel E5-2667 2.90GHz CPU with 6 cores.

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Demonstration of flow-in-cloud: A multi-FPGA system

Hironaka K., Iizuka K., Ben Ahmed A., Imdad Ullah M.M., Yamauchi Y., Sun Y., Yamakura M., Hiruma A., Amano H.

Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019 （Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019） 417 - 418 2019年09月

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Demonstration of low power stream processing using a variable pipelined CGRA

Kojima T., Ando N., Matsushita Y., Amano H.

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Multi-FPGA Management on Flow-in-Cloud Prototype System

Hironaka K., Akram B.A., Amano H.

Proceedings - 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2019 （Proceedings - 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2019） 443 - 448 2019年07月

FiC (Flow-in-Cloud) is a multi-FPGA system to achieve monolithic large scale FPGA with across multiple FPGAs for computational-heavy applications. The FiC system employs multiple economical mid-range FPGAs and connect them directly with flexible and high bandwidth interconnection network. We developed FiCSW board as a 1st generation of FPGA board in the FiC project. The FiCSW design, since the FPGA is used as both computational resource and the network circuit switch, there are no host server for FPGA needed like other server-based multi FPGA architecture. This design strategy helps scalable FPGA fabric in low-cost. However, from the system manageability's perspective, the strategy is hard to handle multiple FPGA nodes without management system. In this paper, we mainly focused on the management system on the FiCSW multi-FPGA system, introducing the system architecture and implementation, and working application on the FiCSW prototype system.

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天野 英晴

論文 - 天野 英晴

天野　英晴

論文 - 天野　英晴