論文 - 天野　英晴

CLAHE implementation and evaluation on a low-end FPGA board by high-level synthesis

Honda K., Wei K., Arai M., Amano H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems）  E104D （ 12 ） 2048 - 2056 2021年

ISSN  09168532

　概要を見る

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing to improve the quality of the image. Contrast Limited Adaptive Histogram Equalization (CLAHE) is one of such techniques to improve the quality of the image for the side mirror camera, which requires a large computation performance. Here, an implementation method of CLAHE on a low-end FPGA board by high-level synthesis is proposed. CLAHE has two main processing parts: cumulative distribution function (CDF) generation, and bilinear interpolation. During the CDF generation, the effect of increasing loop initiation interval can be greatly reduced by placing multiple Processing Elements (PEs). and during the interpolation, latency and BRAM usage were reduced by revising how to hold CDF and calculation method. Finally, by connecting each module with streaming interfaces, using data flow pragmas, overlapping processing, and hiding data transfer, our HLS implementation achieved a comparable result to that of HDL. We parameterized the components of the algorithm so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga clahe.

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CASE: CNN Acceleration for Speech-Classification in Edge-Computing

Gulzar H., Shakeel M., Nishida K., Itoyama K., Nakadai K., Amano H.

Proceedings - 2021 IEEE Cloud Summit, Cloud Summit 2021 （Proceedings - 2021 IEEE Cloud Summit, Cloud Summit 2021）     63 - 68 2021年

　概要を見る

High performance of Machine Learning algorithms has enabled numerous applications based upon speech interface in our daily life, but most of the frameworks use computationally expensive algorithms deployed on cloud servers as speech recognition engines. With the recent surge in the number of IoT devices, a robust and scalable solution for enabling AI applications on IoT devices is inevitable in form of edge computing. In this paper, we propose the application of Systemon-Chip (SoC) powered edge computing device as accelerator for speech commands classification using Convolutional Neural Network (CNN). Different aspects affecting the CNN performance are explored and an efficient and light-weight model named as CASENet is proposed which achieves state-of-the-art performance with significantly smaller number of parameters and operations. Efficient extraction of useful features from audio signal helped to maintain high accuracy with a 6X smaller number of parameters, making CASENet the smallest CNN in comparison to similarly performing networks. Light-weight nature of the model has led to achieve 96.45% validation accuracy with a 14X smaller number of operations which makes it ideal for low-power IoT and edge devices. A CNN accelerator is designed and deployed on FPGA part of SoC equipped edge server device. The hardware accelerator helped to improve the inference latency of speech command by a 6.7X factor as compared to standard implementation. Memory, computational cost and latency are the most important metrics for selecting a model to deploy on edge computing devices, and CASENet along with the accelerator surpasses all of these requirements.

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Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface

Kayashima H., Amano H.

Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 （Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021）     292 - 296 2021年

　概要を見る

The building block computing system can build several systems by stacking small chips with inductive coupling wireless chip-to-chip connection TCI (Through Chip Interface). TCI IP (Intellectual Property) was developed by using the Renesas 65nm SOTB process, and several family chips have been developed with the IP. Although all of the chips worked alone without problems, when they were stacked to construct a system, problems were found on some combinations of chips that TCI did not work as designed. This paper analyzes the resistances of power grid of chips with IPs from their layout to investigate the reason of the problems. Then, the voltage drop is estimated with the model built from the real chip evaluation. The analysis results appeared that in some chips, the resistances of the power grid are more than double of the target value, and because of the voltage drop, the supply voltage given to the IP of the largest chip SMTT is about the half of given to the power pad. Although it comes from the limitation of the I/O pads for chip stacking and fixed location of TCI IPs, we must take special care of the design of the transmitter power grid.

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An FPGA-based optimizer design for distributed deep learning with multiple GPUs

Itsubo T., Koibuchi M., Amano H., Matsutani H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems）  E104D （ 12 ） 2057 - 2067 2021年

ISSN  09168532

　概要を見る

Since deep learning workloads perform a large number of matrix operations on training data, GPUs (Graphics Processing Units) are efficient especially for the training phase. A cluster of computers each of which equips multiple GPUs can significantly accelerate the deep learning workloads. More specifically, a back-propagation algorithm following a gradient descent approach is used for the training. Although the gradient computation is still a major bottleneck of the training, gradient aggregation and optimization impose both communication and computation overheads, which should also be reduced for further shortening the training time. To address this issue, in this paper, multiple GPUs are interconnected with a PCI Express (PCIe) over 10Gbit Ethernet (10GbE) technology. Since these remote GPUs are interconnected with network switches, gradient aggregation and optimizers (e.g., SGD, AdaGrad, Adam, and SMORMS3) are offloaded to FPGA-based 10GbE switches between remote GPUs; thus, the gradient aggregation and parameter optimization are completed in the network. The proposed FPGA-based 10GbE switches with the four optimizers are implemented on NetFPGA-SUME board. Their resource utilizations are increased by PEs for the optimizers, and they consume up to 56% of the resources. Evaluation results using four remote GPUs connected via the proposed FPGA-based switch demonstrate that these optimizers are accelerated by up to 3.0x and 1.25x compared to CPU and GPU implementations, respectively. Also, the gradient aggregation throughput by the FPGA-based switch achieves up to 98.3% of the 10GbE line rate.

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A multi-tenant resource management system for multi-FPGA systems

Yamakura M., Takano R., Ben Ahmed A., Sugaya M., Amano H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems）  E104D （ 12 ） 2078 - 2088 2021年

ISSN  09168532

　概要を見る

FPGA (Field Programmable Gate Array) based accelerators are attracting significant interest in cloud computing systems. Combining multi-FPGA systems with cloud computing brings a new perspective to the reconfigurable computing research. However, the multi-tenancy of a multi-FPGA system has not been fully discussed in the previous researches. In this paper, we propose a multi-tenant resource management system, named FiC-RM, for a multi-FPGA cloud system. FiC-RM provides users with a set of FPGA resources according to their requirements and allows them to exclusively access FPGA boards and the interconnection network. To achieve this, we propose a placement algorithm which is a key to efficiently share the limited resources. We demonstrate FiC-RM controls a practical scale multi-FPGA system. Moreover, Our simulation study shows that our placement algorithm achieved 3 to 4% improvement in the average resource usage and a 20-second reduction in the response time, compared to other existing naive algorithms.

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Parallel Implementation of CNN on Multi-FPGA Cluster

Fukushima Y., Iizuka K., Amano H.

Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021 （Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021）     77 - 83 2021年

　概要を見る

We developed a PYNQ cluster called M-KUBOS that consists of economical Zynq boards that are interconnected through low-cost high-performance GTH serial links. For the software environment, we employed the PYNQ open-source software platform. The PYNQ cluster is anticipated to be a multi-access edge computing (MEC) server for 5G mobile networks. We implemented the ResNet-50 inference accelerator on the PYNQ cluster for image recognition of MEC applications. By estimating the execution time of each ResNet-50 layer, layers of ResNet-50 were divided into four boards so that the execution time of each board would be as equal as possible for efficient pipeline processing. Owing to the PYNQ cluster in which FPGAs were directly connected by high-speed serial links, stream processing without network bottlenecks and pipeline processing between boards were readily realized. The implementation achieved 292 GOPS performance, 75.1 FPS throughput, and 5.15 GOPS/W power efficiency. It achieved 17 times faster speed and 86 times more power efficiency compared to the implementation on the CPU, and 3.8 times more power efficiency compared to the implementation on the GPU.

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Weight Least Square Filter for Improving the Quality of Depth Map on FPGA

Mao R., Wei K., Amano H., Kuno Y., Arai M.

Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 （Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021）     297 - 300 2021年

　概要を見る

The techniques based on measuring the distance between objects and the camera itself have made progress in recent years. Through this technology, the system used for 3D imaging will provide a great convenience for people's lives. In this project, we focus on optimizing depth maps with better quality for the 3D scene display system on the car. During the 3D imaging process, to calculate the distance between a certain location and one of the specific points of the scene, it will produce two depth maps computed from two images as an intermediate product for 3D imaging processing. However, there is a great number of invalid pixels that distance cannot be measured. In dealing with such drawbacks, post-filtering has been introduced as a solution. In this project, we propose implementing the Weight Least Square (WLS) filter on FPGA, which can fill the invalid pixels by using the results of neighboring pixels. Through our approach, we can improve the quality of the depth map on M-KUBOS. Besides that, the optimized memory usage can successfully suit the size of the memory on-chip, and a 69.29% acceleration compared to the ARM core.

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Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim

Yan Y.J., Amano H., Aono M., Ohkoda K., Fukuda S., Saito K., Kasai S.

2021 International Conference on Field-Programmable Technology, ICFPT 2021 （2021 International Conference on Field-Programmable Technology, ICFPT 2021）  2021年

　概要を見る

The Boolean satisfiability problem (SAT) is an NP-complete combinatorial optimization problem, where fast SAT solvers are useful for various smart society applications. Since these edge-oriented applications require time-critical control, a high speed SAT solver on FPGA is a promising approach. Here the authors propose a novel FPGA implementation of a bio-inspired stochastic local search algorithm called 'AmoebaSAT' on a Zynq board. Previous studies on FPGA-AmoebaSATs tackled relatively smaller-sized 3-SAT instances with a few hundred variables and found the solutions in several milli seconds. These implementations, however, adopted an instance-specific approach, which requires synthesis of FPGA configuration every time when the targeted instance is altered. In this paper, a slimmed version of AmoebaSAT named 'AmoebaSATslim,' which omits the most resource-consuming part of interactions among variables, is proposed. The FPGA-AmoebaSATslim enables to tackle significantly larger-sized 3-SAT instances, accepting 30,000 variables with 130, 800 clauses. It achieves up to approximately 24 times faster execution speed than the software-AmoebaSATslim implemented on a CPU of the x86 server.

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Remote dynamic reconfiguration of a multi-FPGA system FiC (flow-in-cloud)

Hironaka K., Iizuka K., Yamakura M., Ben Ahmed A., Amano H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems）  E104D （ 8 ） 1321 - 1331 2021年

ISSN  09168532

　概要を見る

Multi-FPGA systems have been receiving a lot of attention as a low cost and energy efficient system for Multi-access Edge Computing (MEC). For such purpose, a bare-metal multi-FPGA system called FiC (Flow-in-Cloud) is under development. In this paper, we introduce the FiC multi FPGA cluster which is applied partial reconfiguration (PR) FPGA design flow to support online user defined accelerator replacement while executing FPGA interconnection network and its low-level multiple FPGA management software called remote PR manager. With the remote PR manager, the user can define the FiC FPGA cluster setup by JSON and control the cluster from user application with the cooperation of simple cluster management tool / library called ficmgr on the client host and REST API service provider called ficwww on Raspberry Pi 3 (RPi3) on each node. According to the evaluation results with a prototype FiC FPGA cluster system with 12 nodes, using with online application replacement by PR and on-the-fly FPGA bitstream compression, the time for FPGA bitstream distribution was reduced to 1/17 and the total cluster setup time was reduced by 21∼57% than compared to cluster setup with full configuration FPGA bitstream.

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FiC-RNN: A multi-FPGA acceleration framework for deep recurrent neural networks

Sun Y., Amano H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems）  E103D （ 12 ） 2457 - 2462 2020年12月

ISSN  09168532

　概要を見る

Recurrent neural networks (RNNs) have been proven effective for sequence-based tasks thanks to their capability to process temporal information. In real-world systems, deep RNNs are more widely used to solve complicated tasks such as large-scale speech recognition and machine translation. However, the implementation of deep RNNs on traditional hardware platforms is inefficient due to long-range temporal dependence and irregular computation patterns within RNNs. This inefficiency manifests itself in the proportional increase in the latency of RNN inference with respect to the number of layers of deep RNNs on CPUs and GPUs. Previous work has focused mostly on optimizing and accelerating individual RNN cells. To make deep RNN inference fast and efficient, we propose an accelerator based on a multi-FPGA platform called Flow-in-Cloud (FiC). In this work, we show that the parallelism provided by the multi-FPGA system can be taken advantage of to scale up the inference of deep RNNs, by partitioning a large model onto several FPGAs, so that the latency stays close to constant with respect to increasing number of RNN layers. For single-layer and four-layer RNNs, our implementation achieves 31x and 61x speedup compared with an Intel CPU.

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Traffic-independent multi-path routing for high-throughput data center networks

Kawano R., Yasudo R., Matsutani H., Koibuchi M., Amano H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems）  E103D （ 12 ） 2471 - 2479 2020年12月

ISSN  09168532

　概要を見る

Network throughput has become an important issue for big-data analysis on Warehouse-Scale Computing (WSC) systems. It has been reported that randomly-connected inter-switch networks can enlarge the network throughput. For irregular networks, a multi-path routing method called k-shortest path routing is conventionally utilized. However, it cannot efficiently exploit longer-than-shortest paths that would be detour paths to avoid bottlenecks. In this work, a novel routing method called koptimized path routing to achieve high throughput is proposed for irregular networks. We introduce a heuristic to select detour paths that can avoid bottlenecks in the network to improve the average-case network throughput. Experimental results by network simulation show that the proposed k-optimized path routing can improve the saturation throughput by up to 18.2% compared to the conventional k-shortest path routing. Moreover, it can reduce the computation time required for optimization to 1/2760 at a minimum compared to our previously proposed method.

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Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems

Leal D.P., Sugaya M., Amano H., Ohkawa T.

Proceedings - 2020 International Conference on Field-Programmable Technology, ICFPT 2020 （Proceedings - 2020 International Conference on Field-Programmable Technology, ICFPT 2020）     292 - 293 2020年12月

　概要を見る

Integrating FPGAs to robot systems can be a demanding task. In this paper we present Forest, an open-source tool that automatically generates ROS2 nodes for high-level synthesis-based FPGA modules, greatly facilitating the integration of FPGAs with other robot components. Forest runs on the PYNQ version 2.5 environment with ROS2 Eloquent and can be used with Xilinx SoCs, such as Xilinx Zynq-7000. The ROS2-FPGA node generated by Forest is evaluated in an image processing task, where the FPGA logic performs a linear contrast stretch on images of three different sizes, and an average speed-up of 36.3x and a performance per watt improvement of 432.2x is observed when compared to a ROS2 node running on a modern CPU.

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An implementation methodology for Neural Network on a Low-end FPGA Board

Wei K., Honda K., Amano H.

Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020 （Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020）     228 - 234 2020年11月

　概要を見る

Artificial Intelligence(AI) has achieved unprecedented success in various fields including image/speech recognition which is useful for edge computing. Most of AI systems are implemented on power-hungry devices like GPU, high-end FPGA, or even TPU to process data with high performance. However, these energy budgets are often not affordable to edge computing. Low-end FPGA taking advantage of high energy-efficiency is a desirable platform to meet the requirements of image recognition working on small autonomous vehicles. In this paper, we propose the design methodology and implementation to adapt a neural network system to a low-end FPGA board using HLS description. The whole design consists of algorithm-level downscaling and hardware optimization. The former emphasizes the model downscale by considering accuracy. The latter applies various HLS design techniques to speed-up the application running on the target board. In the case study of tiny YOLO (You Only Look Once) v3, the model running on PYNQ-Z1 presents up to 22× acceleration comparing with the PYNQ ARM CPU. Energy efficiency also achieves 3× better than Xeon E5-2667.

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Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks

Kawano R., Matsutani H., Amano H.

Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020 （Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020）     93 - 99 2020年11月

　概要を見る

As the scale of supercomputers has increased, the end-to-end network latency has become non-negligible on the performance of parallel applications. For this reason, low-latency network topologies achieving the smallest number of hops among switches are drawing attention. The Order/Degree Problem to find the topology with the smallest diameter has revealed that a topology based on graph symmetry and simulated annealing (SA) is optimal for a wide range of system sizes. Focusing on the characteristics of clustering and symmetry of this graph, we extend the method to guarantee the lower limit of the number of cables in each cabinet. The total cable length and cost can be minimized as well as minimizing the deterioration of communication delay. Compared with the conventional network topologies, the proposed network topology can attain higher performance with the smaller total cable length and cost.

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Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System

Ito K., Iizuka K., Hironaka K., Hu Y., Koibuchi M., Amano H.

Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020 （Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020）     211 - 217 2020年11月

　概要を見る

A multi-FPGA System called Flow-in-Cloud (FiC) is currently being developed as an accelerator of Multi-access Edge Computing (MEC), which is one of the core 5G technologies. FiC is a system that consists of multiple mid-range FPGAs tightly connected by high-speed serial links. Since timing-critical jobs are assumed to be executed in MEC, a circuit-switched network with static time-division multiplexing (STDM) switches has been implemented on FiC. In this paper, we investigate the methods to enhance the interconnection performance of FiC. We proposed the link aggregation and the slot distribution for making the use of multiple lanes naturally supported with Aurora-IP and economical FireFly cables. We evaluated combinations of the techniques by using three practical applications on a real FiC prototype with 24 boards. When the number of slots is large and the number of packets is small, the slot distribution is sometimes more effective, while the link aggregation is superior for other most cases. As a result, the communication performance could be improved up to 3.01 times by using four lanes. Furthermore, we found that application designers can use enough resources even using four lanes and the link aggregation is better than the slot distribution.

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Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system

Yamauchi Y., Ahmed A.B., Hironaka K., Iizuka K., Amano H.

Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020 （Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020）     277 - 281 2020年11月

　概要を見る

Although convolutional neural networks (CNNs) have plenty of parallelism, traditional layer-by-layer task division designs for multi-FPGA systems have the following problems: (1) The computational load of each layer is different from each other, so the execution time is dominated with the heaviest one. (2) Each FPGA must be designed independently, it means that we must design, generate and manage various configuration files. To address this problem, we propose a horizontal division method that enables us to use of a single design for each FPGA. All layers are divided horizontal direction of the target CNN, and a set of layers is implemented on an FPGA. It reduces the time of design as well as management costs for the execution. Also, since the weight data can be separated, the usage of local memory can be reduced. The apparent disadvantage of this method is that it requires all-to-all data communication between FPGA boards, and so it is not suitable to traditional multi-FPGA systems with a simple linear network. Here, we tried to apply the method to FiC (Flow-in-Cloud) which has a powerful network to enable efficient broadcasting. A simple CNN LeNet and a matrix multiplication for more practical fully connected layer is implemented on the FiC prototype. As a result of the evaluation, LeNet using 8 FP-GAs achieved 7.5 times faster than that with a single FPGA, and achieved 12.6 times faster than the optimized software of a high-end CPU.

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GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures

Kojima T., Doan N.A.V., Amano H.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems （IEEE Transactions on Very Large Scale Integration (VLSI) Systems）  28 （ 11 ） 2383 - 2396 2020年11月

ISSN  10638210

　概要を見る

Coarse-grained reconfigurable architectures (CGRAs) are expected to be used for embedded systems, Internet of Things (IoT) devices, and edge computing thanks to their high-energy efficiency and programmability. In essence, a CGRA is an array of numerous processing elements. To exploit this abundant computation resource, a compiler for CGRAs has to fulfill more tasks compared that for general-purpose processors. Therefore, many studies have proposed optimization methods, especially for application mapping, because the performance and energy efficiency strongly depend on optimization at compile time. However, many works focus only on performance improvement or resource minimization, although such optimization objectives are not always appropriate when considering various use cases. In this work, we propose GenMap, an application mapping framework using multiobjective optimization based on a genetic algorithm so that users can set optimization criteria as needed. Besides, it provides aggressive power optimization using our dynamic power model and leakage minimization technique. The proposed method is applied to three fabricated CGRA chips for evaluation. Experimental results show that GenMap achieves 15.7% reduction of wire length while keeping processing element utilization when compared with conventional methods. In addition, according to real chip experiments, 12.1%-46.8% of energy consumption is reduced, and up to 2\times speedup is archived for several architectures when compared with other two approaches.

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FPGA Acceleration of ROS2-Based Reinforcement Learning Agents

Leal D.P., Sugaya M., Amano H., Ohkawa T.

Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020 （Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020）     106 - 112 2020年11月

　概要を見る

Reinforcement learning agents have shown very good results in robot control and navigation tasks, allowing robots to learn how to interact with an environment appropriately in a model-free manner. However, real-world robot systems have strict latency, power, and cost constraints, thus requiring special hardware consideration for the demanding computations of neural networks. Furthermore, reinforcement learning networks should be able to interface efficiently with the various other robot components. To address these challenges, we propose a method for applying FPGA hardware accelerators to robotics reinforcement learning agents at the inference stage and seamlessly integrating the FPGA hardware module to the robot system by automatically wrapping it in a Robot Operating System 2 (ROS2) node. The proposed system is evaluated in three OpenAI gym control environments: Cartpole-v1, Acrobot-v1, and Pendulum-v0. In the evaluation, both quantized and non-quantized reinforcement learning neural networks are used, and the proposed FPGA system is observed to provide up to a 3.69x speed up and up to 52.7x better performance per watt when compared to an agent running on a ROS2 node on a modern CPU.

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Exploiting temporal parallelism in particle-based incompressive fluid simulation on FPGA

Orsztynowicz M., Amano H., Kubota K., Miyajima T.

Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020 （Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020）     195 - 201 2020年11月

　概要を見る

—While the semiconductor manufacturing process is shrinking, the Bytes per Flop (B/F) ratio on recent machines is becoming lower. Particle-based computational fluid dynamics (CFD) methods such as Moving Particle Simulation (MPS) require a higher B/F ratio than that of stencil-based CFD methods. Techniques to reduce the B/F ratio by exploiting temporal parallelism is becoming popular in stencil-based CFD methods on CPU and GPU. It is also reported that a technique to combine temporal blocking with stencil buffer is suitable for FPGA and can outperform CPU and GPU. On the other hand, it has been considered that temporal parallelism cannot be exploited in the particle-based CFD methods. This is because the number of particles in each bucket, a three-dimensional grid covering a computational domain, changes every time-step. In this paper, we propose a technique to exploit temporal parallelism in MPS method, a particle-based CFD method for incompressive fluid. The key idea is that the buckets in MPS can be considered as stencils in stencil-based CFD. This is because the maximum number of particles in a bucket can be assumed empirically in the case of an incompressible fluid. To the best of our knowledge, this is the first research which exploits temporal parallelism in the particle-based incompressible fluid method. We implemented the proposed technique with a degree of temporal parallelism of three. We also optimized it on Intel Arria10 FPGA in Intel HLS, and measured the performance and resource consumption. The result shows that the optimized implementation with a degree of temporal parallelism of three achieved 2.1 times speedup compared with implementation without exploiting temporal parallelism on CPU.

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CLAHE implementation on a low-end FPGA board by high-level synthesis

Honda K., Wei K., Arai M., Amano H.

Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020 （Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020）     282 - 285 2020年11月

　概要を見る

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing for improving quality. This paper describes a design of Contrast Limited Adaptive Histogram Equalization (CLAHE), which improves the quality of the dark image for the side mirror camera, on a low-end FPGA board by high-level synthesis. By constituting CLAHE as a data flow design flow, we could achieve performance comparable to the implementation with HDL. The code is parameterized so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga_clahe.

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