Papers - Kuroda, Tadahiro
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低消費電力／高速CMOS回路設計手法
KURODA TADAHIRO
日本工業技術センター 1-23 1996.08
Research paper (scientific journal), Single Work
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マルチメディアLSIと低消費電力設計技術（招待）
桜井貴康, 黒田忠広,
電気学会 第43回半導体専門講座 1-32 1996.07
Research paper (scientific journal), Joint Work
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A 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage (VT) scheme
K. Suzuki, T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai,
in Proc. 4th International Workshop on Advanced LSI’s 150-158 1996.07
Research paper (scientific journal), Joint Work
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Transform Core Professor with Variable-Threshold-Voltage (VT) Scheme
KURODA TADAHIRO
電子情報通信学会 集積回路研究会 信学技法, ED96-49/SDM96-32/ICD96-52 43-48 1996.06
Research paper (scientific journal), Single Work
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Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability
T. Kuroda, T. Fujita, M. Noda, Y. Itabashi, S. Kabumoto, T. S. Wong, D. Beeson, and D. Gray,
IEEE Journal of Solid-State Circuits, vol. 31, no. 6 31 ( 6 ) 819-827 1996.06
Research paper (scientific journal), Joint Work
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A 5Gb/s ATM Switch Element CMOS LSI Supporting 5 Quality-of-Service Classes with 200MHz LVDS Interface
K. Seki, Y. Unekawa, K. Sakue, T. Nakano, S. Yoshida, T. Nagamatsu, H. Nakakita, Y. Kaneko, M. Motoyama, Y. Ohba, K. Ise, M. Ono, K. Fujikawara, Y. Miyazawa, T. Kuroda, Y. Kamatani, T. Sakurai, and A. Kanuma,
Technical Report of IEICE, ED96-51 57-64 1996.06
Research paper (scientific journal), Joint Work
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A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Professor with Variable-Threshold-Voltage(VT) Scheme
藤田哲也, 黒田忠広, 三田真二, 永松 徹, 吉岡晋一, 佐野文彦, 法島政之, 室田雅之, 加古真琴, 衣川正明, 各務正一, 桜井貴康,
電子情報通信学会 集積回路研究会 信学技法, ED96-49/SDM96-32/ICD96-52 43-48 1996.06
Research paper (scientific journal), Joint Work
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低消費電力化設計手法
KURODA TADAHIRO
日本工業技術センター 1-29 1996.05
Research paper (scientific journal), Single Work
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A high-speed low-power 0.3um CMOS gate array with variable threshold voltage (VT) scheme
T. Kuroda, T. Fujita, T. Nagamatu, S. Yoshioka, T. Sei, K. Matsuo, Y. Hamura, T. Mori, M. Murota, M. Kakumu, and T. Sakurai,
in Proc. IEEE Custom Integrated Circuits Conference (CICC’96) 53-56 1996.05
Research paper (scientific journal), Joint Work
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A 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme
T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai,
IEEE International Solid-State Circuits Conference (ISSCC’96), Dig. Tech. Papers 166-167 1996.02
Research paper (scientific journal), Joint Work
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A 5Gb/s 8 x 8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200MHz LVDS interface
Y.Unekawa, K.Fukuda, K.Sakaue, T.Nakao, S.Yoshioka, T.Nagamatsu, H.Nakakita, Y.Kaneko, M.Motoyama, Y.Ohba, K.Ise, M.Ono, K.Fujiwara, Y.Miyazawa, T.Kuroda, Y.Kamitani, T.Sakurai, and A.Kanuma,
IEEE International Solid-State Circuits Conference (ISSCC’96), Dig. Tech. Papers 118-119 1996.02
Research paper (scientific journal), Joint Work
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低消費電力設計手法
KURODA TADAHIRO
日本工業技術センター 35-53 1995.11
Research paper (scientific journal), Single Work
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Low-power circuit design for multimedia VLSI (invited)
T. Sakurai and T. Kuroda,
in Proc. International Conference on VLSI & CAD (ICVC’95) 1-6 1995.10
Research paper (scientific journal), Joint Work
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Tutorial on Low-Power LSI Design (invited)
T. Sakurai and T. Kuroda,
The 8th Karuizawa Workshop on Circuits and Systems 209-214 1995.04
Research paper (scientific journal), Joint Work
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Overview of low-power ULSI circuit techniques
T. Kuroda and T. Sakurai,
IEICE Transactions. on Electronics, vol. E78-C, no. 4, E78-C ( 4 ) 334-344 1995.04
Research paper (scientific journal), Joint Work
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Low-Power Circuit Design using Pass-Transistor Logic and Substrate-bias Control (invited)
T. Kuroda and T. Sakurai,
The 8th Karuizawa Workshop on Circuits and Systems 215-220 1995.04
Research paper (scientific journal), Joint Work
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1.65Bb/s 60mW 4:1 multiplexer and 1.8Gb/s 80mW 1:4 demultiplexer ICs using 2V 3-level series gating ECL circuits
T. Kuroda, T. Fujita, Y. Itabashi, S. Kabumoto, M. Noda, and A. Kanuma,
IEEE International Solid-State Circuits Conference (ISSCC’95), Dig. Tech. Papers 36-37 1995.02
Research paper (scientific journal), Joint Work
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50% Active Power Saving without Speed Degradation Using Standby Power Reduction (SPR) Circuit
K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai,
IEEE International Solid-State Circuits Conference (ISSCC’95), Dig. Tech. Papers 318-319 1995.02
Research paper (scientific journal), Joint Work
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ランダムロジック－パストランジスタロジック－
KURODA TADAHIRO
日本工業技術センター 25-38 1994.11
Research paper (scientific journal), Single Work
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ローパワーLSI設計技術の現状と動向
KURODA TADAHIRO
日本工業技術センター 1-24 1994.11
Research paper (scientific journal), Single Work