論文 - 山中　直明

2.2 Gbit/s Si bipolar 8 × 8 crosspoint switching LSI

Yamanaka Naoaki, Kikuchi Shiro, Suzuki Masao, Hirata Michihiro

Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi) 74 （ 2 ） 100 - 110 1991年02月

ISSN  8756-663X

　概要を見る

<p>A high-speed 8 × 8 space-division switching LSI has been developed for video and HDTV switching and broadcasting applications in the future B-ISDN. The LSI employs a new circuit design and super self-aligned process technology (SST-1A), and is switched successfully with a bit error rate of less than 10^-9 at 2.5 Gbit/s using a 2⁹-1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 70 ps at 2.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell. The LSI has an ECL-compatible interface, -4.0 V and -2.0 V power supply voltages, and power dissipation of less than 997 mW. High-speed address control memories (ACMs) are integrated monolithically into the LSI, which can operate both synchronously and asynchronously.</p>

Experimental ATM transport system and virtual path management techniques

Sato Youichi, Yamanaka Naoaki, Sato Ken ichi, Tokura Nobuyuki

  2110 - 2116 1991年

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<p>The authors present the main points of a recently developed experimental ATM (asynchronous transfer mode) transport system and the key virtual path (VP) management techniques. The ATM network configuration and the developed ATM cross-connect and add/drop multiplexing (ADM) systems are outlined. They describe the design considerations of the VP management techniques, which include VP bandwidth specifying parameters. The newly developed usage parameter control techniques are then presented. An analytical method for evaluating cell multiplexing delay and cell loss characteristics for multimedia signal sources is developed. Next, by utilizing this method, a link capacity-design algorithm for accommodating VPs is proposed. Finally, the performance and application areas of the proposed algorithm are evaluated.</p>

A 2 Gb/s expandable space-division switching LSI and network architecture for gigabit-rate broad-band circuit switching

Yamanaka Naoaki, Kikuchi Shiro, Suzuki Masao, Yoshioka Yukiharu

IEEE Journal on Selected Areas in Communications 8 （ 8 ） 1543 - 1550 1990年10月

ISSN  0733-8716

　概要を見る

<p>An expandable space-division (SD) switch architecture and a bipolar circuit design for gigabit-per-second crosspoint-switch LSIs are described. An expandable 2-Gb/s 16 × 16 crosspoint switch LSI which employs a novel switch structure, a novel circuit design, and a super self-aligned process (SST-1A) is developed. A switching module and partial 1:n nonblock, full 1:1 nonblock switching network architecture are also presented. Using the LSI and the switching network architecture, an experimental 620-Mb/s network system is demonstrated.</p>

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Circuit design for 2-Gbit/s Si bipolar crosspoint switch LSI's

Suzuki Masao, Yamanaka Naoaki, Hirata Michihiro, Kikuchi Shiro

IEEE Journal of Solid-State Circuits 25 （ 1 ） 155 - 159 1990年02月

ISSN  0018-9200

　概要を見る

<p>An 8 × 8 and an expandable 16 × 16 crosspoint switch LSI utilizing a new circuit design and super self-aligned process technology (SST-1A) are discussed. The LSIs successfully switched with a bit error rate of less than 10^-9 at 2.5 Gb/s using a 2⁹ - 1 pseudorandom NRZ sequence. Pulse jitter was limited to less than 80 ps at 1.2 Gb/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSIs have an ECL-compatible interface, -4-V and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8 × 8 LSI and 2.8 W for the expandable 16 × 16 LSI.</p>

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Newly structured expandable 52-Mbit/s, 48-channel time-division switching LSI with 2.4 Gbit/s throughput

Yamanaka N., Kikuchi S., Miyanaga H.

Electronics Letters 26 （ 8 ） 524 - 526 1990年01月

ISSN  0013-5194

　概要を見る

<p>An expandable Si bipolar 2.4 Gbit/s throughput, 52 Mbit/s 48-channel time-division switching LSI system is described. A high-throughput of 2.4 Gbit/s and a power-dissipation of 5.3 W are achieved by adopting a low-voltage swing four-serial-gated differential bipolar circuit design and super self-aligned process (SST-1A) logic-in-memory LSI technology. This LSI is applicable to the digital video time-division switching and digital crossconnect systems ot future B-ISDN.</p>

Multichip 1.8-Gb/s high-speed space-division switching module using copper-polyimide multilayer substrate

Yamanaka Naoaki, Kikuchi Shiro, Kon Taichi, Ohsaki Takaaki

  562 - 570 1990年

　概要を見る

<p>A high-speed multichip 32 × 32 space-division switching module for high-definition TV broadcasting and switching systems is described. This module employs a novel Si-bipolar SST (super self-aligned process technology) switching LSI and a multilayer substrate with a polyimide dielectric and a fine pattern of copper conductors. The substrate contains matrix-shaped thin-film resistors for terminated transmission and has a spiral via hole structure to increase fabrication reliability. The module has 50-Ω characteristic impedance transmission lines that have a small deviation of less than 2.5%. The multichip module can handle a signal speed of 1.8 Gb/s using 1:1 and 1:n connections. Performance results confirm that this module will be suitable for future B-ISDN (broadband integrated services digital network) communication systems.</p>

1.5 Gbit/s GaAs four-channel selector LSI with monolithically integrated newly structured GaAs ohmic contact MSM photodetector and laser driver

Yamanaka Naoaki, Takada Tohru

IEEE Photonics Technology Letters 1 （ 10 ） 310 - 312 1989年10月

ISSN  1041-1135

　概要を見る

<p>A monolithic integrated 1.5 Gb/s high-speed four-channel optoelectronic integrated circuit (OEIC) selector GaAs LSI circuit is discussed. This LSI circuit incorporates photodetectors, preamplifiers, a selector, a decision circuit, and a high-speed laser driver. To achieve high efficiency, a AuGe/Ni-GaAs structured ohmic contact metal-semiconductor-metal (OC-MSM) is used for the interdigitated structural photodetector. With this OC-MSM structure, photocurrent is approximately twice as effective as with the conventional Schottky contact MSM structure. The new LSI has a maximum operating speed of 1.5 Gb/s and exhibits low power dissipation of 927 mW.</p>

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1 Gbit/s, 32 × 32 high-speed space-division switching module for broadband ISDN using SST LSIs

Yamanaka N., Kikuchi S., Yoshioka Y., Suzuki M.

Electronics Letters 25 （ 13 ） 831 - 833 1989年01月

ISSN  0013-5194

　概要を見る

<p>A high-speed 32 × 32 space-division switching module for high-definition TV broadcasting and switching systems is described. It employs a newly developed Si-bipolar SST 8 × 8 switch LSI, high-speed peripheral ICs and a high-speed impedance-controlled board. The module is capable of a 1.0 Gbit/s signal speed using 1:1 and 1:n connections.</p>

2 Gbit/s, 16 × 16 expandable high-speed space-division-switch LSI using SST

Yamanaka N., Suzuki M., Kikuchi S.

Electronics Letters 25 （ 22 ） 1470 - 1471 1989年01月

ISSN  0013-5194

　概要を見る

<p>A Si bipolar 2 Gbit/s 16 × 16 high-speed space-division-switch LSI is described. High-speed operation of 2 Gbit/s and low-power dissipation of 2.8 W are achieved by adopting a new expandable structure, a very low voltage swing-differential bipolar circuit design and a super self-aligned process technology SST-1A. This LSI is applicable to future B-ISDN HDTV switching systems.</p>

Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs

Suzuki Masao, Yamanaka Naoaki, Hirata Michihiro, Kikuchi Shiro

  65 - 66 1989年

　概要を見る

<p>An Si bipolar circuit technology for gigabit-per-second crosspoint switch LSIs is described. A novel circuit design and a super-self-aligned process technology were adopted, and 8 × 8 and 16 × 16 (+16) crosspoint switch LSIs were fabricated. The LSIs successfully switched with a bit error rate of less than 10^-9 at 2.5 Gb/s using a 2⁹-1 pseudorandom NRZ sequence. Pulse jitters are made less than 76 ps at 2 Gb/s by utilizing a small internal voltage swing (225 mV) with a differential CML. The LSIs have full emitter-coupled logic (ECL)-compatible interfaces, -4/-2-V power supply voltages, and a power consumption of less than 0.9 W for an 8 × 8 LSI, and 2.8 W for a 16 × 16 (+16) LSI. These results confirm that the proposed technologies are applicable to future B-ISDN (broadband integrated services digital network) communication systems.</p>

Novel structure for high-speed multihighway serial-to-parallel converter

Yamanaka Naoaki, Hirata Michihiro, Suzuki Masao, Yano Takao

IEEE Transactions on Communications 36 （ 11 ） 1221 - 1225 1988年11月

ISSN  0096-1965

　概要を見る

<p>The authors propose a novel structure for a high-speed multihighway serial-to-parallel converter for future high-speed digital switching systems. The proposed structure consists of a two-dimensional shift register array that can shift both horizontally and vertically. The shift direction is changed at the frame periods. The calculated results confirmed the superiority of the proposed structures over conventional ones, namely, faster operating speed and fewer gates.</p>

HIGH-SPEED TIME DIVISION SWITCH FOR 32-MBIT/S BEARER RATE SIGNALS.

Yamanaka Naoaki, Miyanaga Hiroshi, Yamamoto Yousuke

IEEE Journal on Selected Areas in Communications SAC-5 （ 8 ） 1249 - 1255 1987年10月

ISSN  0733-8716

　概要を見る

<p>A high-speed time-division switch used in a 32-Mb/s bearer-signal communications system is described. System performance is realized by using three technologies. The first is a switch structure referred to as a 2-RAM 2-bank structure which ensures high-speed performance by increasing switching throughput four times over that of the basic structure. The second is the inclusion in the switch of two types of peripheral logic developed using Si-bipolar super-self-aligned process technology. The third is high-speed synchronous transmission of data. A large-channel-capacity time-division switching network is also discussed. In conjunction with the network, these technologies make it possible to realize the ISDN time-division switches necessary for such services as TV and high-definition TV communications.</p>

HIGH-SPEED TIME-DIVISION SWITCH FOR BROADBAND ISDN.

Yamanaka Naoaki, Kikuchi Shiro

  2010 - 2014 1987年

　概要を見る

<p>A broadband ISDN architecture is proposed, and its requirements are discussed. The structure and traffic characteristics of a broadband switching system using multirate switching technology are described. A high-speed time-division switch for broadband circuit switching is presented. It uses a high-speed time switch, a serial-to-parallel converter, and peripheral ICs, all of which operate at over 512 Mb/s. Experimental results are presented.</p>

NEWLY STRUCTURED 512 Mbit/s HIGH-SPEED TIME-DIVISION SWITCH.

Yamanaka N., Miyanaga H., Yamamoto Y.

Electronics Letters 22 （ 21 ） 1094 - 1096 1986年10月

ISSN  0013-5194

　概要を見る

<p>The letter describes the recently developed fastest time-division switch experimental system operating at 512 Mbit/s. The system adopts a new switch structure which can increase switching throughput by four times over the basic structure to ensure high-speed performance. Also employed in the switch are two types of peripheral logic developed using Si bipolar super-self-aligned process technology. This switch makes possible the ISDN time-division switches necessary for TV and high-definition TV communication.</p>

LOW-POWER Si-BIPOLAR MULTI-GBIT/S LOGICS HAVING THE SAME FUNCTION AS ECL100K FAMILY.

Yamanaka Naoaki, Miyanaga Hiroshi, Yamamoto Yousuke

Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E E69 （ 10 ） 1068 - 1071 1986年10月

ISSN  0387-236X

　概要を見る

<p>This paper presents the development of high-speed logic ICs having the same function as the ECL100K family for high-speed digital system applications such as for time division switching systems. A Super-Self-Aligned process Technology (SST) and a low-voltage swing differential circuit technique are used. The ICs operate up to about 2 Gb/s under a chip power dissipation of 170 mw-570 mw.</p>

A Novel Concept for High-Speed Time Switch Approaching Memory Read Cycle Limit

Yamamoto Yousuke, Miyanaga Hiroshi, Kobayashi Yoshiji, Terada Yasukazu, Yamanaka Naoaki

IEEE Transactions on Communications 34 （ 9 ） 953 - 955 1986年

ISSN  0090-6778

　概要を見る

<p>A novel concept and structure for a high-speed time division switch operating in the gigabit/second range are presented. The basic concept is to use the high-speed memory in the time switch effectively by means of a slow writing/fast reading method. N numbers of speech data are written in parallel during N clock times and read serially during one clock time for one switched datum. By using the concept and high-speed memories that we have, a data switching system which approaches the memory and read cycle limit can be realized with a proper time margin. Copyright © 1986 by The Institute of Electrical and Electronics Engineers, Inc.</p>

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BIPOLAR GBIT/S 8 multiplied by 8 BIT S/P, P/S CONVERTER LSI.

Hirata Michihiro, Suzuki Masao, Yamanaka Naoaki, Yamamoto Yousuke

  271 - 274 1986年

　概要を見る

<p>A Si bipolar very high-speed 8-channel multiplied by 8-bit Serial/Parallel and Parallel/Serial conversion LSI (SPPS-LSI), having 1. 5 Gb/s throughput is developed for high-speed digital communication systems. To achieve high performance, a novel data conversion method is adopted. By applying a sophisticated circuit design and SST-1A process technology, a high-speed and low-power LSI is achieved with small chip size.</p>

HIGH-SPEED TIME DIVISION SWITCH OPERATING AT 256Mb/s.

Yamanaka Naoaki, Kawakami Masaharu, Terada Yasukazu

Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E E68 （ 9 ） 570 - 571 1985年09月

ISSN  0387-236X

　概要を見る

<p>This letter presents the construction of a high-speed time division switching system for the video network, using Si-bipolar super-high-speed RAMs and ECL 100K families. A switching speed of 256 Mb/s and a switching throughput of 2 Gb/s (signal speed 32 Mb/s multiplied by 64 channels) are obtained.</p>

FINE STRUCTURES IN THE BROADENED LINE OF DISTRIBUTED FEEDBACK LASERS UNDER HIGH-SPEED DIRECT MODULATION.

Yoshikuni Yuzo, Matsuoka Takashi, Motosugi George, Yamanaka Naoki

Applied Physics Letters 45 （ 8 ） 820 - 822 1984年01月

ISSN  0003-6951

　概要を見る

<p>Precise observation of the single longitudinal mode spectrum for distributed feedback lasers revealed fine structures when the spectrum was broadened by high-speed modulation. A dynamic simulation can explain reasonably the above behavior if the model takes into account the carrier density modulation enhanced by the relaxation oscillation. In this work, experimental results where both modulation depth and speed were varied are described along with a calculated result.</p>

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