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Performance limitation of the leaky bucket algorithm for ATM networks

Yamanaka Naoaki, Sato Youichi, Sato Ken Ichi

IEEE Transactions on Communications 43 （ 8 ） 2298 - 2300 1995年08月

ISSN 0090-6778

The performance limitation of the 'Leaky Bucket algorithm' is analyzed for usage parameter control and traffic management in Asynchronous Transfer Mode (ATM) networks. Simulation results show that the conventional statistical bandwidth allocation method, which uses 'the worst pattern derived from the cell interarrival time moments' permitted by the Leaky Bucket algorithm, can not guarantee the QOS. As a result, this paper proves that the VC/VP bandwidth allocation method based on the Leaky Bucket algorithm is unsatisfactory.

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Optimum logical-design scheme for flexible multi-QoS ATM networks guaranteeing reliability

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E78-B （ 7 ） 1016 - 1024 1995年07月

ISSN 0916-8516

An optimum design scheme for logical network topologies on a Flexible Multi-QoS Logical ATM Network, named Full-Net, is proposed. Full-Net offers high-quality Virtual-Path (VP) networks and controls end-to-end QoS only at the VP-network's access points. To develop the optimum network topology for multimedia traffic in a single ATM network, a logically configured Virtual Channel Handler (VCH) interconnection network is associated with each QoS class. Many logical networks can be mapped at the same time on the same network, because mapping is independent of the network's physical implementation. To achieve an optimum design scheme for logical networks, the number of disjoint routes is introduced as the parameter used to optimize logical network topology. The number of disjoint routes is chosen so as to maximize total network efficiency. The optimum number of disjoint routes depends on the required QoS, VC-traffic characteristics, and traffic demand. By choosing the relevant cost characteristics, the network operator can easily maximize network efficiency and provide customers with the QoS they request at minimum cost. The proposed optimum multi-QoS network design scheme on a Full-Net architecture is an efficient solution to implementing multi-QoS control in an ATM network.

Recursive matrix-calculation method for disjoint path search with hop link number constraints

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E78-B （ 5 ） 769 - 774 1995年05月

ISSN 0916-8516

A new approximation calculation method, named the Recursive Matrix-calculation (RM) method, is proposed. It uses matrix calculation to determine the number of link disjoint paths under a hop link number constraint, i.e. hop limit. The RM method does not overestimate the number of link disjoint paths. When networks are designed by this method, network reliability is perfectly guaranteed. Moreover, the RM method is based on matrix calculation, so CPU time can be reduced by using super-computers equipped with vector processors. Simulation results confirm that the RM method yields rapid approximations that are conservative. Thus the proposed method is very useful for designing reliable multimedia networks.

Jitter tolerant usage parameter control method for ATM-based B-ISDN

Yamanaka Naoaki, Takenaka Toyofumi, Sato Youichi, Sato Ken ichi

IEICE Transactions on Communications E78-B （ 4 ） 485 - 493 1995年04月

ISSN 0916-8516

A uniquely-structured Usage Parameter Control (UPC) method named Virtual-shaping is proposed which considers cell arrival time jitter between user and UPC point. The method uses a modified Dangerous Bridge UPC circuit (Sliding window type) and virtually (logically) shapes cell traffic using cell arrival time compensation to offset cell delay variation (CDV). In addition, the proposed method is based on a cell-buffer-less structure and can be realized with reasonable hardware. The method yields precise and accurate monitoring. Computer simulations show that the method offers higher network utilization than the conventional Leaky Bucket based UPC method. The proposed method will make it possible to create more effective B-ISDNs, and more cost-effective broadband VBR services.

320 Gb/s high-speed ATM switching system hardware technologies based on copper-polyimide MCM

Yamanaka Naoaki, Endo Ken ichi, Genda Kouichi, Fukuda Hideki, Kishimoto Tohru, Sasaki Shin ichi

IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging 18 （ 1 ） 83 - 91 1995年02月

ISSN 1070-9894

This paper describes a 320 Gb/s high-speed multichip ATM switching system for broadband ISDN. This system employs a copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 15-layer ceramic power supply layers. The system uses 64 MCM's that are interconnected by 98-highway flexible printed circuit connector. Si-bipolar VLSI's are mounted on MCM's using the 150 μm very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is adopted. The system switches ATM cells up to 320 Gb/s throughput, which is applicable for future B-ISDN.

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TORUS-switch

Genda K., Yamanaka N.

Electronics Letters 31 （ 11 ） 906 - 908 1995年01月

ISSN 0013-5194

A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient.

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Optimum logical ATM network design method guaranteeing multimedia QoS requirements

Oki Eiji, Yamanaka Naoaki

263 - 269 1995年

This paper proposes a new topological design method, named BXCQ, which optimizes logical network configuration while guaranteeing QoS requirements for each service class in an ATM network. The BXCQ method determines the optimum logical network topology associated with each service class so as to minimize network cost. In our previously proposed Full-Net architecture[1], these different logical topologies can be suitably mapped at the same time on the same ATM physical network by using VCHs logical interconnection networks. According to the BXCQ method, the results quantitatively clarify the relations between multimedia traffic characteristics and desirable logical network configurations in the Full-Net. Evaluation results suggest that a service class that is bursty, delay tolerant and cell loss sensitive with small demand should be supported by a loop-like topology. Furthermore, the results also show that suitably changing logical configurations in accordance with traffic demand fluctuations leads to a dramatic reduction of 8.8% in network cost. This study will be useful for designing flexible and cost-effective multimedia networks that can also adapt to not-yet-known services.

Sub-T bit/s large-capacity ATM MCM switching system design and modules with new low-power Gbit/s I/O circuits

Kawamura Tomoaki, Yamanaka Naoaki, Matsumura Tsuneo, Ichino Haruhiko, Yamaguchi Chikara, Kobayashi Yoshiji

44 - 47 1995年

This paper presents a low-power large-capacity ATM switching system design and modules (LSI and MCM). The design uses MCM technology with a copper-polyimide substrate, 150-μm pitch outer lead TAB and 98-highway flexible printed circuit cables for high-density packaging and high-speed operation. Using these technologies, a 160 Gbit/s ATM switching system with a power dissipation of about 1.3 kW can be achieved for future Broadband ISDN systems. This power is 65% of that of the reported system which uses ECL I/Os, and can be cooled by forced air with conventional fin-structures.

TORUS-switch

Genda Kouichi, Yamanaka Naoaki

1738 - 1745 1995年

An over 1 Tb/s scalable ATM switching system architecture is proposed suitable for the mature B-ISDN environment. Two kinds of switch modules are combined, the small-scale switch with VC and VP-level management named AHM having 10 to 20 Gb/s throughput, and the high-speed and simple routing switch named AMC offering simple ATM layer management for AHMs-interconnection. AMC resource management employs the Grouped VP resource management scheme only at AHM. The proposed system architecture gives high statistical multiplexing gain from small-size switches to over 1 Tb/s switches and easy management; switching capacity can be efficiently expanded. As the switch architecture of the AMC, a high-speed and scalable ATM switch architecture, named TORUS-switch, is proposed. The switch is an internal speed-up crossbar-type switch with cylindrical configuration. The self-bit-synchronization technique is adopted to achieve high-speed cell transmission without requiring high-density implementation technology. Also, distributed contention-control based on the fixed output-precedence scheme is newly adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultra-high-speed crosspoint LSI using the advanced Si-bipolar process to confirm its feasibility. Measured results confirm that the TORUS-switch can be used to realize a expandable tera-bit-rate ATM switch that is also efficient.

New traffic shaping mechanism for ATM networks

Pitcho Francis, Yamanaka Naoaki

IEICE Transactions on Communications E77-B （ 12 ） 1628 - 1631 1994年12月

ISSN 0916-8516

High-speed-retry banyan switch architecture for giga-bit-rate BISDN networks

Genda Kouichi, Yamanaka Naoaki, Arai Yoshimitsu, Kataoka Hideki

International Journal of Communication Systems 7 （ 3 ） 223 - 229 1994年07月

ISSN 1074-5351

This paper proposes a high-speed ATM switch architecture for handling cell rates of several Gb/s in a broadband communication switching system or cross-connect system. The proposed switch architecture, named the high-speed-retry banyan switch, employs a bufferless banyan network between input and output buffers: a cell is repeatedly transmitted from an input buffer until it can be successfully transmitted to the desired output buffer. A simple cell-retransmission algorithm, is employed as is a ring-arbitration algorithm for cell conflict. They are suitable for FIFO type buffers and bufferless high-speed devices. Good traffic characteristics which are independent of switch size are achieved for an internal speed ratio of only four times the input line speed. A prototype system with the internal speed of 1·2 Gb/s is constructed in order to confirm the basic operation of the high-speed-retry banyan switch. The prototype system, even in its present state, could be used to realize a giga-bit-rate BISDN switching system.

320 Gb/s high-speed ATM switching system hardware technologies based on copper-polyimide MCM

Yamanaka Naoaki, Endo Ken ichi, Genda Kouichi, Fukuda Hideki, Kishimoto Tohru, Sasaki Shin ichi

776 - 785 1994年

This paper describes a 320 Gb/s high-speed multi-chip ATM switching system for broadband ISDN. This system employs a Copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 15-layer ceramic power supply layers. The system uses 64 MCMs that are interconnected by 98-highway flexible printed circuit connector. Si-bipolar VLSIs are mounted on MCM using the 150 μm very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is adopted. The system switches ATM cells up to 320 Gb/s throughput and it is applicable for future B-ISDN.

High-speed ATM switching architecture using small shared switch blocks

Endo Ken ichi, Yamanaka Naoaki

IEICE Transactions on Communications E76-B （ 7 ） 736 - 740 1993年07月

ISSN 0916-8516

This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The N × N matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N^-2 to (N/D)². Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10^-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.

Wavelength path network management scheme for multimedia photonic network

Yamanaka Naoaki, Chaki Shin ichiro

IEICE Transactions on Communications E76-B （ 7 ） 731 - 735 1993年07月

ISSN 0916-8516

A wavelength path (WP) network management scheme is proposed for a photonic network. Multimedia data streams are integrated into a single-mode fiber using wave-length division WP multiplexing, both analog/digital and STM/ATM communications are handled. The WP management scheme using WP blocks (WPBs) with guard bands is described. An initially assigned WP does not use the guard band and most bandwidth changes made to accommodate WP changes occur within the original WPB using the guard band. An effective WP assignment method based on a recursive packing scheme is also proposed. The proposed WP packing scheme with guard band realizes a maximum network efficiency of 98%, and the probability of WP reassignment is under 10%. The techniques introduced in this paper permit the realization of flexible and effective multimedia services with a multimedia photonic network.

High-speed ATM switch that uses a simple retry algorithm and small input buffers

Genda Kouichi, Yamanaka Naoaki, Doi Yukihiro

IEICE Transactions on Communications E76-B （ 7 ） 726 - 730 1993年07月

ISSN 0916-8516

This letter describes the High-speed Statistical Retry switch (HSR switch) for high-speed ATM switching systems. The HSR switch uses a new matrix-shaped switching structure with buffers at input and output ports, and a simple retry algorithm. The input buffers are very small, and no complicated arbitration function is employed. A cell is repeatedly transmitted from each input buffer at 'm' times the input line speed until the input buffer receives an acknowledge signal from the intended output buffer. A maximum of one cell can be transmitted from each input buffer during the cell transmission time. The internal ratio (m) is decided according to the probability of cell conflict in the output line. Simulation results show that just a 10-cell buffer at each input port and a 50-cell buffer at each output port are required when m=4 to achieve a cell loss probability of better than 10^-8, irrespective of the switch size. At each crosspoint, cells on the horizontal input line take precedence over those on the vertical input line. Only a very simple retry algorithm is employed, no complex arbitration is needed, and the arbitration circuit at the crosspoint can be reduced by about 90% in size. The proposed ATM switch architecture is applicable to high-speed (Gbit/s) ATM switches for B-ISDN because of its simplicity.

Usage parameter control and bandwidth allocation methods considering cell delay variation in ATM networks

Yamanaka Naoaki, Sato Youichi, Sato Ken ichi

IEICE Transactions on Communications E76-B （ 3 ） 270 - 279 1993年03月

ISSN 0916-8516

This paper proposes an ATM traffic management method that utilizes a deterministic source traffic descriptor, a deterministic Usage Parameter Control (UPC) algorithm and a conservative statistical bandwidth allocation method all of which were developed considering the Cell Delay Variation (CDV) typically experienced in ATM networks. For the source traffic descriptor, sliding time interval-type descriptors are proposed. A newly-structured UPC method which combines a sliding window-type circuit and a 2-phase credit window type circuit is proposed. The method is precise and accurate and requires only a small amount of hardware. The proposed parameter conversion method considers the CDV generated between User and UPC point. A bandwidth allocation method based on the worst clumping pattern and UPC output pattern is proposed. The network efficiency degradation caused by CDV is calculated. This traffic management method not only guarantees the QOS of all connections but also allows for large statistical multiplexing gains. The proposed method will, therefore, make it possible to create a more effective B-ISDN, one that can offer cost-effective broadband VBR services.

High-speed ATM switch with input and cross-point buffers

Doi Yukihiro, Yamanaka Naoaki

IEICE Transactions on Communications E76-B （ 3 ） 310 - 314 1993年03月

ISSN 0916-8516

This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1 Gbit/s.

Network resource management techniques for VP-based B-ISDN

Sato Ken ichi, Sato Youichi, Yamanaka Naoaki, Hayashi Kazuhiro

NTT R and D 42 （ 3 ） 343 - 356 1993年

ISSN 0915-2326

This paper describes network resource management techniques which are the key to exploiting the benefits of VP-based ATM networks. In ATM networks, the Virtual Path (VP) concept has been established which enables separation of the logical path capability from the physical interface structure. This is an inherent benefit of VPs and will greatly enhance network flexibility and performance. However, the benefits of ATM can only be utilized through a new network resource management technique and a Usage Parameter Control technique, which are described in this paper.

A 1.8-Gb/s GaAs optoelectronic universal switch LSI with monolithically integrated photodetector and laser driver

Yamanaka Naoki, Kikuchi Shiro, Takada Tohru

Journal of Lightwave Technology 10 （ 8 ） 1162 - 1166 1992年08月

ISSN 0733-8724

A high-speed monolithic optical interface switch LSI is developed using a GaAs MSM photodetector and large-scale integrated electric circuits. This LSI operates universally as a 1.8-Gb/s optical-input/optical-output four-channel time-division switch, a 1.8-Gb/s optical-input/electrical-output 1:4 demultiplexer, a 2.0-Gb/s electrical-output 4:1 multiplexer, and a 2.8-Gb/s electrical-input/electrical-output 4 × 4 space-division switch. It uses a new multistage 2 × 2 switch block with small hardware and high-speed operation. It can be expanded to a 16 × 16 optical-input/optical-output time-division switch operating at up to 1.8 Gb/s for broadband-ISDN.

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A gigabit-rate five-highway GaAs OE-LSI chipset for high-speed optical interconnections between modules or VLSI's

Yamanaka Naoaki, Sasaki Masaharu, Kikuchi Shiro, Takada Thoru, Idda Masao

IEEE Journal on Selected Areas in Communications 9 （ 5 ） 689 - 697 1991年06月

ISSN 0733-8716

A gigabit-rate five highway interface GaAs optoelectronic LSI chipset has been fabricated for the 0.85 μm wavelength range optical interconnections between modules or VLSIs. The optical sender consists of a high-speed laser driver array LSI having 2 Gb/s maximum operation speed and a tiny laser array. The optical receiver in a GaAs high-speed optical receiver array LSI with a monolithically integrated metal-semiconductor-metal (MSM) photodetector, a high-speed preamplifier, and a decision circuit that has a maximum operation speed of 1.8 Gb/s. The receiver LSI is provided with a new bit-synchronizing circuit and an automatic threshold determination circuit.

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