研究者詳細 - 山中　直明

論文 - 山中　直明

分割表示 279 件中 201 - 220 件目／全件表示 >>

Advanced ATM switching system hardware technology using MCM-D, stacking RAM micro-processor module

Yamanaka Naoaki, Kawamura Tomoaki, Kaizu Katsumi, Harada Akio

884 - 888 1998年

This paper describes newly developed advanced ATM switching system hardware structures based on MCM-D micro-processor modules. The Si-Substrate MCM-D technology which integrates micro-processor, interface control and peripheral control custom VLSIs, high-speed S-RAMs, and FPGAs (Field Programmable Gate Arrays) is employed. An MCM-D micro-processor module is realized by combining a Motorola 68030, high-performance ASICs, and high-speed S-RAM caches. This is made possible by high density packaging and high-speed 4M-byte with parity cache using 25 ns access to 4-Mbit of S-RAM memory. The MCM employs 12 S-RAMs, possible with the stacked RAM technique, to reduce the module size by 7/8 compared to conventional surface mounting modules. This micro-processor module technology and MCM technology will advance the development of practical B-ISDN ATM switching systems.

Development of plastic chip scale package for ATM switching systems

Harada Akio, Kaizu Katsumi, Yamanaka Naoaki, Kawamura Tomoaki

30 - 35 1998年

A plastic chip-scale package (CSP) smaller than conventional ones has been developed and applied to ATM switching systems. It uses a low-cost glass-epoxy substrate. Because glass epoxy is widely used in the printed circuit boards (PCBs) of ATM switching systems, its use in the CSPs mounted on a PCB reduces the difference in thermal expansion between the PCB and CSPs, thus lengthening CSP life. The power plane, ground plane, and thermal vias of the CSP are designed to offset the increased thermal resistance due to the CSP's smaller size. Simulation showed a thermal resistance for this CSP with copper layers and thermal vias of as much as 22% less than that of one with no copper layers or thermal vias. A six-layer test board mounting four CSPs was used to simulate a sub-board for ATM switching systems. The thermal resistance of the two CSPs located downstream was about 10% higher than that of the two located upstream. Two CSPs were developed for two types of application-specific ICs: a bus interface controller (BIC) and a peripheral interface circuit (PIC). Both CSPs were 18 mm square with a 0.8-mm outer solder-ball pitch and 256 outer balls. These CSPs occupied areas about 87% and 68% smaller than those of a conventional pin grid array (PGA) and quad flat package (QFP), respectively. The junction temperature of both CSPs satisfied the thermal condition. These high-performance CSPs are thus attractive for use in ATM switching systems.

A high-speed tandem-crosspoint ATM switch architecture with input and output buffers

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E81-B （ 2 ） 215 - 222 1998年

ISSN 0916-8516

This paper proposes a high-speed input and output buffering ATM switch, named Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at every crosspoint. Even if a cell can not be transmitted to an output port on the first plane, it has a chance to be transmitted on the next plane. Cell transmission is executed on each switch plane in a pipeline manner. Therefore, more than one cell can be transmitted to the same output port within one cell time slot, although the internal line speed of each switch is equal to the input /output line speed. The TDXP switch architecture has several advantages in implementation. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require to rebuild the cell sequences at output buffers using time stamps, as is required by a parallel switch. These merits make implementing the high-speed ATM switch easy. Numerical results show that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput both for unicasting and multicasting traffic. This switch architecture is expected to enable the development of high-speed ATM switching systems that can realize over 1 Tb/s throughput in a cost-effective way.

A high-speed CAC scheme in ATM networks by using virtual requests for connection

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E81-B （ 10 ） 1927 - 1930 1998年

ISSN 0916-8516

This paper proposes a high-speed connection admission control scheme, named PERB CAC (CAC based on Prior Estimation for Residual Bandwidth). This scheme estimates the residual bandwidth in advance by generating a series of virtual requests for connection. When an actual connection request occurs, PERB CAC can instantaneously judge if the required bandwidth is larger than the estimated residual bandwidth, so the connection set-up time can be greatly reduced. Therefore, PERB CAC can realize high-speed connection set-up.

A new multiple QoS control scheme with equivalent-window CAC in ATM networks

Oki Eiji, Yamanaka Naoaki, Shiomoto Kohei, Moitra Soumyo D.

IEICE Transactions on Communications E81-B （ 7 ） 1462 - 1473 1998年

ISSN 0916-8516

This paper proposes a multiple QoS control scheme that combines the head-of-line priority (HOLP) discipline with equivalent-window connection admission control (CAC). The proposed scheme can support the different cell loss ratios of both delay-sensitive traffic in high-priority buffers and delay-tolerant traffic in low-priority buffers. The CAC scheme extends a measurement-based CAC algorithm for a single buffer to the low-priority buffer with the HOLP discipline to provide the cell loss ratio objective. We introduce an equivalent window for monitoring low-priority cell streams. The equivalent window size equals the period within which the number of times the low-priority buffer is scanned to read cells is constant. Thus the equivalent window size varies with the high-priority queueing state. Numerical results indicate that the proposed QoS control scheme using the equivalent-window CAC can utilize network resources more effectively than the conventional control scheme which is Virtual Path (VP) separation for different cell loss requirement services. In addition, it is confirmed that the proposed scheme provides conservative admissible loads. Thus, this proposed scheme can achieve large statistical gains while providing both high-priority and low-priority cell loss ratio objectives. The proposed scheme will be very useful for cost-effective multimedia services that have different QoS requirements.

Advanced MCM-D micro-processor module for ATM wide-area network switching systems

Kawamura Tomoaki, Yamanaka Naoaki, Kaizu Katsumi, Harada Akio, Yashiro Zenichi

21 - 26 1998年

This paper describes an advanced MCM-D micro-processor module and its high-performance cooling technologies for an ATM-WAN (Wide-Area Network) switching system. The MCM-D module is fabricated on 2 Si-substrates using the stacking RAM technique to reduce module size. The MCM has 4-layer Si substrates, a micro-processor LSI, 4 ASIC-LSIs, 12 high-speed SRAMs, an FPGA and bus-driver ICs. By using the stacking RAM technique, MCM-D module size was reduced to 65 mm×85 mm. This is 14% of that (200 mm×200 mm) of assembly area of a conventional circuit using conventional packaging technologies. The MCM-D module was mounted on an ATM line interface circuit board, and realized 25 MHz micro-processor functions with high-speed (access time 25 ns) and large-capacity (4 MBytes) SRAM cache and ATM line interface circuit functions in an ATM-WAN switching system. The line interface circuit board mounted the MCM-D module has high-performance cooling architecture without fin-structure. The MCM-D module is mounted on a sub-board and has thermal contact to the main board through a rubber with low thermal resistance. By using this high-performance cooling architecture, the MCM-D micro-processor module and the ATM line interface circuit board operate under conventional forced air cooling condition without fin-structure. This MCM technology and high-performance cooling technology can be applied to ATM-WAN switching systems and future B-ISDN ATM switching systems.

A 160 GB/s ATM switch using internal speed-up crossbar switch architecture

Genda Kouichi, Yamanaka Naoaki, Doi Yukihiro, Endo Kenichi

Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi) 80 （ 9 ） 68 - 79 1997年09月

ISSN 8756-6621

As an architecture for a large-scale tera bit/s class ATM switch system, a building-block structure combining multiple small-scale switches (AHM: ATM circuit handling module) and interconnection switches (AMC: ATM intermodule connector) is proposed in this paper. In this proposed structure, mesh-like VP connections are made between AHMs by AMCs. Resource management is not done inside the AMC, but is simply executed inside AHMs which interconnect the AMCs. Resources are managed by the total capacity of connectivity (GVP: grouped virtual path) between the AHM and the input/output side AHM. It is shown theoretically that, with this proposed structure, it is possible to increase effectively the switching capacity in proportion to the number of AHMs connected. A new switch architecture with 160 Gb/s switch throughput is also proposed for application to the large-scale ATM switch system proposed in this paper. The proposed switch is an internal speed-up crossbar ATM switch which is suitable for switching high-speed cells. In order to avoid loss of QoS (Quality Of Service) of cells switched by AMC, it accommodates cells which are accelerated up to 10 Gb/s at the output port of the input side AHM. A new high-speed arbitration control algorithm which is distributed to each output line is adopted in this structure. The proposed control algorithm, in which a logical ring is composed of three buses, has a capability twice that of a conventional ring arbiter can realize very high switching throughput above 160 Gb/s. It is shown that a prototype ATM switch has been developed successfully using a combination of new technologies such as a new switch architecture, high-speed Si-bipolar LSI, and a sophisticated multi-chip module technology, and its functions and performance were satisfactorily confirmed. © 1997 Scripta Technica, Inc.

TORUS

Genda Kouichi, Yamanaka Naoaki

IEEE Journal on Selected Areas in Communications 15 （ 5 ） 817 - 828 1997年06月

ISSN 0733-8716

A high-speed and distributed ATM switch architecture, called the TORUS switch, is proposed with the aim of achieving a terabit-per-second ATM switching system. The switch is a distributed and scalable internal speed-up crossbar-type ATM switch with cylindrical structure. The self-bit-synchronization technique and optical interconnection technology are combined to achieve gigabit-rate cell transmission, where high-density implementation technologies such as multichip module technology are not required at all. Also, distributed contention control based on the fixed output-precedence scheme is newly adopted. This control is very suitable for high-speed devices because its circuit is achieved with only one gate in each crosspoint. A TORUS switch is fabricated as a 4 × 2 switch module using optical interconnection technology and very high-speed crosspoint LSI's, constructed using an advanced Si-bipolar process. Measured results confirm that the TORUS switch can be used to realize an expandable terabit-rate ATM switch.

Access to Document (DOI)

Flexible multi-QoS logical ATM network (full-net)

Yamanaka Naoaki, Oki Eiji

Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi) 80 （ 6 ） 47 - 57 1997年06月

ISSN 8756-6621

This paper proposes Full-Net (Flexible Multi-QoS Logical ATM Network), a simple, flexible, and cost-effective network architecture that will enable the development of an advanced multimedia communications network. The backbone of this Full-Net is a VP (virtual path) network where mesh interconnection is made possible between all VCH (virtual channel handler) switches. End-to-end QoS (quality of service) control is executed at access points to the VP network to map out each optimum VC (virtual channel) according to the VCs' respective service characteristics. This is done independently and simultaneously on the same physical ATM network. In the proposed network, a relatively small size switching system is utilized as a transit switch or a local switch depending on the service request. That is, the logical topology of the VC network is altered in response to individual service requests, and multiple VC networks are realized by overlapping them on the same physical network. In order to assure high QoS and construct an optimum VC network, two parameters which characterize the VC network topology are introduced; one is the disjoint route D and the other is the hop limit H. Traffic reliability is the most important QoS factor, and it is shown that an optimum disjoint number D can be determined to maximize the network resource. In the Full-Net, it is clearly shown that it is possible to control easily the end-to-end delay characteristic, also a critical QoS factor, at one or two VCH access points to VP network. The flexible node system PUN (programmable unified node) used in the Full-Net is also described in this paper. The Full-Net described is proposed as an efficient solution for sophisticated network architectures which will satisfy the demand for new services and will flexibly meet the varying demands of the future multimedia age. © 1997 Scripta Technica, Inc.

Very-high-speed ATM switching system technologies

Yamanaka Naoaki, Doi Yukihiro, Fukuda Hideki, Takenaka Toyofumi, Yashiro Zen Ichi

NTT Review 9 （ 2 ） 12 - 19 1997年03月

ISSN 0915-2334

High-performance packaging technology for very-high-speed ATM switching systems

Kaizu Katsumi, Kishimoto Tohru, Sasaki Shin Ichi, Yamanaka Naoaki, Genda Kouichi

NTT Review 9 （ 2 ） 36 - 45 1997年03月

ISSN 0915-2334

This paper describes high-performance, high-density multichip modules (MCMs) using a copper polymide multi-layer substrate and innovative heat-pipe cooling for high-speed ATM switching systems. High-speed ATM link wires are interconnected on the top surface of the MCMs by the newly developed flexible printed circuit cables and con-nectors to reduce the rear-side I/O count and achieve 620-Mbit/s 32-bit parallel interconnections. A heat-pipe is attached to the back surface of each MCM to cool the power dissipation, which is 30 W per MCM. With a 2-m/s forced air flow, a prototype ATM switch system operated at 320 Gbit/s (with 8 × 8 MCMs) with a maximum junction temperature of less than 85 °C. These results indicate that this technology is suitable for future B-ISDN high-speed switching systems.

A very-high-speed ATM switch architecture using internal speed-up technique

Genda Kouichi, Doi Yukihiro, Endo Ken Ichi, Yamanaka Naoaki

NTT Review 9 （ 2 ） 20 - 27 1997年03月

ISSN 0915-2334

An internal speed-up crossbar-type ATM switch architecture is proposed. This switch accommodates 10 Gbit/s cell streams from AHMs in order to guarantee the QoS of switched cells. A new high-speed arbitration algorithm using three buses on each output line, called the bi-directional arbiter, is used. It handles output contention about twice as fast as the conventional ring-arbiter and has the same fairness function. It increases the switch throughput to 160 Gbit/s efficiently. By combining the high-speed switch and AHMs, it will be able to make a sub-terabit/s ATM switching system for future Broadband ISDN networks.

160 Gbit/s high speed ATM switching system

Yamanaka Naoaki, Kaizu Katsumi, Kishimoto Tohru, Genda Kouichi

NTT Review 9 （ 2 ） 28 - 35 1997年03月

ISSN 0915-2334

This paper describes a 160 Gbit/s high speed multi-chip ATM switching system for broadband ISDN. This system uses a Copper/Polyimide MCM with 4-layer copper-polyimide signal transmission layers and 11-layers ceramic power supply layers. It uses 64 MCMs that are interconnected by a 98-high-way flexible printed circuit connector. Si-bipolar VLSIs are mounted on a Multi-Chip Module (MCM) using the 15-μm very thin pitch outer lead TAB technique. The system switches ATM cells at a throughput of up to 320 Gbit/s and it is applicable for future B-ISDN.

A simple cell spacer architecture regenerating source cell interval for multiple traffic classes

Shiomoto Kohci, Yamanaka Naoaki

IEICE Transactions on Communications E80-B （ 1 ） 187 - 191 1997年

ISSN 0916-8516

A new simple cell spacing architecture that guarantees the peak cell interval and realizes preferential contention resolution is proposed. Scheduling the cell emission on departure of the previous cell not arrival allows the source peak cell interval to be regenerated without clumping. Priority control is also realized in the proposed spacer. A connection is scheduled either at the head or tail of the contention chain depending on its priority. The proposed method is applied to realize the UPC function. The proposed cell spacer eliminates the clumping effects of CDV completely and achieves high bandwidth efficiency.

Advanced ATM switching system line interface hardware technologies based on MCM-D integrated with ASIC and S-RAMS

Yamanaka Naoaki, Kawamura Tomoaki, Kaizu Katsumi

286 - 289 1997年

This paper describes newly developed advanced ATM switching system hardware structures. They are based on the Si-Substrate MCM-D technology which integrates ASIC custom VLSIs, high-speed S-RAMs and FPGAs (Field Programmable Gate Arrays). The MCM-D module realizes the ATM layer function by combining a high-performance ASIC with high-speed S-RAM cache. This is made possible by high density packaging and high-speed (20 ns) access to 1-Mbit of memory. The MCM employs 8 S-RAMs, possible with the stacked RAM technique, to reduce module size. This sub-module technology and MCM technology will advance the development of practical B-ISDN ATM switching systems.

Tandem-crosspoint ATM switch architecture and its cost-effective expansion

Oki Eiji, Yamanaka Naoaki, Yasukawa Seisho

45 - 51 1997年

This paper proposes a high-speed input and output buffering ATM switch, named the Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at all crosspoints. The TDXP switch architecture offers several advantages. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. These merits make it easy to implement a high-speed ATM switch. Numerical results show that the TDXP switch can effectively eliminate HOL blocking and achieve high throughput. In addition, we discuss how TDXP switches can be combined to form larger switches in a cost-effective way. We clarify the relative advantages of the crossbar switch configuration and the three-stage Clos switch configuration in achieving a specific throughput. Because the three-stage Clos switch configuration is not strictly non-blocking, we introduce a nearly non-blocking condition and evaluate switch throughput under the condition. The evaluation shows that crossbar switch configuration becomes more cost effective as the throughput of individual switch LSIs, which depends on device technologies, increases.

Extended multicasting technique to allow multiple destinations per output port in ATM switches

Agrawal Jagan P., Yamanaka Naoaki

IEEE Communications Letters 1 （ 4 ） 117 - 118 1997年

ISSN 1089-7798

When a multicast cell at an aynchronous transfer mode (ATM) switch requires distribution of its copies to the multiple users and/or outgoing sub-rate links served by one of its output ports, multiple cell copies at that output port are required. The conventional copy approach and broadcast approach of multicasting either cannot handle such situations or handles at the cost of switch performance. In this letter we propose a technique to enhance the ability of the copy and broadcast approaches to multicasting to enable them to handle such situations efficiently and economically.

Access to Document (DOI)

A high-speed ATM switch based on scalable distributed arbitration

Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E80-B （ 9 ） 1372 - 1376 1997年

ISSN 0916-8516

This paper proposes a high-speed crosspoint-buffer-type ATM switch, named Scalable-Distributed-Arbitration (SDA) switch. The SDA switch employs a new arbitration scheme that allows the switch to be scalable. The SDA switch has a crosspoint buffer and a transit buffer at every crosspoint. Arbitration is executed between the crosspoint buffer and the transit buffer. The arbitration selects a cell based on delay time using a synchronous counter. The selected cell is transferred from a crosspoint buffer to the output port by way of several transit buffers. Since arbitration is executed in a distributed manner at each crosspoint and the arbitration time does not depend on the switch size, the SDA switch can be expanded to realize large throughput. Numerical results show that the SDA switch ensures fairness in terms of delay time. In addition, the maximum delay time and the required crosspoint buffer size of the SDA switch are reduced, compared with those in the conventional switch based on ring arbitration. Thus, the proposed SDA switch based on the new arbitration scheme has a simple and expandable architecture, and will be suitable for future high-speed multimedia ATM networks.

Some new suvivability measures for network analysis and design

Moitra Soumyo D., Oki Eiji, Yamanaka Naoaki

IEICE Transactions on Communications E80-B （ 4 ） 625 - 631 1997年

ISSN 0916-8516

Advanced ATM-layer function MCM-D module for ATM wide-area network

Kawamura Tomoaki, Yamanaka Naoaki, Kaizu Katsumi

486 - 490 1997年

This paper describes a high-performance and cost-effective MCM-D module for an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size was reduced to 50.8 mm×50.8 mm. This is 40% of that (100 mm×65 mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a high-performance ASIC with high-speed (access time 20 ns) and large-capacity (1 MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module was mounted on an ATM line interface circuit, and realized 150 Mbit/s throughput ATM-layer functions(header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM-WAN (wide-area network) switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to ATM-WAN switching systems and future B-ISDN ATM switching systems.

　前のページ - 次のページ　

山中 直明

論文 - 山中 直明

山中　直明

論文 - 山中　直明