KEIO RESEARCHERS INFORMATION SYSTEM

Profile 【 Display / hide 】

Profile 【 Display / hide 】

• Munehiro Tada received the M.S. and Ph.D. degrees from Keio University, Japan, in 1999 and 2007, respectively. He joined NEC Corporation, Japan, in 1999. From 2007 to 2008, he was a visiting scholar at Stanford University. From 2019, he is a cofounder and executive board director at NanoBridge Semiconductor, Inc. From 2024, he is a full professor at Keio University. He published papers with 16-IEDM, 17-VLSI and 11-IITC. He hold more than 100 issued patents.
  He is an IEEE Fellow and a JSAP Fellow. He is an adviser at JST-CREST(2020-), an executive board director at JSAP(2024-2025), a board director at NanoBridge Semiconductor, Inc.(2019-), a director at Yagami Innovation Laboratory in Keio University (2025-), and IEEE Fellow Commitee Member(2026-).

Message from the Faculty Member 【 Display / hide 】

Message from the Faculty Member 【 Display / hide 】

• 
  After completing my graduate studies, I joined a private company and have been involved in semiconductor research and product development for over 20 years. During this time, I experienced numerous transfers, including studying abroad in the United States and being seconded to research associations, where I worked alongside people with diverse perspectives and approaches. In 2019, I founded a startup, and since 2024, I have been engaged at this institution. I aim to leverage my professional experience in the private sector to contribute to education.

Profile Summary 【 Display / hide 】

Profile Summary 【 Display / hide 】

• To address the limitations of semiconductor miniaturization technology, I aim to achieve low-power, high-performance information processing and integrated systems by combining new nanodevices with heterogeneous technologies. With a focus on optimizing systems, I am working on areas such as advanced fine wiring technologies, brain-inspired "brains-in-silicon" circuits using atomic switches, efficient cooling technologies for three-dimensional stacked chips, and quantum bit control systems at cryogenic temperatures.

Licenses and Qualifications 【 Display / hide 】

Licenses and Qualifications 【 Display / hide 】

• 危険物取扱者　甲種（神奈川県知事）, 1999.12

• 特定化学物質等作業主任者（厚生労働省）, 2002.05

• 特定高圧ガス取扱主任者（経済産業省、高圧ガス保安協会）, 2004.05

• Certificate of Stanford Environmental Health & Safety for X-ray Equipment（Stanford University） , 2008.10

• 日商簿記3級（日本商工会議所） , 2020.03

Research Areas 【 Display / hide 】

Research Areas 【 Display / hide 】

• Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment (Semiconductor Device Engineering)

Research Keywords 【 Display / hide 】

Research Keywords 【 Display / hide 】

• Semiconductor device engineering

• ヘテロジーニアス集積システム

• 原子スイッチ・ナノブリッジ

Research Themes 【 Display / hide 】

Research Themes 【 Display / hide 】

• Scaled inteconnect technology, 

  2024.04

  -

  Present

  　View Summary

  2nm世代以降のロジック半導体に用いられる微細配線技術として、銅に代わる代替配線材料の基礎検討を進めます。

• ブレインズインシリコン技術, 

  2024.04

  -

  Present

  　View Summary

  原子スイッチをアナログ素子として用いたニューロフィック回路に関する開発を行います。従来よりも消費電力効率の良いAI処理を目指します。

• 三次元チップ実装における冷却技術の開発, 

  2024.07

  -

  Present

  　View Summary

  発熱量の大きいHPC（High Performance Computing）向けのチップの三次元実装を実現するチップ冷却技術を開発します。

• 超伝導配線・クライオCMOS技術の開発, 

  2024.04

  -

  Present

  　View Summary

  量子コンピューティングを実現するための冷凍機内の制御システムとして、超伝導配線とクライオCMOS義技術の研究開発を進めています。

Books 【 Display / hide 】

Books 【 Display / hide 】

• Book chapter, Applications of Reconfigurable Processors as Embedded Automatons in the Iot Sensor Networks in Space, VLSI Design and Test for Systems Dependability

  H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, Springer, 2018.08,  Page： xvii, 800 p.

  • CiNii Research

Papers 【 Display / hide 】

Papers 【 Display / hide 】

• BEOL Interconnects for 2nm Technology Node and Beyond

  G. Thareja, A. Mema, G. Qu, N. Giulani, D. Cornigli, T. Takahisa, E. Piccinini, X. Wang, A. Palmieri, S. Barkam, M. Jamieson, B. Xie, S. You, S. Sharma, Y. Wu, M. Gage, Z. Wu, R. Shaviv, F. Nardi, M. Haverty, M. Spuller, B. Ng, N. Tam, A. Jansen, A. Lo, Z. Chen, F. K. Mungai, S. Deshpande, H. Ren, J. Tang, M. Naik, S. Kesapragada, C.-I. Lang, S. Muthukrishnan, B. Brown, M. Tada, J. J. Lee, Q. L. Xia, M. Berkens, L. Larcher, K. Kashefizadeh, H. Amrouch and X. Tang

  IEEE/JSAP 2025 Symposium on VLSI Technology and Circuits (VLSI) (IEEE (Institute of Electrical and Electronics Engineers))   2025.06

  Research paper (international conference proceedings), Joint Work

• A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator

  Pai C.W., Uchida K., Tada M., Ishikuro H.

  Microelectronics Journal 153 2024.11

  ISSN  09598324

  　View Summary

  This paper presents a 10-bit 60-MS/s SAR ADC using an energy-efficient common-mode variation suppression (CMVS) switching scheme. The proposed CMVS switching scheme reduces energy consumption by about 92 % compared to the conventional scheme. Also, it narrows the common-mode variation to 16.6 % VDD. It improves the accuracy of the SAR ADC and makes the comparator and SAR ADC operate at the best-performance region. The proposed comparator adopts a gain boosting dynamic capacitive pre-amplifier to enhance the amplification and accelerate the comparison speed. The regeneration latch keeps the cross-coupled inverter structure to ensure high-speed regeneration. The input pair of the latch suppresses the through current while decreasing the regeneration speed. Therefore, an auxiliary input pair is added to enhance the regeneration speed. The SAR ADC is designed and simulated using 65-nm Cryo-CMOS technology with VDD = 1.2 V. At T = 300 K, it achieves a FoM of 15.39 fJ/conversion-step with 55-MS/s. At T = 4 K, it achieves a FoM of 14.15 fJ/conversion-step with 60-MS/s.

  • Access to Document (DOI)

• Imaginary impedance due to hopping phenomena and evaluation of dopant ionization time in cryogenic metal-oxide-semiconductor devices on highly doped substrate

  Tomohisa Miyao, Keito Yoshinaga, Takahisa Tanaka, Hiroki Ishikuro, Munehiro Tada, Ken Uchida

  Applied Physics Express (IOP Publishing)  17 ( 5 ) 051001 - 051001 2024.05

  ISSN  18820778

  　View Summary

  Abstract
  
  MOS capacitors fabricated on substrates with doping concentrations as high as 10¹⁸ cm⁻³ were characterized at 4.2 K. The highly doped substrate exhibited an intrinsic imaginary component of impedance at 4.2 K. The imaginary component is attributed to the time delay induced by hopping phenomena, leading to a decrease in the gate capacitance. Furthermore, we investigated the time constant associated with dopant ionization under depletion conditions and determined it to be 0.35 μs. An equivalent circuit model of the highly doped substrate at 4.2 K is also shown.

  • Access to Document (DOI)

• Superconducting Nb interconnects for Cryo-CMOS and superconducting digital logic applications

  Hideaki Numata, Noriyuki Iguchi, Masamitsu Tanaka, Koichiro Okamoto, Sadahiko Miura, Ken Uchida, Hiroki Ishikuro, Toshitsugu Sakamoto, Munehiro Tada

  Japanese Journal of Applied Physics (IOP Publishing)  63 ( 4 ) 04SP73 - 04SP73 2024.04

  ISSN  00214922

  　View Summary

  Abstract
  
  A 100 nm wide superconducting niobium (Nb) interconnect was fabricated by a 300 mm wafer process for Cryo-CMOS and superconducting digital logic applications. A low pressure and long throw sputtering was adopted for the Nb deposition, resulting in good superconductivity of the 50 nm thick Nb film with a critical temperature (T_c) of 8.3 K. The interconnects had a titanium nitride (TiN)/Nb stack structure, and a double-layer hard mask was used for the dry etching process. The exposed area of Nb film was minimized to decrease the effects of plasma damage during fabrication and atmosphere. The developed 100 nm wide and 50 nm thick Nb interconnect showed good superconductivity with a T_c of 7.8 K and a critical current of 3.2 mA at 4.2 K. These results are promising for Cryo-CMOS and superconducting digital logic applications in the 4 K stage.

  • Access to Document (DOI)

• A 0.11pJ/bit read energy embedded NanoBridge non-volatile memory and its integration in a 28 nm 32 bit RISC-V microcontroller units

  Bai X., Nebashi R., Miyamura M., Funahashi K., Okamoto K., Numata H., Iguchi N., Sakamoto T., Tada M.

  Japanese Journal of Applied Physics (Japanese Journal of Applied Physics)  63 ( 2 )  2024.02

  ISSN  00214922

  　View Summary

  A 28 nm 512 Kb NanoBridge (NB) non-volatile memory is developed for an energy-efficient microcontroller unit. 0.11 pJ/bit read energy is achieved by utilizing an inverter sense scheme thanks to large ON/OFF conductance ratio of a split-electrode NB. The read energy is 71% and 54% less than those of a ReRAM and a silicon oxide nitride oxide silicon commercial embedded NOR flash at the same technology node, respectively. Moreover, a 28 nm 32 bit RISC-V microcontroller unit embedded with a 2 Mb NB non-voltage memory is fabricated and achieves 80 MHz operation frequency.

  • Access to Document (DOI)

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Reviews, Commentaries, etc. 【 Display / hide 】

Reviews, Commentaries, etc. 【 Display / hide 】

• NanoBridge-FPGAによるIoTデバイスの低電力・高性能化

  阪本 利司, 宮村 信, 白 旭, 杉林 直彦, 多田 宗弘

  NEC技報 = NEC technical journal (日本電気)  71 ( 1 ) 97 - 102 2018.09

  ISSN  0285-4139

  • CiNii Research

• 「第4回応用物理学会シリコンテクノロジー分科会論文賞受賞記念講演」原子移動型スイッチの低電圧化と信頼性の改善

  多田 宗弘, 阪本 利司, 宮村 信, 伴野 直樹, 岡本 浩一郎, 井口 憲幸, 波田 博光

  応用物理学会学術講演会講演予稿集 (公益社団法人 応用物理学会)  2013.1   2744 - 2744 2013.03

  • Access to Document (DOI)

Presentations 【 Display / hide 】

Presentations 【 Display / hide 】

• 200nm-pitched,Superconducting Nb Interconnects for Cryo-CMOS Applications

  N.Iguchi,H.Numata,M.Tanaka,K.Okamoto,T.Tanaka,K.Uchida,H.Ishikuro,T.Sakamoto,and M.Tada,

  International Interconnect Technology Conference(IITC)2024,San Jose,United States, 

  2024.06

• A 0.11pJ/bit Read Energy Embedded NanoBridge NVM and its Integration in a 28nm 32-bit RISC-V MCU

  Xu Bai, Ryusuke Nebashi, Makoto Miyamura, Kazunori Funahashi, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Toshitsugu Sakamoto, Munehiro Tada

  International Conference on Solid State Device and Materials (SSDM) K-2-01, (Nagoya, Japan)., 

  2023.09

• Gate-Length Dependent Variability of nMOSFET at Cryogenic Temperatures

  Toshitsugu Sakamoto, Makoto Miyamura, Kazunori Funahashi, Munehiro Tada, Ken Uchida, Hiroki Ishikuro

  International Conference on Solid State Device and Materials (SSDM) F-1-01, (Nagoya, Japan)., 

  2023.09

• NanoBridge use case for FPGA

  Munehiro Tada　(Invited)

  DARPA MEC Back-End of Line (BEOL) Integration of Active Devices Workshop, Institute for Defense Analyses (IDA) (Alexandria, USA)., 

  2023.05

• Stochastic Modeling of Cryogenic and Room Temperature Operation of ReRAM

  T. Tanaka, K. Okamoto, M. Tada, K. Uchida

  35th International Microprocess and Nanotechnology Conference, (Tokushima, Japan)., 

  2022.11

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Intellectual Property Rights, etc. 【 Display / hide 】

Intellectual Property Rights, etc. 【 Display / hide 】

• 記憶装置およびプログラミング方法

  Date applied： JP2020002069  2020.01 

  Date published： WO2020-158531  2020.08 

  Patent

• スイッチング素子およびその製造方法

  Date applied： JP2020000129  2020.01 

  Date published： WO2020-145253  2020.07 

  Patent

• 半導体装置

  Date applied： JP2019016072  2019.04 

  Date published： WO2019-203169  2019.10 

  Patent

• 非線形抵抗素子、スイッチング素子、および非線形抵抗素子の製造方法

  Date applied： 特願2019-061663  2019.03 

  Date announced： 特開2020-161723  2020.10 

  Patent

• 抵抗変化素子の書換え方法、および抵抗変化素子を用いた不揮発性記憶装置

  Date applied： JP2018039252  2018.10 

  Date published： WO2019-082860  2019.05 

  Patent

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Awards 【 Display / hide 】

Awards 【 Display / hide 】

• フェロー

  2021.06, 応用物理学会

• RADECS 2018 Best Conference Paper Award

  2019.10, IEEE

• Fellow

  2019.01, IEEE

• 第66回電気科学技術奨励会会長賞、及び電気科学技術奨励賞

  2018.11

• 第4回 論文賞

  2013.03, 応用物理学会シリコンテクノロジー分科会

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Courses Taught 【 Display / hide 】

Courses Taught 【 Display / hide 】

• SYSTEM DESIGN OF INFORMATION PROCESSING

  2025

• SEMINAR IN SYSTEM DESIGN ENGINEERING

  2025

• REAL TIME SIGNAL PROCESSING

  2025

• LABORATORIES IN SYSTEM DESIGN ENGINEERING 2)

  2025

• INTRODUCTION TO INFORMATICS

  2025

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Memberships in Academic Societies 【 Display / hide 】

Memberships in Academic Societies 【 Display / hide 】

• Institute of Electronics, Information and Communication Engineers (IEICE), 

  2021

  -

  Present

• Japan Society of Applied Physics (JSAP), 

  2000

  -

  Present

• Institute of Electrical and Electronic Engineers (IEEE), 

  2000

  -

  Present

Committee Experiences 【 Display / hide 】

Committee Experiences 【 Display / hide 】

• 2024

  -

  Present

  応用物理学会　理事

• 2024

  -

  Present

  Advanced Metallization Conference (ADMETA), Adviser

• 2023

  IEEE VLSI Technology, System and Applications (VLSI-TSA), Joint Focus Session Organizer

• 2023

  Advanced Metallization Conference (ADMETA), General chair

• 2021

  -

  Present

  システムデバイスロードマップ委員会（SDRJ）Beyond CMOS(BC)　委員

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