KEIO RESEARCHERS INFORMATION SYSTEM

Profile Summary 【 Display / hide 】

Profile Summary 【 Display / hide 】

• Munehiro Tada received the M.S. and Ph.D. degrees from Keio University, Japan, in 1999 and 2007, respectively. He joined NEC Corporation, Japan, in 1999. From 2007 to 2008, he was a visiting scholar at Stanford University. From 2019, he was a cofounder and executive board director at NanoBridge Semiconductor, Inc. From 2024, he is a full professor at Keio University. He published papers with 16-IEDM, 16-VLSI and 10-IITC. He hold more than 100 issued patents.
  He is an IEEE Fellow and a JSAP Fellow. He is an adviser at JST-CREST(2020-presnt) and an executive board director at JSAP(2024-present). He was a General Chair of ADMETA (2023). Non-executive Director at NanoBridge Semiconductor, Inc. from 2024.

Licenses and Qualifications 【 Display / hide 】

Licenses and Qualifications 【 Display / hide 】

• 危険物取扱者　甲種（神奈川県知事）, 1999.12

• 特定化学物質等作業主任者（厚生労働省）, 2002.05

• 特定高圧ガス取扱主任者（経済産業省、高圧ガス保安協会）, 2004.05

• Certificate of Stanford Environmental Health & Safety for X-ray Equipment（Stanford University） , 2008.10

• 日商簿記3級（日本商工会議所） , 2020.03

Research Keywords 【 Display / hide 】

Research Keywords 【 Display / hide 】

• Semiconductor device engineering

• ヘテロジーニアス情報処理集積システム

Books 【 Display / hide 】

Books 【 Display / hide 】

• Book chapter, Applications of Reconfigurable Processors as Embedded Automatons in the Iot Sensor Networks in Space, VLSI Design and Test for Systems Dependability

  H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, Springer, 2018.08,  Page： xvii, 800 p.

Papers 【 Display / hide 】

Papers 【 Display / hide 】

• Imaginary impedance due to hopping phenomena and evaluation of dopant ionization time in cryogenic metal-oxide-semiconductor devices on highly doped substrate

  Tomohisa Miyao, Keito Yoshinaga, Takahisa Tanaka, Hiroki Ishikuro, Munehiro Tada, Ken Uchida

  Applied Physics Express （IOP Publishing)  17 （ 5 ） 051001 - 051001 2024.05

  ISSN  18820778

  　View Summary

  Abstract
  
  MOS capacitors fabricated on substrates with doping concentrations as high as 10¹⁸ cm⁻³ were characterized at 4.2 K. The highly doped substrate exhibited an intrinsic imaginary component of impedance at 4.2 K. The imaginary component is attributed to the time delay induced by hopping phenomena, leading to a decrease in the gate capacitance. Furthermore, we investigated the time constant associated with dopant ionization under depletion conditions and determined it to be 0.35 μs. An equivalent circuit model of the highly doped substrate at 4.2 K is also shown.

  • Access to Document (DOI)

• Superconducting Nb interconnects for Cryo-CMOS and superconducting digital logic applications

  Hideaki Numata, Noriyuki Iguchi, Masamitsu Tanaka, Koichiro Okamoto, Sadahiko Miura, Ken Uchida, Hiroki Ishikuro, Toshitsugu Sakamoto, Munehiro Tada

  Japanese Journal of Applied Physics （IOP Publishing)  63 （ 4 ） 04SP73 - 04SP73 2024.04

  ISSN  00214922

  　View Summary

  Abstract
  
  A 100 nm wide superconducting niobium (Nb) interconnect was fabricated by a 300 mm wafer process for Cryo-CMOS and superconducting digital logic applications. A low pressure and long throw sputtering was adopted for the Nb deposition, resulting in good superconductivity of the 50 nm thick Nb film with a critical temperature (T_c) of 8.3 K. The interconnects had a titanium nitride (TiN)/Nb stack structure, and a double-layer hard mask was used for the dry etching process. The exposed area of Nb film was minimized to decrease the effects of plasma damage during fabrication and atmosphere. The developed 100 nm wide and 50 nm thick Nb interconnect showed good superconductivity with a T_c of 7.8 K and a critical current of 3.2 mA at 4.2 K. These results are promising for Cryo-CMOS and superconducting digital logic applications in the 4 K stage.

  • Access to Document (DOI)

• A 0.11pJ/bit read energy embedded NanoBridge non-volatile memory and its integration in a 28 nm 32 bit RISC-V microcontroller units

  Bai X., Nebashi R., Miyamura M., Funahashi K., Okamoto K., Numata H., Iguchi N., Sakamoto T., Tada M.

  Japanese Journal of Applied Physics （Japanese Journal of Applied Physics)  63 （ 2 ）  2024.02

  ISSN  00214922

  　View Summary

  A 28 nm 512 Kb NanoBridge (NB) non-volatile memory is developed for an energy-efficient microcontroller unit. 0.11 pJ/bit read energy is achieved by utilizing an inverter sense scheme thanks to large ON/OFF conductance ratio of a split-electrode NB. The read energy is 71% and 54% less than those of a ReRAM and a silicon oxide nitride oxide silicon commercial embedded NOR flash at the same technology node, respectively. Moreover, a 28 nm 32 bit RISC-V microcontroller unit embedded with a 2 Mb NB non-voltage memory is fabricated and achieves 80 MHz operation frequency.

  • Access to Document (DOI)

• Design and analysis of a high-speed low-power comparator with regeneration enhancement and through current suppression techniques from 4 K to 300 K in 65-nm Cryo-CMOS

  Chia-Wei Pai, Ken Uchida, Munehiro Tada, Hiroki Ishikuro

  Microelectronics Journal （Elsevier BV)  144   106066 - 106066 2024.02

  ISSN  0026-2692

  • Access to Document (DOI)

• A 65nm Cryogenic CMOS Design and Performance at 4.2K for Quantum State Controller Application

  Tada M., Okamoto K., Tanaka T., Miyamura M., Ishikuro H., Uchida K., Sakamoto T.

  IEEE Journal of the Electron Devices Society （IEEE Journal of the Electron Devices Society)  12   28 - 33 2024

  　View Summary

  A performance evaluation of cryogenic CMOS circuit at liquid-helium temperature (4.2K) is conducted using a standard 65nm bulk CMOS for quantum state controller (QSC) applications. The ON-current (Ion) of the core n/pMOSFET are increased by 25% and 9% with excellent gate modulation (Ion/Ioff=~109). The cryogenic characteristics of copper interconnects in the back end of the line (BEOL), including line and via resistances, capacitances, and Joule-heating effect (JHE) are accurately assessed. The interconnect and via resistances decrease with temperature due to a reduction of electron-phonon scattering, resulting in resistances that are 75% and 20% lower at 4.2K compared to those at room temperature(RT). No significant change in inter-line capacitance and no severe JHE are observed in the Cu BEOL at 4.2K. The developed cell libraries for Simulation Program with Integrated Circuit Emphasis (SPICE) model and the technology file, which includes RC interconnect parameters, enable precise design of CMOS circuits at 4.2K. This results in a demonstrated +18.3% increase in speed or -16% reduction in power consumption for ring-oscillator (ROSC) at 4.2K, aligning well with the simulation results obtained from the developed model.

  • Access to Document (DOI)

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Presentations 【 Display / hide 】

Presentations 【 Display / hide 】

• A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS

  Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada

  Proceedings - 30th International Conference on Field-Programmable Logic and Applications, FPL 2020, 

  2020

  , 

  IEEE

  　View Summary

  © 2020 IEEE. A nonvolatile FPGA using atom-switch crossbars is implemented in a 28nm CMOS. The depopulated atom-switch crossbar with double-gate layout achieves 75% area saving. The routability degradation due to the depopulation is mitigated by a modified routing architecture of mixed segment lengths with thinning out connection block populations. To our knowledge, the novel FPGA provides the largest logic capacity of 171k lookup-table (LUT) among 3D-FPGAs based on monolithically integrated nonvolatile switch and memory. The operating frequency and dynamic power are significantly improved as compared to conventional atom-switch FPGAs.

  • Access to Document (DOI)

• 1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy

  Bai, X. and Banno, N. and Miyamura, M. and Nebashi, R. and Okamoto, K. and Numata, H. and Iguchi, N. and Hashimoto, M. and Sugibayashi, T. and Sakamoto, T. and Tada, M.

  Digest of Technical Papers - Symposium on VLSI Technology, 

  2020

  , 

  Digest of Technical Papers - Symposium on VLSI Technology

  　View Summary

  1.5x energy-efficient and 1.4x operation-speed, nonvolatile via-switch (VS) FPGA with atom switch and a-Si/SiN/a-Si varistor is demonstrated in a 65nm-node for various basic applications. For rapid and low-cost migration from VS-FPGA to ASIC, 'hard-via' to replace VS with 'ON', named VS-copy (VSC), is newly proposed. The VSC-ASIC is fabricated by sharing all the photo masks with VS-FPGA excepting one via mask revise and three VS masks skip, realizing an exact design copy with minimum NRE cost and TAT. The VS-FPGA equipped with the VSC gives energy-efficient edge device, e.g., for up-to-date AI inference algorithms, covering a wide range of chip volume with extremely low cost.

  • Access to Document (DOI)

• 45nm-node interconnects with porous SiOCH-stacks, tolerant of low-cost packaging applications

  N. Inoue, M. Tagami, F. Itoh, H. Yamamoto, T. Takeuchi, S. Saito, N. Furutake, M. Ueki, M. Tada, T. Suzuki, Y. Hayashi

  Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers, 

  2007

  , 

  Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

  　View Summary

  The 45nm-node interconnect with porous SiOCH-stacks of keff=2.9 is confirmed to have the practical reliability in PGBA and QFP. Adhesion strength of the via-ILD to the lower SiCN capping layer significantly impacts on the wire-bond reliability, but spreading the contact area of the bonding-wire within the fine-pitched bonding-pad suppresses the bonding failures in the low-k stack structures, irrespective of additional process of low-k curing or not. No failure was detected during reliability tests in PBGA package as well as QFP, confirming the practicality of the low keff interconnects for 45nm-node ULSIs. © 2007 IEEE.

  • Access to Document (DOI)

Intellectual Property Rights, etc. 【 Display / hide 】

Intellectual Property Rights, etc. 【 Display / hide 】

• 記憶装置およびプログラミング方法

  Date applied： JP2020002069  2020.01 

  Date published： WO2020-158531  2020.08 

  Patent

• スイッチング素子およびその製造方法

  Date applied： JP2020000129  2020.01 

  Date published： WO2020-145253  2020.07 

  Patent

• 半導体装置

  Date applied： JP2019016072  2019.04 

  Date published： WO2019-203169  2019.10 

  Patent

• 非線形抵抗素子、スイッチング素子、および非線形抵抗素子の製造方法

  Date applied： 特願2019-061663  2019.03 

  Date announced： 特開2020-161723  2020.10 

  Patent

• 抵抗変化素子の書換え方法、および抵抗変化素子を用いた不揮発性記憶装置

  Date applied： JP2018039252  2018.10 

  Date published： WO2019-082860  2019.05 

  Patent

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Awards 【 Display / hide 】

Awards 【 Display / hide 】

• フェロー

  2021.06, 応用物理学会

• RADECS 2018 Best Conference Paper Award

  2019.10, IEEE

• Fellow

  2019.01, IEEE

• 第66回電気科学技術奨励会会長賞、及び電気科学技術奨励賞

  2018.11

• 第4回 論文賞

  2013.03, 応用物理学会シリコンテクノロジー分科会

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Courses Taught 【 Display / hide 】

Courses Taught 【 Display / hide 】

• SYSTEMS OF INFORMATION PROCESSING

  2024

• SEMINAR IN SYSTEM DESIGN ENGINEERING

  2024

• REAL TIME SIGNAL PROCESSING

  2024

• INTRODUCTION TO INFORMATICS

  2024

• INDEPENDENT STUDY ON INTEGRATED DESIGN ENGINEERING

  2024

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Memberships in Academic Societies 【 Display / hide 】

Memberships in Academic Societies 【 Display / hide 】

• Institute of Electronics, Information and Communication Engineers (IEICE), 

  2021

  -

  Present

• Japan Society of Applied Physics (JSAP), 

  2000

  -

  Present

• Institute of Electrical and Electronic Engineers (IEEE), 

  2000

  -

  Present

Committee Experiences 【 Display / hide 】

Committee Experiences 【 Display / hide 】

• 2024

  -

  Present

  応用物理学会　理事

• 2024

  -

  Present

  Advanced Metallization Conference (ADMETA), Adviser

• 2023

  IEEE VLSI Technology, System and Applications (VLSI-TSA), Joint Focus Session Organizer

• 2023

  Advanced Metallization Conference (ADMETA), General chair

• 2021

  -

  Present

  システムデバイスロードマップ委員会（SDRJ）Beyond CMOS(BC)　委員

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