Papers - Yoshioka, Kentaro
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An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/step SAR ADC with successively activated threshold configuring comparators in 40 nm CMOS
Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
Transactions on Very Large Scale Integration (VLSI) Systems (IEEE) 23 ( 2 ) 356 - 368 2014.02
Research paper (scientific journal), Joint Work, Lead author, Accepted
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An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique
Kentaro Yoshioka, A Shikata, R Sekimoto, T Kuroda, H Ishikuro
Asia and South Pacific Design Automation Conference (ASP-DAC) (IEEE) 2014.01
Research paper (international conference proceedings), Joint Work, Lead author, Accepted
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A 0.5-V 5.2-fJ/conversion-step full asynchronous SAR ADC with leakage power reduction down to 650 pW by boosted self-power gating in 40-nm CMOS
Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro
Journal of Solid State Circuits (IEEE) 2013.11
Research paper (scientific journal), Joint Work, Accepted
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An adaptive DAC settling waiting time optimized ultra low voltage asynchronous SAR ADC in 40 nm CMOS
Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro
Transactions on electronics (IEICE) E96-C ( 6 ) 820 - 827 2013.06
Research paper (scientific journal), Joint Work, Accepted
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A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique
Kentaro Yoshioka, A Shikata, R Sekimoto, T Kuroda, H Ishikuro
Symposium on VLSI Circuits (IEEE) 2013.06
Research paper (international conference proceedings), Joint Work, Lead author, Accepted
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0.5 V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS
M Nomura, A Muramatsu, H Takeno, S Hattori, D Ogawa, M Nasu, K Hirairi, S Kumashiro, S Moriwaki, Y Yamamoto, S Miyano, Y Hiraku, I Hayashi, K Yoshioka, A Shikata, Hiroki Ishikuro, M Ahn, Y Okuma, X Zhang, Y Ryu, K Ishida, M Takamiya, T. Kuroda, H. Shinohara, T Sakurai
Symposium on VLSI Circuits (IEEE) 2013.06
Research paper (international conference proceedings), Joint Work, Accepted
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A 4–10 bit, 0.4–1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller
Akira Shikata, Ryota Sekimoto, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro
Transactions on electronics (IEICE) E96-A ( 2 ) 443 - 452 2013.02
Research paper (scientific journal), Joint Work, Accepted
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A voltage scaling 0.25–1.8 V delta-sigma modulator with inverter-opamp self-configuring amplifier
Kentaro Yoshioka, Yosuke Toyama, Teruo Jyo, Hiroki Ishikuro
International Symposium on Circuits and Systems (ISCAS) (IEEE) 2013.01
Research paper (international conference proceedings), Joint Work, Lead author, Accepted
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A 0.35-0.8 V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC
Kentaro Yoshioka, A Shikata, R Sekimoto, T Kuroda, H Ishikuro
Asia and South Pacific Design Automation Conference (ASP-DAC) (IEEE) 2013.01
Research paper (international conference proceedings), Joint Work, Lead author, Accepted
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A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating
Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro
Asian Solid State Circuits Conference (A-SSCC) (IEEE) 2012.11
Research paper (international conference proceedings), Joint Work, Accepted
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An 8bit 0.35–0.8 V 0.5–30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator
Kentaro Yoshioka, A Shikata, R Sekimoto, T Kuroda, H Ishikuro
Proceedings of the ESSCIRC (ESSCIRC) 2012.09
Research paper (international conference proceedings), Joint Work, Lead author, Accepted