Papers - Yoshioka, Kentaro

An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging with a 40-Channel 0.0036-mm²Voltage/Time Dual-Data-Converter-Based AFE

Kondo S., Kubota H., Katagiri H., Ota Y., Hirono M., Ta T.T., Okuni H., Ohtsuka S., Ojima Y., Sugimoto T., Ishii H., Yoshioka K., Kimura K., Sai A., Matsumoto N.

IEEE Journal of Solid-State Circuits (IEEE Journal of Solid-State Circuits)  55 ( 11 ) 2866 - 2877 2020.11

Research paper (scientific journal), Joint Work, Accepted,  ISSN  00189200

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This article presents a 40-channel high-resolution automotive LiDAR system-on-chip (SoC), which utilizes the world's first dual-data converter (DDC). The proposed DDC consolidates the functions of ADC and TDC into a single circuitry and achieves acquisition of both high-precision time and voltage data from the input, realizing a 5 times smaller analog front-end (AFE) area than prior arts. Such innovations lead us to a 40-channel AFE integration of the SoC without silicon cost increase, which characterizes our LiDAR system with 2 times higher pixel resolution. To enhance the ADC's signal-to-noise and distortion ratio (SNDR) without sacrificing the area efficiency, a calibration-free and variation-tolerant voltage-controlled oscillator (VCO)-based ADC with a multiphase pulse density modulator (MP-PDM)-based feedback is proposed. Our proof-of-concept LiDAR system achieves a measurement range of 225 m at 70-klx direct sunlight, with a resolution of 240 times 192 pixels at 10 frames per second (FPS). To quantitatively measure the effect of the resolution improvement of our LiDAR, we evaluate the LiDAR's detection accuracy of small targets 75 m away. Due to the 2 times higher vertical pixel resolution, our LiDAR can detect targets with 2 times smaller height. The 3-D point cloud of the LiDAR captured outdoor in the wild is presented.

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A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR

Ta T.T., Kubota H., Kokubun K., Sugimoto T., Hirono M., Sengoku M., Katagiri H., Okuni H., Kondo S., Ohtsuka S., Kwon H., Sasaki K., Ota Y., Suzuki K., Kimura K., Yoshioka K., Sai A., Matsumoto N.

Symposium on VLSI Circuits (IEEE)   2020.06

Research paper (international conference proceedings), Joint Work, Accepted

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This paper introduces several key RX techniques to realize a 200m-range and low-cost high-pixel-resolution solid-state LiDAR for autonomous self-driving systems. In-Sensor Scanning 2D-SPAD array can remove the mechanical mirror and improve the pixel-resolution by implying short dead time active-quenching SPADs. For ToF calculating SoC, we adopt the world first dual-data converter (DDC) which consolidates the functions of ADC and TDC into a single circuitry, achieving the acquisition of both high-precision time/voltage data from a single input. Such innovations lead us to 200m-range 300×80-pixel solid-state LiDAR RX under 70klux solar radiation.

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A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm2 Voltage/Time Dual-Data-Converter-Based AFE

Kondo S., Kubota H., Katagiri H., Ota Y., Hirono M., Ta T.T., Okuni H., Ohtsuka S., Ojima Y., Sugimoto T., Ishii H., Yoshioka K., Kimura K., Sai A., Matsumoto N.

International Solid-State Circuits Conference-(ISSCC) (IEEE)   2020.02

Research paper (international conference proceedings), Joint Work, Accepted

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A safe and reliable self-driving system is a key enabling technology for a society without traffic jams or accidents; LiDAR plays an essential role for such systems. To ensure higher levels of safety and comfort, early detection of small objects (e.g., debris/children) is crucial. To achieve this, state-of-the-art LiDARs [1-3] must attain even more finely scaled pixel resolution: for example, a 0.1-degree angle resolution (a 2x finer resolution than [3]) is required to detect a 20×20cm2 object 100m away. However, hybrid LiDAR systems [3] require a pair of TDC/ADC AFEs per pixel to obtain both precise short-range (SR) distance measurement (DM) and 200m long-range (LR) DM. Scaling the pixel resolution will significantly enlarge the SoC area and explode its cost.

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Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits

Yoshioka K., Sugimoto T., Waki N., Kim S., Kurose D., Ishii H., Furuta M., Sai A., Ishikuro H., Itakura T.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE Transactions on Very Large Scale Integration (VLSI) Systems)  27 ( 11 ) 2575 - 2586 2019.11

Research paper (scientific journal), Joint Work, Lead author, Accepted,  ISSN  10638210

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To realize high-resolution pipelined and pipelined-SAR analog-to-digital-converters (ADCs), an accurate residue amplifier is necessary. However, realizing such an amplifier in scaled CMOS is challenging due to the worsened transistor characteristics. Prior works focused on gain calibration techniques to mitigate the use of low-gain amplifiers, in return of system complexity and prolonged startups. In this paper, we introduce a digital amplifier (DA) technique to realize power-efficient and accurate amplification in scaled CMOS. DA cancels out all errors (i.e., gain error, nonlinearity, incomplete settling, power supply noise, and thermal noise) of the low-gain amplifier by feedback based on successive approximation. The DA accuracy can be arbitrary set by configuring the number of bits in the DA capacitor digital-to-analog-converter; the amplifier gain is decoupled from the transistor intrinsic gain which is suitable for scaled CMOS integration. We also show that the power efficiency can be enhanced over conventional opamp-based designs with relaxed settling error requirements of DA-based multiplying digital-to-analog-converters (MDACs). Moreover, the circuit design of DA-based MDACs is further discussed. Measurement results of the calibration-free 0.7-V 12-bit 160-MS/s pipelined-SAR ADC implemented in 28-nm CMOS are reported. Without calibration, the ADC achieves signal-to-noise-and-distortion-ratio = 61.1 dB, figure-of-merit = 12.8 fJ/conv., which is over 3× improvement compared with conventional calibration-free high-speed pipelined ADCs. In addition, we evaluate the DA's process scalability by comparing the measured results of the DA-based MDAC prototyped in 65-and 28-nm CMOS. We observe 2×-3× improvement in speed, power, and area mainly resulting from the DA's process scalability.

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An 8 bit 12.4 TOPS/W phase-domain MAC circuit for energy-constrained deep learning accelerators

Y Toyama, K Yoshioka, K Ban, S Maya, A Sai, K Onizuka

IEEE Journal of Solid-State Circuits 54 (10), 2730-2742 (IEEE Journal of Solid-State Circuits)  54 ( 10 ) 2730 - 2742 2019.10

Research paper (scientific journal), Joint Work, Accepted,  ISSN  00189200

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A small-gate-count 8 bit bidirectional phase-domain MAC (PMAC) circuit is proposed to minimize both area and energy consumption of extremely energy-efficient deep neural network (DNN) accelerators, targeting the Internet-of-Things (IoT) edge devices operating with very strict power budgets (e.g., energy harvesting). PMAC consumes significantly less energy than standard fully digital MACs, due to its efficient analog accumulation nature based on gated-ring oscillator (GRO). The architectural analysis of energy-efficient accelerators is performed, and the energy budget analysis is disclosed. Furthermore, theoretical analysis of PMAC is conducted and comparisons with the conventional analog approaches are shown. By exploiting the DNN digital quantization noise, we further improve the PMAC energy efficiency by designing the internal gain. The bidirectional architecture proposed in this paper achieves an area comparable to those of digital MACs and up to a fivefold improvement in power efficiency. Moreover, the system design constraints are relaxed by eliminating the phase error originating in leakage currents. An asynchronous readout technique and a two-step digital-to-time converter (DTC) to enhance system throughput and compact implementation, respectively, are presented for the first time. We also present DNN hardware-software co-training procedures to show further scaling of the PMAC efficiency. Utilizing such techniques, the measured PMAC achieves peak efficiency of 12.4 TOPS/W in 28 nm CMOS.

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Dataset Culling: Towards Efficient Training of Distillation-Based Domain Specific Models

Yoshioka K., Lee E., Wong S., Horowitz M.

International Conference on Image Processing, ICIP (IEEE)   2019.09

Research paper (international conference proceedings), Joint Work, Lead author, Accepted

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Real-time CNN-based object detection models for applications like surveillance can achieve high accuracy but are computationally expensive. Recent works have shown 10 to 100× reduction in computation cost for inference by using domain-specific networks. However, prior works have focused on inference only. If the domain model requires frequent retraining, training costs can pose a significant bottleneck. To address this, we propose Dataset Culling: a pipeline to reduce the size of the dataset for training, based on the prediction difficulty. Images that are easy to classify are filtered out since they contribute little to improving the accuracy. The difficulty is measured using our proposed confidence loss metric with little computational overhead. Dataset Culling is extended to optimize the image resolution to further improve training and inference costs. We develop fixed-angle, long-duration video datasets across several domains, and we show that the dataset size can be culled by a factor of 300× to reduce the total training time by 47× with no accuracy loss or even with slight improvement.1

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A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications

Toyama Y., Yoshioka K., Ban K., Sai A., Onizuka K.

Asian Solid State Circuits Conference (A-SSCC) (IEEE)   2018.12

Research paper (international conference proceedings), Joint Work, Accepted

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A small gate count 8 bit bidirectional phase domain MAC (PMAC) circuit is proposed for DNN inference applications targeting IoT edge. PMAC consumes significantly smaller power than standard fully digital MACs, owing to its efficient analog accumulation nature based on Gated-Ring-Oscillator (GRO). Compared with the previous first PoC of PMAC, the bidirectional architecture proposed in this paper achieves 20% less gate count, which is comparable with fully digital MACs, and relaxes system design constraints by eliminating phase error originating in leakage current. Asynchronous readout technique and 2-step DTC for the better system throughput and compact implementation, respectively, are presented for the first time. The PMAC achieves peak efficiency of 12.4 TOPS/W in 28 nm CMOS.

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An 802.11ax 4 × 4 high-efficiency WLAN AP transceiver SoC supporting 1024-QAM with frequency-dependent IQ calibration and integrated interference analyzer

Kawai S., Ito R., Nakata K., Shimizu Y., Nagata M., Takeuchi T., Kobayashi H., Ikeuchi K., Kato T., Hagiwara Y., Fujimura Y., Yoshioka K., Saigusa S., Yoshida H., Arai M., Yamagishi T., Kajihara H., Horiuchi K., Yamada H., Suzuki T., Ando Y., Nakanishi K., Ban K., Sekiya M., Egashira Y., Aoki T., Onizuka K., Mitomo T.

IEEE Journal of Solid-State Circuits (IEEE Journal of Solid-State Circuits)  53 ( 12 ) 3688 - 3699 2018.12

Research paper (scientific journal), Accepted,  ISSN  00189200

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A fully integrated 4 × 4 802.11abgn/ac/ax transceiver system-on-chip (SoC) with integrated interference analyzer and frequency-dependent in-phase and quadrature (IQ) (FD-IQ) calibration is presented. The FD-IQ technique helps meeting the extremely strict IQ imbalance requirement for 1-K quadratic-amplitude modulation (QAM). The pure current-mode TX baseband (BB) improves SNR to better than 50 dB, and a multi-mode local oscillator (LO) distribution circuit provides non-contiguous operation with the error vector magnitude (EVM) of less than -37 dB. The integrated interference analyzer achieves the highly reliable connection in the presence of the undesired signal and hence improves the frequency usage efficiency by identifying the wireless LAN (WLAN) and other signals in the 2G/5G band.

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A 20-ch TDC/ADC hybrid architecture LiDAR SoC for 240 × 96 pixel 200-m range imaging with smart accumulation technique and residue quantizing SAR ADC

Yoshioka K., Kubota H., Fukushima T., Kondo S., Ta T.T., Okuni H., Watanabe K., Hirono M., Ojima Y., Kimura K., Hosoda S., Ota Y., Koizumi T., Kawabe N., Ishii Y., Iwagami Y., Yagi S., Fujisawa I., Kano N., Sugimoto T., Kurose D., Waki N., Higashi Y., Nakamura T., Nagashima Y., Ishii H., Sai A., Matsumoto N.

IEEE Journal of Solid-State Circuits (IEEE Journal of Solid-State Circuits)  53 ( 11 ) 3026 - 3038 2018.11

Research paper (scientific journal), Lead author, Accepted,  ISSN  00189200

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This paper presents a time-to-digital converter/analog-to-digital-converter (TDC/ADC) hybrid LiDAR system-on-chip (SoC) to realize reliable self-driving systems. The smart accumulation technique (SAT) is proposed to achieve both 200-m and high-pixel-resolution range imaging, which was untrodden with conventional LiDARs. The 'smart' accumulation is realized by a simple object recognition strategy with small circuit overhead. When compared to conventional accumulations, the LiDAR range is enhanced without degrading the pixel resolution. Moreover, a TDC/ADC hybrid architecture is proposed to achieve a wide-distance-range LiDAR with a small silicon area and short-range precision. To minimize the ADC cost, a residue-quantizing noise-shaping (RQNS) SAR ADC is proposed. The prototype LiDAR SoC is fabricated in the 28-nm CMOS technology and integrated into the silicon photomultiplier (SiPM)-based LiDAR system. LiDAR measured with 240 × 96 pixels at 10 frames/s achieves a measurement range of 200 m with a 70-klx direct sunlight: The measurement range is 2 × longer than conventional designs. Furthermore, our LiDAR achieves 4 × higher effective pixel resolution compared to conventional designs using simple accumulation. A 3-D point-cloud image acquired with a real-life environment is presented.

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PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators

Yoshioka K., Toyama Y., Ban K., Yashima D., Maya S., Sai A., Onizuka K.

Symposium on VLSI Circuits (IEEE)   2018.10

Research paper (international conference proceedings), Joint Work, Lead author, Accepted

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PhaseMAC (PMAC), a phase domain Gated-Ring-Oscillator (GRO) based 8bit MAC circuit, is proposed to minimize both area and power consumption of deep learning accelerators. PMAC composes of only digital cells and consumes significantly smaller power than standard digital designs, owing to its efficient analog accumulation nature. It occupies 26.6 times smaller area than conventional analog designs, which is competitive to digital MAC circuits. PMAC achieves a peak efficiency of 14 TOPS/W, which is best reported and 48% higher than conventional arts. Results in anomaly detection tasks are demonstrated, which is the hottest application in the industrial IoT scene.

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An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer

Kawai S., Aoyama H., Ito R., Shimizu Y., Ashida M., Maki A., Takeuchi T., Kobayashi H., Urakawa G., Hoshino H., Saigusa S., Koyama K., Morita M., Nihei R., Goto D., Nagata M., Nakata K., Ikeuchi K., Yoshioka K., Tachibana R., Arai M., Teh C.K., Suzuki A., Yoshida H., Hagiwara Y., Kato T., Seto I., Horiguchi T., Ban K., Takahashi K., Kajihara H., Yamagishi T., Fujimura Y., Horiuchi K., Nonin K., Kurose K., Yamada H., Taniguchi K., Sekiya M., Tomizawa T., Taki D., Ikuta M., Suzuki T., Ando Y., Yashima D., Kaihotsu T., Mori H., Nakanishi K., Kumagaya T., Unekawa Y., Aoki T., Onizuka K., Mitomo T.

International Solid-State Circuits Conference-(ISSCC) (IEEE)  61   442 - 444 2018.03

Research paper (international conference proceedings), Joint Work, Accepted

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An exponentially Increasing number of wireless-LAN (WLAN) devices In a dense environment causes a decrease in throughput owing to collisions among the devices and the lack of contiguous bandwidth. The next-generation standard of 802.11ax improves spectrum efficiency by additionally supporting 1024 (1K) QAM, OFDMA with 80+80MHz; these impose several challenges to silicon design. 1K-QAM demands extreme IQ balance with an IRR better than -50dB over a wide frequency range up to 80MHz to achieve at least -35dB RX EVM or less. Noise characteristics better than -44dBc LO integrated phase noise as well as 50dB isolation between each TRX chain are mandatory. To best make use of the essential features defined in the 11ax standard, a real-time and arbitrary spectrum-resource control capability at each access point (AP) is beneficial both in terms of further improvement in spectrum efficiency as well as communication reliability in ISM coexisting bands and legacy WLAN. Interference identification of the order of 10μϵ while incorporating everything into a strictly limited silicon area is key to launching the advanced unique functionality. This paper presents a fully integrated 4×4 802.11abgn/ac/ax-compliant AP transceiver SoC. The chip offers frequency-dependent IQ (FD-IQ) mismatch calibration for both amplitude and phase, low-noise TX BB and multimode LO distribution techniques, and real-time interference detection including 2.4GHz inverter-type microwave (MW) ovens.

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A 20ch TDC/ADC hybrid SoC for 240× 96-pixel 10%-reflection< 0.125%-precision 200m-range imaging LiDAR with smart accumulation technique

Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Masatoshi Hirono, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiko Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto

International Solid-State Circuits Conference-(ISSCC) (IEEE)   2018.02

Research paper (international conference proceedings), Joint Work, Lead author, Accepted

A 0.7 V 12b 160MS/s 12.8 fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique

Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura

International Solid-State Circuits Conference-(ISSCC) (IEEE)   2017.02

Research paper (international conference proceedings), Joint Work, Lead author, Accepted

Dynamic architecture and frequency scaling in 0.8–1.2 GS/s 7 b subranging ADC

Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro

Journal of Solid State Circuits (IEEE)  50 ( 4 ) 932 - 945 2015.04

Research paper (scientific journal), Joint Work, Lead author, Accepted

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A 13b SAR ADC with eye-opening VCO based comparator

Kentaro Yoshioka, Hiroki Ishikuro

European Solid State Circuits Conference (ESSCIRC)  2014.09

Research paper (international conference proceedings), Joint Work, Lead author, Accepted

7-bit 0.8–1.2 GS/s dynamic architecture and frequency scaling subrange ADC with binary-search/flash live configuring technique

Kentaro Yoshioka, R Saito, T Danjo, S Tsukamoto, H Ishikuro

Symposium on VLSI Circuits (IEEE)   2014.06

Research paper (international conference proceedings), Joint Work, Lead author, Accepted

An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/step SAR ADC with successively activated threshold configuring comparators in 40 nm CMOS

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

Transactions on Very Large Scale Integration (VLSI) Systems (IEEE)  23 ( 2 ) 356 - 368 2014.02

Research paper (scientific journal), Joint Work, Lead author, Accepted

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An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique

Kentaro Yoshioka, A Shikata, R Sekimoto, T Kuroda, H Ishikuro

Asia and South Pacific Design Automation Conference (ASP-DAC) (IEEE)   2014.01

Research paper (international conference proceedings), Joint Work, Lead author, Accepted

A 0.5-V 5.2-fJ/conversion-step full asynchronous SAR ADC with leakage power reduction down to 650 pW by boosted self-power gating in 40-nm CMOS

Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro

Journal of Solid State Circuits (IEEE)   2013.11

Research paper (scientific journal), Joint Work, Accepted

An adaptive DAC settling waiting time optimized ultra low voltage asynchronous SAR ADC in 40 nm CMOS

Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro

Transactions on electronics (IEICE)  E96-C ( 6 ) 820 - 827 2013.06

Research paper (scientific journal), Joint Work, Accepted

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