Details of a Researcher - Yamasaki Nobuyuki

Yamasaki Nobuyuki

写真a

Affiliation: Faculty of Science and Technology, Department of Information and Computer Science (Yagami)

Position: Professor

Related Websites

山﨑研究室ホームページ

External Links

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Career 【 Display / hide 】

1996.04

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1998.09

通商産業省工業技術院電子技術総合研究所
1997.10

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2000.09

科学技術振興事業団さきがけ研究21 研究員
1998.10

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2000.03

大学助手(有期)(理工学部情報工学科)
1998.10

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2002.03

電子技術総合研究所 COE特別研究員
2000.04

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2004.03

大学専任講師(理工学部情報工学科)

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Academic Background 【 Display / hide 】

1991.03

Keio University, Faculty of Science and Technology, Physics

University, Graduated
1996.03

Keio University, Graduate School, Division of Science and Engineeri

Graduate School, Completed, Doctoral course

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Academic Degrees 【 Display / hide 】

工学　, Keio University, 1996.03

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Research Areas 【 Display / hide 】

Informatics / Computer system (Computer System Network)
Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Communication and network engineering (Communication/Network Engineering)
Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment (Electronic Device/Electronic Equipment)
Informatics / Software (ソフトウエア)
Informatics / Mechanics and mechatronics (Intelligent Mechanics/Mechanical System)

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Research Keywords 【 Display / hide 】

Operating System
System LSI
Processor Architecture
Real-Time Communication
Robot

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Books 【 Display / hide 】

電気学会誌

YAMASAKI NOBUYUKI, 2007.03

Scope: 156-160
日本ロボット学会新版ロボット工学ハンドブック基礎編

山﨑信行、他, 日本ロボット学会新版ロボット工学ハンドブック基礎編, 2005

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表記題名についてハンドブックへの解説を行う。
バーチャルリアリティとテレロボティクス，アクティブインタフェースとパーソナルロボット

山﨑信行、他, 情報処理学会　新版情報処理ハンドブック, 1995

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表記題名についてハンドブックへの解説を行う。
オブジェクト指向コンピューティングI

YAMASAKI NOBUYUKI, 1993.07
リアルタイム処理システム

山﨑信行、他, 日本機会学会機械工学便覧基礎編

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表記題名について便覧への解説を行う。

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Papers 【 Display / hide 】

Migration Using Context Cache for Multicore RISC-V Processor

Akira Yamazawa, Tsutomu Itou, Kazutoshi Suito and Nobuyuki Yamasaki

Concurrency and Computation: Practice and Experience vol.37 2025.10

Research paper (scientific journal), Joint Work, Accepted

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With the advancement of computer technology, modern systems increasingly run multiple programs. A context switch occurs when the operating system switches the executing program from one thread to another. During this process, the system saves the current thread's context to memory and restores the context of the following thread from memory. However, the context switch has significant overhead, which can degrade overall system performance if it occurs frequently. In this study, we design the context cache for a multicore RISC-V processor to reduce the migration overhead caused by context switches between multiple cores. By utilizing a context cache, we aim to accelerate context switches and improve system performance and efficiency. We evaluated the context cache, which reduced the overhead of thread migration. Furthermore, we assessed the trade-off between performance and area by changing its configuration.
A Design of Fault-Tolerant System for Safety-Critical Systems

Kai Yoshizawa, Nobuyuki Yamasaki

2025 11th International Conference on Automation, Robotics, and Applications (ICARA) 280 - 284 2025.02

Research paper (international conference proceedings), Joint Work, Accepted

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In safety-critical systems where failures or faults can lead to accidents, especially in special and harsh environments like those encountered in spacecraft, it is well known that multiple levels of errors can significantly increase the likelihood of system failure. For instance, system-level errors may occur due to cable breaks caused by severe vibrations, while gate-level errors can arise from radiation effects on System-on-Chip (SoC) semiconductors. Furthermore, in such specialized environments, human repair is often not feasible, necessitating that the system continue to operate even when a fault occurs in a part of it. Therefore, this research discusses the design, implementation, and evaluation of a redundant system that combines multi-level redundancy mechanisms to tolerate multiple errors and maintain operation. The implementation was carried out on the Space I/O Core (SIOC), a System-on-Chip equipped with processors and I/O for distributed real-time systems. Additionally, bitstreams were created from the implemented logic, and the performance of the fault-tolerant system was evaluated using an actual FPGA.
A Learning-based Control Scheme for Prioritized SMT Processor

Kaname Sato, Nobuyuki Yamasaki

Proceedings - 2024 Twelfth International Symposium on Computing and Networking Workshops (CANDARW) (Proceedings - 2024 Twelfth International Symposium on Computing and Networking Workshops (CANDARW)) 76 - 82 2024.11

Research paper (international conference proceedings), Accepted
Context Cache for Multicore RISC-V Processor

Akira Yamazawa, Tsutomu Itou, Kazutoshi Suito and Nobuyuki Yamasaki

Proceedings - 2024 Twelfth International Symposium on Computing and Networking (CANDAR) (Proceedings - 2024 Twelfth International Symposium on Computing and Networking (CANDAR)) 272 - 278 2024.11

Research paper (international conference proceedings), Accepted
A Design Scheme for Highly Efficient Mixed-Criticality Systems Using IPC Control

Kosuke Yashima, Nobuyuki Yamasaki

14th International Workshop on Networking, Computing, Systems, and Software 2024.02

Research paper (international conference proceedings)

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Presentations 【 Display / hide 】

エラーフリーPOF用軽量Codecの設計

和田光平, 山崎信行

第252回システム・アーキテクチャ・第208回システムとLSIの設計技術・第68回組込みシステム合同研究発表会(ETNET2025) (日本) ,

2025.03
,
Oral presentation (general)
IPC制御可能なRMT Processor用Hypervisor iRMTvisorの設計と実装

佐貫陽香, 山崎信行

第252回システム・アーキテクチャ・第208回システムとLSIの設計技術・第68回組込みシステム合同研究発表会(ETNET2025),

2025.03
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Oral presentation (general)
RISC-V ISAを用いたGPGPUのCompute Unitの設計

武藤圭汰, 山崎信行

第252回システム・アーキテクチャ・第208回システムとLSIの設計技術・第68回組込みシステム合同研究発表会(ETNET2025),

2025.03
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Oral presentation (general)
マルチコア RISC-V プロセッサ用コンテキストキャッシュの設計

山澤彪, 伊藤務, 水頭一壽, 山﨑信行

第248回システム・アーキテクチャ・第205回システムとLSIの設計技術・第65回組込みシステム合同研究発表会（ETNET2024）,

2024.03
リアルタイムシステム向けRISC-V SMTプロセッサの設計

野尻悠太, 山﨑信行

第248回システム・アーキテクチャ・第205回システムとLSIの設計技術・第65回組込みシステム合同研究発表会,

2024.03

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Intellectual Property Rights, etc. 【 Display / hide 】

半導体装置

Date applied：特願2023-69504 2023.04

Date announced：特開2024-155089 2024.10

Patent
処理制御装置及びプロセッサ

Date applied：特願2023-69503 2023.04

Date announced：特開2024-155088 2024.10

Patent
Multithreaded central processing unit and simultaneous multithreading control method

Date applied： PCT出願番号：PCT/JP2006/311022 2006.06

Patent
Context switching method, context switching unit, context switching program, storage medium, and central processing unit

Date applied： PCT出願番号：PCT/JP03/15838 2005.06

Patent
マルチスレッド中央演算装置および同時マルチスレッディング制御方法

Date applied：特願2005-167427 2005.06

Patent

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Awards 【 Display / hide 】

日本ロボット学会研究奨励賞

YAMASAKI NOBUYUKI, 1998.10, 日本ロボット学会
FPGA/PLDデザインカンファレンス優秀論文賞

YAMASAKI NOBUYUKI, 1999.06
日本機械学会ロボティクスメカトロニクス部門ベストプレゼンテーション賞

YAMASAKI NOBUYUKI, 2001.06, 日本機械学会ロボティクスメカトロニクス部門
日本ロボット学会論文賞

YAMASAKI NOBUYUKI, 2002.10, 日本ロボット学会
情報処理学会システムLSI設計技術研究会優秀論文賞

YAMASAKI NOBUYUKI, 2004.07, 情報処理学会システムLSI設計技術研究会