Yamasaki Nobuyuki

写真a

Affiliation

Faculty of Science and Technology, Department of Information and Computer Science (Yagami)

Position

Professor

Related Websites

External Links

Career 【 Display / hide

  • 1996.04
    -
    1998.09

    通商産業省 工業技術院 電子技術総合研究所

  • 1997.10
    -
    2000.09

    科学技術振興事業団 さきがけ研究21 研究員

  • 1998.10
    -
    2000.03

    大学助手(有期)(理工学部情報工学科)

  • 1998.10
    -
    2002.03

    電子技術総合研究所 COE特別研究員

  • 2000.04
    -
    2004.03

    大学専任講師(理工学部情報工学科)

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Academic Background 【 Display / hide

  • 1991.03

    Keio University, Faculty of Science and Technology, Physics

    University, Graduated

  • 1996.03

    Keio University, Graduate School, Division of Science and Engineeri

    Graduate School, Completed, Doctoral course

Academic Degrees 【 Display / hide

  • 工学 , Keio University, 1996.03

 

Research Areas 【 Display / hide

  • Informatics / Computer system (Computer System Network)

  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Communication and network engineering (Communication/Network Engineering)

  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment (Electronic Device/Electronic Equipment)

  • Informatics / Software (ソフトウエア)

  • Informatics / Mechanics and mechatronics (Intelligent Mechanics/Mechanical System)

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Research Keywords 【 Display / hide

  • Operating System

  • System LSI

  • Processor Architecture

  • Real-Time Communication

  • Robot

 

Books 【 Display / hide

  • 電気学会誌

    YAMASAKI NOBUYUKI, 2007.03

    Scope: 156-160

  • 日本ロボット学会 新版ロボット工学ハンドブック 基礎編

    山﨑信行、他, 日本ロボット学会 新版ロボット工学ハンドブック 基礎編, 2005

     View Summary

    表記題名についてハンドブックへの解説を行う。

  • バーチャルリアリティとテレロボティクス,アクティブインタフェースとパーソナルロボット

    山﨑信行、他, 情報処理学会 新版情報処理ハンドブック, 1995

     View Summary

    表記題名についてハンドブックへの解説を行う。

  • オブジェクト指向コンピューティングI

    YAMASAKI NOBUYUKI, 1993.07

  • リアルタイム処理システム

    山﨑信行、他, 日本機会学会 機械工学便覧 基礎編

     View Summary

    表記題名について便覧への解説を行う。

Papers 【 Display / hide

  • Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems

    Shota Nakabeppu, Nobuyuki Yamasaki

    IEICE Transactions on Electronics (Institute of Electronics, Information and Communication, Engineers, IEICE)  E106.C ( 7 ) 365 - 381 2023.07

    Research paper (scientific journal), Joint Work, Accepted

     View Summary

    It is very important to design an embedded real-time system as a fault-tolerant system to ensure dependability. In particular, when a power failure occurs, restart processing after power restoration is required in a real-time system using a conventional processor. Even if power is restored quickly, the restart process takes a long time and causes deadline misses. In order to design a fault-tolerant real-time system, it is necessary to have a processor that can resume operation in a short time immediately after power is restored, even if a power failure occurs at any time. Since current embedded real-time systems are required to execute many tasks, high schedulability for high throughput is also important. This paper proposes a non-stop microprocessor architecture to achieve a fault-tolerant real-time system. The non-stop microprocessor is designed so as to resume normal operation even if a power failure occurs at any time, to achieve little performance degradation for high schedulability even if checkpoint creations and restorations are performed many times, to control flexibly non-volatile devices through software configuration, and to ensure data consistency no matter when a checkpoint restoration is performed. The evaluation shows that the non-stop microprocessor can restore a checkpoint within 5µsec and almost hide the overhead of checkpoint creations. The non-stop microprocessor with such capabilities will be an essential component of a fault-tolerant real-time system with high schedulability.

  • Data Rearrange Unit for Efficient Data Computation

    Akiyuki Mamiya, Nobuyuki Yamasaki

    International Journal of Networking and Computing 12 ( 2 ) 295 - 316 2022.07

    Research paper (scientific journal), Joint Work, Accepted

     View Summary

    Recently, the demand for computation-intensive applications such as multimedia and AI applications has increased. Data-parallel execution units are typically used for calculations in these applications to increase computational throughput. However, the data required for computation may need to be accessed at discontinuous memory addresses, which can reduce computation efficiency. Generally, normal memory access instructions access data blocks of continuously allocated memory addresses, containing both valid and invalid data for computation. These memory access patterns result in low computation density in the data parallel execution units, wasting computation resources. Therefore, simply increasing the number of data-parallel execution units leads to an increase in wasted computational resources, which will become a significant issue in embedded systems where multiple resource limitations exist. It is essential to improve computational efficiency to perform practical computation in such systems. This paper introduces a Data Rearrange Unit (DRU), which gathers and rearranges valid computation data between main memory and execution units. The DRU improves the performance of multimedia and AI application by significantly reducing the access rate from/to main memory and increasing computation efficiency. It is applicable to most hardware architectures, and its effectiveness can be further enhanced by the execution unit interface that directly connects the DRU to the execution unit. We demonstrate the effectiveness of our DRU by implementation on the RMTP SoC, improving convolution throughput on a data-parallel execution unit by a maximum of 94 times while only increasing the total cell area by about 12.7%.

  • Prioritized Asynchronous Calls for Parallel Processing on Responsive MultiThreaded Processor

    Lopez Tomas A., Yamasaki Nobuyuki

    Proceedings - 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022 (Proceedings - 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022)     46 - 55 2022

    Research paper (international conference proceedings), Accepted

     View Summary

    With the advent of parallel processors for embedded systems, it is very important to design new runtime and system features so that embedded software developers can take advantage of the increased throughput and responsiveness without the hindrances of low-level synchronization and data sharing. In this paper, we design and implement a fully-prioritized, work-conserving, and event-driven parallel computing runtime on Responsive MultiThreaded Processor (RMTP), a simultaneous multi-threading (SMT) processing platform with priority for real-time systems, which implements hardware-based resource allocation and context switching. The proposed runtime achieves low-cost forks and fine-grained prioritized scheduling by using special-purpose hardware functionalities on the RMTP, and also reduces resource over-subscription penalties while allowing for dynamic parallelism by employing a continuation-stealing execution strategy. We evaluate the performance of the proposed system with a set of benchmarks derived from the MiBench suite, and show that meaningful speedup can be achieved even when the degree of parallelism at each level is dynamically varied.

  • Real-Time Execution based on Fluid Scheduling by using IPC Control Scheme

    Santo A., Yamasaki N.

    Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 (Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021)     459 - 463 2021

     View Summary

    Fluid scheduling is an optimal real-time scheduling applicable to multiprocessor systems and is a scheduling model so that every real-time task is executed at a constant speed from release time to deadline. It is necessary for fluid scheduling to control the execution speed of each task. But, since the execution speed of the task is invariable in a conventional general purpose processor. Therefore, fluid scheduling is conventionally achieved by repeatedly executing and stopping tasks. However, this method incurs significant overheads due to frequent task switching. On the other hand, fluid scheduling without overhead by using an IPC control scheme has been proposed. The IPC control scheme controls the execution speed of each thread in an SMT processor. We propose a new IPC control scheme to extract thread-level parallelism and improve throughput effectively, also improving the schedulability of the fluid schedule. The evaluation results show that the proposed method improved the total throughput of the fluid schedule.

  • Data Rearrange Unit for Efficient Data Computation in Embedded Systems

    Mamiya A., Yamasaki N.

    Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 (Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021)     101 - 106 2021

     View Summary

    Recently demands for computation intensive applications such as convolutional neural networks (CNNs) have been increasing. In these applications, valid data for computation are allocated in non-continuous addresses. Therefore, common burst memory access pattern results in a low spatial locality of valid data per access. As a result, computation of data parallel execution units degrades in throughput, as computation resource is wasted by computing invalid data. This is especially a problem in embedded systems in which constraints in power consumption provoke a requirement for high computation efficiency. In this paper, we introduce a Data Rearrange Unit (DRU), a hardware unit rearranging computation data to increase spatial locality of valid data. The DRU drastically reduces the main memory access rate and increases computation efficiency by decreasing memory access to reduce power consumption. We demonstrate the effectiveness of our DRU by implementation on the RMTP SoC [1] [2] improving convolution throughput on a data parallel execution unit by a maximum of 94times, while only increasing the total cell area by about 13%.

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Presentations 【 Display / hide

  • RMTPベースのマルチスレッドRISC-Vプロセッサの設計

    野尻 悠太

    組込み技術とネットワークに関するワークショップ ETNET 2023, 

    2023.03

    Oral presentation (general)

  • Decoded Instruction Cacheの設計

    眞柄 岳郎

    組込み技術とネットワークに関するワークショップ ETNET 2023, 

    2023.03

    Oral presentation (general)

  • Fluidスケジューリングを用いた高効率なMixed Criticalityスケジューリング

    八島 幸祐

    組込み技術とネットワークに関するワークショップ ETNET 2022, 

    2022.03

    Oral presentation (general)

  • SMT Processor用Imprecise Mixed Criticalityスケジューリング

    名倉 怜央

    組込み技術とネットワークに関するワークショップ ETNET 2022, 

    2022.03

    Oral presentation (general)

  • RMT Processor用Hypervisor RMTvisorの設計

    牧野 真成

    組込み技術とネットワークに関するワークショップ ETNET 2022, 

    2022.03

    Oral presentation (general)

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Intellectual Property Rights, etc. 【 Display / hide

  • Multithreaded central processing unit and simultaneous multithreading control method

    Date applied: PCT出願番号:PCT/JP2006/311022  2006.06 

    Patent

  • Context switching method, context switching unit, context switching program, storage medium, and central processing unit

    Date applied: PCT出願番号:PCT/JP03/15838  2005.06 

    Patent

  • マルチスレッド中央演算装置および同時マルチスレッディング制御方法

    Date applied: 特願2005-167427  2005.06 

    Patent

  • Communications method and communications system

    Date applied: EU特許庁 出願番号:05000821.8  2005.01 

    Date issued: 第1549005号  2009.03

    Patent

  • 命令発行方法及び装置、中央演算装置、命令発行プログラム及びそれを記憶したコンピュータ読み取り可能な記憶媒体

    Date applied: 特願2003-83001  2003.03 

    Date announced: 特開2004-295195   

    Date issued: 特許第3646137号  2005.02

    Patent

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Awards 【 Display / hide

  • 日本ロボット学会 研究奨励賞

    YAMASAKI NOBUYUKI, 1998.10, 日本ロボット学会

  • FPGA/PLDデザインカンファレンス 優秀論文賞

    YAMASAKI NOBUYUKI, 1999.06

  • 日本機械学会ロボティクスメカトロニクス部門 ベストプレゼンテーション賞

    YAMASAKI NOBUYUKI, 2001.06, 日本機械学会ロボティクスメカトロニクス部門

  • 日本ロボット学会 論文賞

    YAMASAKI NOBUYUKI, 2002.10, 日本ロボット学会

  • 情報処理学会システムLSI設計技術研究会 優秀論文賞

    YAMASAKI NOBUYUKI, 2004.07, 情報処理学会システムLSI設計技術研究会

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Courses Taught 【 Display / hide

  • SYSTEM ON A CHIP DESIGN

    2023

  • RECITATION IN INFORMATION AND COMPUTER SCIENCE

    2023

  • PROGRAMMING 3

    2023

  • MICROPROCESSOR ARCHITECTURE

    2023

  • INDEPENDENT STUDY ON SCIENCE FOR OPEN AND ENVIRONMENTAL SYSTEMS

    2023

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Courses Previously Taught 【 Display / hide

  • マイクロプロセッサ特論

    Keio University

    2014.04
    -
    2015.03

    Autumn Semester

  • 組込みリアルタイムシステム

    Keio University

    2014.04
    -
    2015.03

    Autumn Semester

  • プログラミング第3同演習

    Keio University

    2014.04
    -
    2015.03

    Autumn Semester

  • System-on-a-Chip 設計技術

    Keio University

    2014.04
    -
    2015.03

    Spring Semester

  • 計算機基礎

    Keio University

    2014.04
    -
    2015.03

    Spring Semester

 

Memberships in Academic Societies 【 Display / hide

  • Information Processing Society of Japan, 

    1993
    -
    Present
  • The Robotics Society of Japan

     
  • The Institute of Electronics, Information and Communication Engineers

     
  • IEEE Institute of Electrical and Electonic Engineers

     

Committee Experiences 【 Display / hide

  • 1993
    -
    Present

    Member, Information Processing Society of Japan

  •  

    会員, IEEE Institute of Electrical and Electonic Engineers

  •  

    会員, 日本ロボット学会

  •  

    会員, 電子情報通信学会

  •  

    Member, IEEE Institute of Electrical and Electonic Engineers

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