KEIO RESEARCHERS INFORMATION SYSTEM

Career 【 Display / hide 】

Career 【 Display / hide 】

• 1996.04

  -

  1998.09

  通商産業省 工業技術院 電子技術総合研究所

• 1997.10

  -

  2000.09

  科学技術振興事業団 さきがけ研究21 研究員

• 1998.10

  -

  2000.03

  大学助手(有期)(理工学部情報工学科)

• 1998.10

  -

  2002.03

  電子技術総合研究所 COE特別研究員

• 2000.04

  -

  2004.03

  大学専任講師(理工学部情報工学科)

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Academic Background 【 Display / hide 】

Academic Background 【 Display / hide 】

• 1991.03

  Keio University, Faculty of Science and Technology, Physics

  University, Graduated

• 1996.03

  Keio University, Graduate School, Division of Science and Engineeri

  Graduate School, Completed, Doctoral course

Academic Degrees 【 Display / hide 】

Academic Degrees 【 Display / hide 】

• 工学　, Keio University, 1996.03

Research Areas 【 Display / hide 】

Research Areas 【 Display / hide 】

• Informatics / Computer system (Computer System Network)

• Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Communication and network engineering (Communication/Network Engineering)

• Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment (Electronic Device/Electronic Equipment)

• Informatics / Software (ソフトウエア)

• Informatics / Mechanics and mechatronics (Intelligent Mechanics/Mechanical System)

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Research Keywords 【 Display / hide 】

Research Keywords 【 Display / hide 】

• Operating System

• System LSI

• Processor Architecture

• Real-Time Communication

• Robot

Books 【 Display / hide 】

Books 【 Display / hide 】

• 電気学会誌

  YAMASAKI NOBUYUKI, 2007.03

  Scope: 156-160

• 日本ロボット学会 新版ロボット工学ハンドブック 基礎編

  山﨑信行、他, 日本ロボット学会 新版ロボット工学ハンドブック 基礎編, 2005

  　View Summary

  表記題名についてハンドブックへの解説を行う。

• バーチャルリアリティとテレロボティクス，アクティブインタフェースとパーソナルロボット

  山﨑信行、他, 情報処理学会　新版情報処理ハンドブック, 1995

  　View Summary

  表記題名についてハンドブックへの解説を行う。

• オブジェクト指向コンピューティングI

  YAMASAKI NOBUYUKI, 1993.07

• リアルタイム処理システム

  山﨑信行、他, 日本機会学会 機械工学便覧 基礎編

  　View Summary

  表記題名について便覧への解説を行う。

Papers 【 Display / hide 】

Papers 【 Display / hide 】

• A Design Scheme for Highly Efficient Mixed-Criticality Systems Using IPC Control

  Kosuke Yashima, Nobuyuki Yamasaki

  14th International Workshop on Networking, Computing, Systems, and Software  2024.02

• A Scheme Reducing Task Drops for Data Dependent Tasks on Mixed Criticality Systems

  Reo Nagura, Nobuyuki Yamasaki

  14th International Workshop on Networking, Computing, Systems, and Software  2024.02

• A Non-stop Fault-Tolerant Real-Time System-on-Chip/System-in-Package

  Shota Nakabeppu, Nobuyuki Yamasaki

  2023 Eleventh International Symposium on Computing and Networking (CANDAR)  2024.02

  Accepted

  　View Summary

  Today, embedded real-time systems such as automobiles, spacecraft, and sensor networks are parts of social infrastructures. Since a system failure in these systems may lead to a severe accident, these systems should be designed as fault-tolerant systems. If a power failure occurs in an embedded real-time system, values of all flip-flops and main memory are lost, resulting in a system failure.This paper describes the design, implementation, and evaluation of a system-on-chip/system-in-package for a non-stop fault-tolerant real-time system that continues to operate even with an unstable power supply. We designed and implemented a non-stop fault-tolerant real-time system-on-chip (SoC) that integrates a non-stop microprocessor, a non-volatile memory (MRAM), a volatile memory (SRAM), and IO peripherals. We also co-designed and implemented a non-stop fault-tolerant real-time system-in-package (SiP) that integrates the SoC, an FPGA, memories, a USB power delivery (USB PD), DC/DC converters, a potentiometer, and a board-to-board (BtoB) connector at the same time to support functions not included in the SoC but required. We evaluated the bit error rate of store operations and benchmark performance with checkpoint creations on the actual SiP.

• A Design of Multithreaded RISC-V Processor for Real-Time System

  Yuta Nojiri, Nobuyuki Yamasaki

  2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW)  2024.02

  Accepted

  　View Summary

  The rising prominence of RISC-V, despite its inherent lack of multithreading support, has sparked research initiatives to design and implement multithreaded RISC-V processors. In this paper, we present a novel multithreaded RISC-V processor explicitly tailored for real-time systems. Our design allows for dynamic thread manipulation- encompassing creation, execution, halting, deletion, and more- to emulate the behavior of tasks in a real-time operating system’s task queue. We introduce specialized instructions to RISC-V to facilitate these thread control operations. The proposed processor is equipped with eight logical cores, enabling simultaneous execution of up to eight threads. A context cache is integrated to efficiently manage context switches between threads, achieving context switches in four clocks. This feature empowers the processor to concurrently run a greater number of threads than its core count. Simulation results underscore the benefits of our design: multithreaded execution yields an instruction per cycle (IPC) rate that surpasses single-threaded execution by up to 5.5 times. Furthermore, our priority system ensures preferential execution of high-priority threads over their lower-priority counterparts. Consequently, we have realized a multithreaded RISC-V processor capable of prioritized execution across eight threads and concurrent execution beyond its core count.

• Design of Decoded Instruction Cache

  Takero Magara, Nobuyuki Yamasaki

  2023 Eleventh International Symposium on Computing and Networking Workshops (CANDARW)  2024.02

  Accepted

  　View Summary

  Recent microprocessors improve performance by extracting various levels of parallelism. Among these, out-of-order processors focus on ILP to improve performance. On the other hand, out-of-order processors consume a lot of power because they fetch and decode many instructions.We propose a Decoded Instruction Cache (DIC), in which the control signals generated by decoding RISC instructions are stored as decoded instructions in the DIC. The scheme improves performance and reduces power consumption because the results of fetch and decode can be reused. The DIC also supports multi-threaded execution, so TLP is also improved.When implemented in a multithreaded RISC processor, the DIC improves IPC by 2.39%.

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Presentations 【 Display / hide 】

Presentations 【 Display / hide 】

• マルチコア RISC-V プロセッサ用コンテキストキャッシュの設計

  山澤 彪, 伊藤 務, 水頭 一壽, 山﨑 信行

  第248回システム・アーキテクチャ・第205回システムとLSIの設計技術・第65回組込みシステム合同研究発表会（ETNET2024）, 

  2024.03

• リアルタイムシステム向けRISC-V SMTプロセッサの設計

  野尻悠太, 山﨑信行

  第248回システム・アーキテクチャ・第205回システムとLSIの設計技術・第65回組込みシステム合同研究発表会, 

  2024.03

• MTJベースの不揮発性デバイスを用いたノンストッププロセッサ

  中別府 将太, 山﨑 信行

  第248回システム・アーキテクチャ・第205回システムとLSIの設計技術・第65回組込みシステム合同研究発表会, 

  2024.03

• RMTPベースのマルチスレッドRISC-Vプロセッサの設計

  野尻 悠太

  組込み技術とネットワークに関するワークショップ ETNET 2023, 

  2023.03

  , 

  Oral presentation (general)

• Decoded Instruction Cacheの設計

  眞柄 岳郎

  組込み技術とネットワークに関するワークショップ ETNET 2023, 

  2023.03

  , 

  Oral presentation (general)

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Intellectual Property Rights, etc. 【 Display / hide 】

Intellectual Property Rights, etc. 【 Display / hide 】

• Multithreaded central processing unit and simultaneous multithreading control method

  Date applied： PCT出願番号：PCT/JP2006/311022  2006.06 

  Patent

• Context switching method, context switching unit, context switching program, storage medium, and central processing unit

  Date applied： PCT出願番号：PCT/JP03/15838  2005.06 

  Patent

• マルチスレッド中央演算装置および同時マルチスレッディング制御方法

  Date applied： 特願2005-167427  2005.06 

  Patent

• Communications method and communications system

  Date applied： EU特許庁　出願番号:05000821.8  2005.01 

  Date issued： 第1549005号  2009.03

  Patent

• 命令発行方法及び装置、中央演算装置、命令発行プログラム及びそれを記憶したコンピュータ読み取り可能な記憶媒体

  Date applied： 特願2003-83001  2003.03 

  Date announced： 特開2004-295195   

  Date issued： 特許第3646137号  2005.02

  Patent

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Awards 【 Display / hide 】

Awards 【 Display / hide 】

• 日本ロボット学会 研究奨励賞

  YAMASAKI NOBUYUKI, 1998.10, 日本ロボット学会

• FPGA/PLDデザインカンファレンス 優秀論文賞

  YAMASAKI NOBUYUKI, 1999.06

• 日本機械学会ロボティクスメカトロニクス部門 ベストプレゼンテーション賞

  YAMASAKI NOBUYUKI, 2001.06, 日本機械学会ロボティクスメカトロニクス部門

• 日本ロボット学会 論文賞

  YAMASAKI NOBUYUKI, 2002.10, 日本ロボット学会

• 情報処理学会システムLSI設計技術研究会 優秀論文賞

  YAMASAKI NOBUYUKI, 2004.07, 情報処理学会システムLSI設計技術研究会

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Courses Taught 【 Display / hide 】

Courses Taught 【 Display / hide 】

• SYSTEM ON A CHIP DESIGN

  2024

• SPECIAL EXERCISES ON INFORMATION AND COMPUTER SCIENCE

  2024

• RECITATION IN INFORMATION AND COMPUTER SCIENCE

  2024

• PROGRAMMING 3

  2024

• MICROPROCESSOR ARCHITECTURE

  2024

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Courses Previously Taught 【 Display / hide 】

Courses Previously Taught 【 Display / hide 】

• 計算機基礎

  Keio University

  2014.04

  -

  2015.03

  , 

  Spring Semester

• マイクロプロセッサ特論

  Keio University

  2014.04

  -

  2015.03

  , 

  Autumn Semester

• 組込みリアルタイムシステム

  Keio University

  2014.04

  -

  2015.03

  , 

  Autumn Semester

• プログラミング第3同演習

  Keio University

  2014.04

  -

  2015.03

  , 

  Autumn Semester

• System-on-a-Chip 設計技術

  Keio University

  2014.04

  -

  2015.03

  , 

  Spring Semester

Memberships in Academic Societies 【 Display / hide 】

Memberships in Academic Societies 【 Display / hide 】

• Information Processing Society of Japan, 

  1993

  -

  Present

• The Robotics Society of Japan

  　

• The Institute of Electronics, Information and Communication Engineers

  　

• IEEE Institute of Electrical and Electonic Engineers

  　

Committee Experiences 【 Display / hide 】

Committee Experiences 【 Display / hide 】

• 1993

  -

  Present

  Member, Information Processing Society of Japan

• 　

  会員, IEEE Institute of Electrical and Electonic Engineers

• 　

  会員, 日本ロボット学会

• 　

  会員, 電子情報通信学会

• 　

  Member, IEEE Institute of Electrical and Electonic Engineers

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