Details of a Researcher - Yamasaki Nobuyuki

Yamasaki Nobuyuki

写真a

Affiliation: Faculty of Science and Technology, Department of Information and Computer Science （Yagami）

Position: Professor

Related Websites

山﨑研究室ホームページ

External Links

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Career 【 Display / hide 】

1996.04

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1998.09

通商産業省工業技術院電子技術総合研究所
1997.10

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2000.09

科学技術振興事業団さきがけ研究21 研究員
1998.10

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2000.03

大学助手(有期)(理工学部情報工学科)
1998.10

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2002.03

電子技術総合研究所 COE特別研究員
2000.04

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2004.03

大学専任講師(理工学部情報工学科)

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Academic Background 【 Display / hide 】

1991.03

Keio University, Faculty of Science and Technology, Physics

University, Graduated
1996.03

Keio University, Graduate School, Division of Science and Engineeri

Graduate School, Completed, Doctoral course

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Academic Degrees 【 Display / hide 】

工学　, Keio University, 1996.03

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Research Areas 【 Display / hide 】

Informatics / Computer system (Computer System Network)
Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Communication and network engineering (Communication/Network Engineering)
Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment (Electronic Device/Electronic Equipment)
Informatics / Software (ソフトウエア)
Informatics / Mechanics and mechatronics (Intelligent Mechanics/Mechanical System)

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Research Keywords 【 Display / hide 】

Operating System
System LSI
Processor Architecture
Real-Time Communication
Robot

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Books 【 Display / hide 】

電気学会誌

YAMASAKI NOBUYUKI, 2007.03

Scope: 156-160
日本ロボット学会新版ロボット工学ハンドブック基礎編

山﨑信行、他, 日本ロボット学会新版ロボット工学ハンドブック基礎編, 2005

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表記題名についてハンドブックへの解説を行う。
バーチャルリアリティとテレロボティクス，アクティブインタフェースとパーソナルロボット

山﨑信行、他, 情報処理学会　新版情報処理ハンドブック, 1995

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表記題名についてハンドブックへの解説を行う。
オブジェクト指向コンピューティングI

YAMASAKI NOBUYUKI, 1993.07
リアルタイム処理システム

山﨑信行、他, 日本機会学会機械工学便覧基礎編

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表記題名について便覧への解説を行う。

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Papers 【 Display / hide 】

Real-Time Execution based on Fluid Scheduling by using IPC Control Scheme

Santo A., Yamasaki N.

Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 （Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021) 459 - 463 2021

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Fluid scheduling is an optimal real-time scheduling applicable to multiprocessor systems and is a scheduling model so that every real-time task is executed at a constant speed from release time to deadline. It is necessary for fluid scheduling to control the execution speed of each task. But, since the execution speed of the task is invariable in a conventional general purpose processor. Therefore, fluid scheduling is conventionally achieved by repeatedly executing and stopping tasks. However, this method incurs significant overheads due to frequent task switching. On the other hand, fluid scheduling without overhead by using an IPC control scheme has been proposed. The IPC control scheme controls the execution speed of each thread in an SMT processor. We propose a new IPC control scheme to extract thread-level parallelism and improve throughput effectively, also improving the schedulability of the fluid schedule. The evaluation results show that the proposed method improved the total throughput of the fluid schedule.
- Access to Document (DOI)
Data Rearrange Unit for Efficient Data Computation in Embedded Systems

Mamiya A., Yamasaki N.

Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 （Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021) 101 - 106 2021

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Recently demands for computation intensive applications such as convolutional neural networks (CNNs) have been increasing. In these applications, valid data for computation are allocated in non-continuous addresses. Therefore, common burst memory access pattern results in a low spatial locality of valid data per access. As a result, computation of data parallel execution units degrades in throughput, as computation resource is wasted by computing invalid data. This is especially a problem in embedded systems in which constraints in power consumption provoke a requirement for high computation efficiency. In this paper, we introduce a Data Rearrange Unit (DRU), a hardware unit rearranging computation data to increase spatial locality of valid data. The DRU drastically reduces the main memory access rate and increases computation efficiency by decreasing memory access to reduce power consumption. We demonstrate the effectiveness of our DRU by implementation on the RMTP SoC [1] [2] improving convolution throughput on a data parallel execution unit by a maximum of 94times, while only increasing the total cell area by about 13%.
- Access to Document (DOI)
A Learning-based Fetch Thread Gating Mechanism for A Simultaneous Multithreading Processor

Ide Y., Yamasaki N.

Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020 （Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020) 19 - 28 2020.11

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Simultaneous Multithreading (SMT) technology is widely adopted in modern high-end processors to maximize on-chip hardware utilization. In an SMT processor, multiple threads are executed in parallel, sharing hardware resources. This technique aggregates potential efficiency which will not be available in a single thread processor. However, when a data cache miss or a branch prediction miss occurs, every thread competing for hardware resources causes the degradation of hardware utilization. Therefore, instruction fetch policies have been proposed to manage hardware resources efficiently in SMT processors. The fetch policies distribute hardware resources indirectly, through fetch bandwidth control. Conventionally, a fetch policy selects fetch threads based only on the resource usage at the moment, while the characteristics of threads are not exploited on decision. Therefore most conventional fetch control schemes only take effects only after an outstanding event occurs. Capability of resource restriction is limited even with an aggressive fetch control scheme. In this paper, we propose a Fetch Gate Estimator (FGE) that is a fetch gating mechanism based on machine learning, which is implemented as a hardware module. The FGE evaluates each thread to decide whether an instruction fetch from a thread should be gated. The FGE is trained dynamically by the execution statistics resulted from the inferences, so that characteristics of each thread are encoded into a learning model. Thus, the FGE is trained dynamically in parallel with execution of programs. We applied a single layer perceptron as learning model inside the FGE for circuit simplicity, and investigated performance impacts. Evaluation results show that the perceptron-based FGE can train itself from acquired execution statistics to identify inefficient threads adaptively, adjusting resources through the fetch gate control mechanism.
- Access to Document (DOI)
Codeword set selection for the error-correcting 4b/10b line code with maximum clique enumeration

Takeda M., Yamasaki N.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences （IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences) E103A （ 10 ） 1227 - 1233 2020.10

ISSN 09168508

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This paper addresses the problem of finding, evaluating, and selecting the best set of codewords for the 4b/10b line code, a dependable line code with forward error correction (FEC) designed for real-time communication. Based on the results of our scheme [1], we formulate codeword search as an instance of the maximum clique problem, and enumerate all candidate codeword sets via maximum clique enumeration as proposed by Eblen et al. [2]. We then measure each set in terms of resistance to bit errors caused by noise and present a canonical set of codewords for the 4b/10b line code. Additionally, we show that maximum clique enumeration is #P-hard.
- Access to Document (DOI)
Space Responsive Multithreaded Processor (SRMTP) for Spacecraft Control

Nakabeppu S., Ide Y., Takahashi M., Tsukahara Y., Suzuki H., Shishido H., Yamasaki N.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings （IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings) 2020.04

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A spacecraft control system is often designed as a distributed real-time system that consists of processors with required functions along with peripheral devices including sensors and actuators. The system must operate under real-time constraints and be maximally dependable. In this paper, we design and implement Space Responsive Multithreaded Processor (SRMTP) System-on-Chip (SoC) and System-in-Package (SiP) for spacecraft control.
- Access to Document (DOI)

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Presentations 【 Display / hide 】

RMTPベースのマルチスレッドRISC-Vプロセッサの設計

野尻悠太

組込み技術とネットワークに関するワークショップ ETNET 2023,

2023.03
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Oral presentation (general)
Decoded Instruction Cacheの設計

眞柄岳郎

組込み技術とネットワークに関するワークショップ ETNET 2023,

2023.03
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Oral presentation (general)
Fluidスケジューリングを用いた高効率なMixed Criticalityスケジューリング

八島幸祐

組込み技術とネットワークに関するワークショップ ETNET 2022,

2022.03
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Oral presentation (general)
SMT Processor用Imprecise Mixed Criticalityスケジューリング

名倉怜央

組込み技術とネットワークに関するワークショップ ETNET 2022,

2022.03
,
Oral presentation (general)
RMT Processor用Hypervisor RMTvisorの設計

牧野真成

組込み技術とネットワークに関するワークショップ ETNET 2022,

2022.03
,
Oral presentation (general)

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Intellectual Property Rights, etc. 【 Display / hide 】

Multithreaded central processing unit and simultaneous multithreading control method

Date applied： PCT出願番号：PCT/JP2006/311022 2006.06

Patent
Context switching method, context switching unit, context switching program, storage medium, and central processing unit

Date applied： PCT出願番号：PCT/JP03/15838 2005.06

Patent
マルチスレッド中央演算装置および同時マルチスレッディング制御方法

Date applied：特願2005-167427 2005.06

Patent
Communications method and communications system

Date applied： EU特許庁　出願番号:05000821.8 2005.01

Date issued：第1549005号 2009.03

Patent
命令発行方法及び装置、中央演算装置、命令発行プログラム及びそれを記憶したコンピュータ読み取り可能な記憶媒体

Date applied：特願2003-83001 2003.03

Date announced：特開2004-295195

Date issued：特許第3646137号 2005.02

Patent

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Awards 【 Display / hide 】

日本ロボット学会研究奨励賞

YAMASAKI NOBUYUKI, 1998.10, 日本ロボット学会
FPGA/PLDデザインカンファレンス優秀論文賞

YAMASAKI NOBUYUKI, 1999.06
日本機械学会ロボティクスメカトロニクス部門ベストプレゼンテーション賞

YAMASAKI NOBUYUKI, 2001.06, 日本機械学会ロボティクスメカトロニクス部門
日本ロボット学会論文賞

YAMASAKI NOBUYUKI, 2002.10, 日本ロボット学会
情報処理学会システムLSI設計技術研究会優秀論文賞

YAMASAKI NOBUYUKI, 2004.07, 情報処理学会システムLSI設計技術研究会