論文 - 松谷　宏紀

Adaptive body bias control scheme for ultra low-power network-on-chip systems

Ben Ahmed A., Okuhara H., Matsutani H., Koibuchi M., Amano H.

Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018 （Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018）     146 - 153 2018年11月

ISSN  9781538666890

　概要を見る

Over the past decade, the power consumption has been one of the main design challenges in Network-on-Chips (NoCs) as it significantly defines the performance of a given Chip-Multiprocessor (CMP). Body bias control is one of the solutions that provide an efficient trade-off between leakage power and performance. However, employing such a method is not straightforward since several factors should be taken into consideration, especially when adaptively implemented on-chip. In this paper, we propose a new router design and on-chip body bias control mechanism to adaptively control the body bias voltages supply in ultra low-power NoC systems. With the help of a light-weight monitoring circuit, the proposed router predicts the traffic load at each input-port and accordingly adjusts its pipeline depth in a fine-grained fashion. To satisfy the timing constraints, the router adaptively supplies each one of its input-ports with the appropriate body bias voltages to either boost the performance or to reduce the leakage power at the standby state. The evaluation results, using the SOTB 65nm Fully Depleted Silicon On Insulator (FD-SOI) technology, shows the ability of the proposed router in reducing both dynamic and static energies. When compared to two fixed-pipeline baseline routers (3-stages and 2-stages), the total energy reduction could reach up to 67% and 59%, respectively. At the same time, a reasonable performance tendency can be obtained with less than 6% area overhead.

• Access to Document (DOI)

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Ahmed A.B., Fujiki D., Matsutani H., Koibuchi M., Amano H.

2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018 （2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018）     1 - 8 2018年10月

研究論文（国際会議プロシーディングス）, 共著, 査読有り,  ISSN  9781538648933

　概要を見る

Various parallel applications, such as numerical convergent computation and multimedia processing, have intrinsic tolerance to inaccuracies that allow soft errors, i.e. bit flips, on a chip. However, existing Network-on-Chips (NoCs) guarantee error-free data transfer; thus, encountering limits to reduce the power consumption. In this context, we propose an approximate dual-voltage NoC, called AxNoC. An AxNoC router uses a per-flit look-ahead power management so that headers and important-data flits are perfectly transferred at a high voltage while the remaining flits may incur bit flips by decreasing the supply voltage. An AxNoC router isolates the critical path when the supply voltage is low since such a critical path is enabled only at high voltage. The critical path isolation enables low-voltage operation to work at the same operating frequency at high voltage. An AxNoC router was implemented using a 28nm process and the evaluation results illustrate its efficiency to reduce the power consumption reaching up to 43% while incurring a small area overhead that does not exceed 6.2%. We also demonstrate that AxNoC exhibits an acceptable accuracy illustrated in a sufficiently small geomean of error.

• Access to Document (DOI)

Proxy responses by FPGA-based switch for MapReduce stragglers

Mitsuzuka K., Koibuchi M., Amano H., Matsutani H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems）  E101D （ 9 ） 2258 - 2268 2018年09月

ISSN  09168532

　概要を見る

In parallel processing applications, a few worker nodes called "stragglers", which execute their tasks significantly slower than other tasks, increase the execution time of the job. In this paper, we propose a network switch based straggler handling system to mitigate the burden of the compute nodes. We also propose how to offload detecting stragglers and computing their results in the network switch with no additional communications between worker nodes. We introduce some approximate techniques for the proxy computation and response at the switch; thus our switch is called "ApproxSW." As a result of a simulation experiment, the proposed approximation based on task similarity achieves the best accuracy in terms of quality of generated Map outputs. We also analyze how to suppress unnecessary proxy computation by the ApproxSW. We implement ApproxSW on NetFPGA-SUME board that has four 10Gbit Ethernet (10GbE) interfaces and a Virtex-7 FPGA. Experimental results shows that the ApproxSW functions do not degrade the original 10GbE switch performance.

• Access to Document (DOI)

Accelerating Blockchain Search of Full Nodes Using GPUs

Morishima S., Matsutani H.

Proceedings - 26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2018 （Proceedings - 26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2018）     244 - 248 2018年06月

ISSN  9781538649756

　概要を見る

Blockchain is a distributed ledger system based on P2P network and originally used for a crypto currency system. The P2P network of Blockchain is maintained by full nodes which are in charge of verifying all the transactions in the network. However, most Blockchain user nodes do not act as full nodes, because workload of full nodes is quite high for personal mobile devices. Blockchain search queries, such as confirming balance, transaction contents, and transaction histories, from many users go to the full nodes. As a result, search throughput of full nodes would be a new bottleneck of Blockchain system, because the number of full nodes is less than the number of users of Blockchain systems. In this paper, we propose an acceleration method of Blockchain search using GPUs. More specifically, we introduce an array-based Patricia tree structure suitable for GPU processing so that we can make effective use of Blockchain feature that there are no update and delete queries. In the evaluations, the proposed method is compared with an existing GPU-based key-value search and a conventional CPU-based search in terms of the throughput of Blockchain key search. As a result, the throughput of our proposal is 3.4 times higher than that of the existing GPU-based search and 14.1 times higher than that of the CPU search when the number of keys is 80 ×220 and the key length is 256-bit in Blockchain search queries.

• Access to Document (DOI)

Special session on bringing cores closer together: The wireless revolution in on-chip communication

Mak T., Matsutani H., Pande P.P.

Proceedings of the IEEE VLSI Test Symposium （Proceedings of the IEEE VLSI Test Symposium）  2018-April 2018年05月

ISSN  9781538637746

　概要を見る

The emerging field of NoC with Wireless interconnects is actively being pursued by a number of researchers worldwide, from a variety of different perspectives, ranging from very high levels of abstraction (e.g., system architecture) to very low levels (physical layer and transceiver design). Successful solutions will likely adopt and encompass elements from all or at least several levels of abstraction and rely on interdisciplinary concepts from multi-core architectures, integrated circuits, 3D ICs, digital communications, complex networks, and optimization techniques. This special session will provide a timely and insightful journey into various challenges and emerging solutions regarding the design of future NoC architectures. By scope and contents, this special session represents an engaging proposition to attendees belonging to both academia and industry.

• Access to Document (DOI)

Building block multi-chip systems using inductive coupling through chip interface

Amano H., Kuroda T., Nakamura H., Usami K., Kondo M., Matsutani H., Namiki M.

Proceedings - International SoC Design Conference 2017, ISOCC 2017 （Proceedings - International SoC Design Conference 2017, ISOCC 2017）     152 - 154 2018年05月

ISSN  9781538622858

　概要を見る

A building block computing system is consisting of multiple chips connecting with inductive coupling wireless through chip interconnect. Like building Lego blocks, various types of systems can be built by stacking different types of chips. In order to develop such systems, several techniques are investigated in the project: that is, inductive coupling wireless through chip interface, low power circuit technologies, autonomous interconnection network architectures, thermal dissipation and building block operating system. Here, the overview of the project and a prototype system are introduced.

• Access to Document (DOI)

A hardware-based caching system on FPGA NIC for Blockchain

Sakakibara Y., Morishima S., Nakamura K., Matsutani H.

IEICE Transactions on Information and Systems （IEICE Transactions on Information and Systems）  E101D （ 5 ） 1350 - 1360 2018年05月

ISSN  09168532

　概要を見る

Engineers and researchers have recently paid attention to Blockchain. Blockchain is a fault-tolerant distributed ledger without administrators. Blockchain is originally derived from cryptocurrency, but it is possible to be applied to other industries. Transferring digital asset is called a transaction. Blockchain holds all transactions, so the total amount of Blockchain data will increase as time proceeds. On the other hand, the number of Internet of Things (IoT) products has been increasing. It is difficult for IoT products to hold all Blockchain data because of their storage capacity. Therefore, they access Blockchain data via servers that have Blockchain data. However, if a lot of IoT products access Blockchain network via servers, server overloads will occur. Thus, it is useful to reduce workloads and improve throughput. In this paper, we propose a caching technique using a Field Programmable Gate Array-based (FPGA) Network Interface Card (NIC) which possesses four 10Gigabit Ethernet (10GbE) interfaces. The proposed system can reduce server overloads, because the FPGA NIC instead of the server responds to requests from IoT products if cache hits. We implemented the proposed hardware cache to achieve high throughput on NetFPGA-10G board. We counted the number of requests that the server or the FPGA NIC processed as an evaluation. As a result, the throughput improved by on average 1.97 times when hitting the cache.

• Access to Document (DOI)

High-Performance with an In-GPU Graph Database Cache

Shin Morishima, Hiroki Matsutani

IEEE IT Professional 19 （ 6 ） 58 - 64 2017年12月

研究論文（学術雑誌）, 共著, 査読有り

HiRy: An advanced theory on design of deadlock-free adaptive routing for arbitrary topologies

Kawano R., Yasudo R., Matsutani H., Koibuchi M., Amano H.

Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS （Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS）  2017-December   664 - 673 2017年12月

研究論文（国際会議プロシーディングス）, 共著, 査読有り,  ISSN  9781538621295

　概要を見る

Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve the performance of parallel application. However, these networks usually suffer from deadlocks in routing packets when using a naive minimal path routing algorithm. To solve this problem, we focus attention on a lately proposed theory that generalizes the turn model to maintain the network performance with deadlock-freedom. The theorems remain a challenge of applying themselves to arbitrary topologies including fully irregular networks. In this paper, we advance the theorems to completely general ones. To apply the idea of the turn model to arbitrary topologies, we introduce a concept of regions that define continuous directions of channels on an n-dimensional space. Moreover, we provide a feasible implementation of a deadlock-free routing method based on our advanced theorem. To reduce the latency and the number of required Virtual Channels (VCs) with this method, a heuristic approach is introduced to reduce the number of prohibited turns between channels. Experimental results show that the routing method based on our proposed theorem can improve the network throughput by up to 138 % compared to a conventional deterministic minimal routing method. Moreover, it can reduce the latency by up to 2.9 % compared to another fully adaptive routing method.

• Access to Document (DOI)

Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches

Yuta Tokusashi, Hiroki Matsutani

IEEE Micro 37 （ 5 ） 44 - 51 2017年10月

研究論文（学術雑誌）, 共著, 査読有り

A Case for Uni-Directional Network Topologies in Large-Scale Clusters

Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova

International Conference on Cluster Computing (Cluster'17)    178 - 187 2017年09月

研究論文（国際会議プロシーディングス）, 共著, 査読有り

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano

International Conference on Parallel Processing (ICPP'17)    322 - 331 2017年08月

研究論文（国際会議プロシーディングス）, 共著, 査読有り

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

IEEE Transactions on Computers (TC) 66 （ 4 ） 702 - 716 2017年04月

研究論文（学術雑誌）, 共著, 査読有り

An FPGA-Based In-NIC Cache Approach for Lazy Learning Outlier Filtering

Ami Hayashi, Hiroki Matsutani

International Conference on Parallel, Distributed, and Network-Based Processing (PDP'17)    15 - 22 2017年03月

研究論文（国際会議プロシーディングス）, 共著, 査読有り

High-Bandwidth Low-Latency Approximate Interconnection Networks

Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi

IEEE International Symposium on High-Performance Computer Architecture (HPCA'17)    469 - 480 2017年02月

研究論文（国際会議プロシーディングス）, 共著, 査読有り

Accelerating Spark RDD Operations with Local and Remote GPU Devices

Yasuhiro Ohno, Shin Morishima, Hiroki Matsutani

International Conference on Parallel and Distributed Systems (ICPADS'16)    791 - 799 2016年12月

研究論文（国際会議プロシーディングス）, 共著, 査読有り

Randomly Optimized Grid Graph for Low-Latency Interconnection Networks

Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi

International Conference on Parallel Processing (ICPP'16)    340 - 349 2016年08月

研究論文（国際会議プロシーディングス）, 共著, 査読有り

A Multilevel NOSQL Cache Design Combining In-NIC and In-Kernel Caches

Yuta Tokusashi, Hiroki Matsutani

IEEE International Symposium on High Performance Interconnects (Hot Interconnects 24)    60 - 67 2016年08月

研究論文（国際会議プロシーディングス）, 共著, 査読有り

Randomizing Packet Memory Networks for Low-latency Processor-memory Communication

Daichi Fujiki, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi

International Conference on Parallel, Distributed, and Network-Based Processing (PDP'16)    168 - 175 2016年02月

研究論文（国際会議プロシーディングス）, 共著, 査読有り

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano

IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 24 （ 2 ） 493 - 506 2016年02月

研究論文（学術雑誌）, 共著, 査読有り