Matsutani, Hiroki

写真a

Affiliation

Faculty of Science and Technology, Department of Information and Computer Science (Yagami)

Position

Professor

Related Websites

Profile 【 Display / hide

  • Hiroki Matsutani received the BA, ME, and PhD degrees from Keio University in 2004, 2006, and 2008, respectively. From 2009 to 2010, he was a research fellow in the Graduate School of Information Science and Technology, The University of Tokyo, and awarded Research Fellowship of Japan Society for the Promotion of Science (JSPS) for Young Scientists (SPD). From 2011 to 2016, he was an assistant professor in the Department of Information and Computer Science, Keio University. From 2017 to 2022, he was an associate professor, and he is currently a professor in the same department. His research interests include the areas of computer architecture, machine learning, and big data processing.

Career 【 Display / hide

  • 2006.04
    -
    2008.03

    Japan Society for the Promotion of Science, Research Fellow DC1

  • 2008.04
    -
    2009.03

    Japan Society for the Promotion of Science, Research Fellow PD

  • 2009.04
    -
    2011.03

    Japan Society for the Promotion of Science, Research Fellow SPD

  • 2009.04
    -
    2011.03

    The University of Tokyo, Graduate School of Information Science and Technology, Research Fellow

  • 2011.04
    -
    2017.03

    Keio University, Faculty of Science and Technology, Assistant Professor

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Academic Background 【 Display / hide

  • 2000.04
    -
    2004.03

    Keio University, Faculty of Environment and Information Studies, Department of Environment and Information Studies

    University, Graduated

  • 2004.04
    -
    2006.03

    Keio University, Graduate School of Science and Technology, School of Science for Open and Environmental Systems

    Graduate School, Completed, Master's course

  • 2006.04
    -
    2008.03

    Keio University, Graduate School of Science and Technology, School of Science for Open and Environmental Systems

    Graduate School, Completed, Doctoral course

Academic Degrees 【 Display / hide

  • B.A. degree in Environmental Information, Keio University, Coursework, 2004.03

  • M.E. degree in Engineering, Keio University, Coursework, 2006.03

  • Ph.D. degree in Engineering, Keio University, Coursework, 2008.03

 

Research Areas 【 Display / hide

  • Informatics / Computer system

  • Informatics / Information network

Research Keywords 【 Display / hide

  • Computer architecture

  • Machine learning

  • Computer network

  • Big data

Research Themes 【 Display / hide

  • On-device learning, 

    2017.04
    -
    Present

 

Books 【 Display / hide

  • 3D Integration for NoC-based SoC Architectures

    Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, Springer, 2010.12

    Scope: Chapter 10: 3-D NoC on Inductive Wireless Interconnect

  • Low Power Networks-on-Chip

    Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano, Springer, 2010.10

    Scope: Chapter 2: Run-Time Power-Gating Techniques for Low-Power On-Chip Networks

  • Networks-on-Chips: Theory and Practice

    Michihiro Koibuchi, Hiroki Matsutani, CRC Press, 2009.03

    Scope: Chapter 3: Networks-on-Chip Protocols

Papers 【 Display / hide

  • A traffic-aware memory-cube network using bypassing

    Shikama Y., Kawano R., Matsutani H., Amano H., Nagasaka Y., Fukumoto N., Koibuchi M.

    Microprocessors and Microsystems (Microprocessors and Microsystems)  90 2022.04

    ISSN  01419331

     View Summary

    Three-dimensional stack memory which provides both high-bandwidth access and large capacity is a promising technology for next-generation computer systems. While a large number of memory cubes increase the aggregate memory capacity, the communication latency and power consumption increase significantly owing to its low-radix large-diameter packet network. In this context, we propose a memory-cube network called Diagonal Memory Network (DMN). A diagonal network topology, its floor layout, and its lightweight router were designed for low-latency and low-voltage memory-read communication. DMN routing efficiently avoids deadlocks of packets, although it allows each packet transmitted to a processor to use both bypassing and original datapaths. Our evaluation results show that the DMN router decreases the use of hardware resources by more than 31% compared with a conventional virtual channel router. The DMN router reduces energy consumption by 13% and 67% to transit a packet along with the original datapath and bypassing datapath, respectively. Furthermore, using flit-level discrete event simulation, a DMN topology achieves high throughput and latency that is lower than that of existing network topologies using conventional packet routers.

  • An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit

    Tsukada M., Matsutani H.

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences)  105 ( 3 ) 437 - 447 2022

    ISSN  09168508

     View Summary

    Currently there has been increasing demand for real-time training on resource-limited IoT devices such as smart sensors, which realizes standalone online adaptation for streaming data without data transfers to remote servers. OS-ELM (Online Sequential Extreme Learning Machine) has been one of promising neural-network-based online algorithms for on-chip learning because it can perform online training at low computational cost and is easy to implement as a digital circuit. Existing OS-ELM digital circuits employ fixed-point data format and the bit-widths are often manually tuned, however, this may cause overflow or underflow which can lead to unexpected behavior of the circuit. For on-chip learning systems, an overflow/underflow-free design has a great impact since online training is continuously performed and the intervals of intermediate variables will dynamically change as time goes by. In this paper, we propose an overflow/underflow-free bit-width optimization method for fixed-point digital circuits of OS-ELM. Experimental results show that our method realizes overflow/underflow-free OS-ELM digital circuits with 1.0x - 1.5x more area cost compared to the baseline simulation method where overflow or underflow can happen.

  • GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph

    Kawano R., Matsutani H., Koibuchi M., Amano H.

    ACM International Conference Proceeding Series (ACM International Conference Proceeding Series)     51 - 55 2021.06

     View Summary

    The design of the network topology of a large-scale parallel computer system can be represented as an order/degree problem in the graph theory. To solve the order/degree problem, we have to obtain all-pairs-shortest-path (APSP) for the graph. A conventional APSP algorithm for GPUs is based on the adjacency matrix (ADJ-APSP). When focusing on low-degree and unweighted graphs, most of the matrix elements are zero in the first few iterations of the algorithm. We will further speed up the APSP algorithm by treating the adjacency matrix as a sparse matrix in the first iterations of the algorithm. Evaluation results show that our proposed algorithm on a single GPU (NVIDIA GeForce RTX 3080) reduces the execution time by up to 32.7 % compared to the conventional algorithm.

  • An area-efficient recurrent neural network core for unsupervised time-series anomaly detection

    SAKUMA T., MATSUTANI H.

    IEICE Transactions on Electronics (IEICE Transactions on Electronics)  1 ( 6 ) 247 - 256 2021.06

    ISSN  09168524

     View Summary

    Since most sensor data depend on each other, time-series anomaly detection is one of practical applications of IoT devices. Such tasks are handled by Recurrent Neural Networks (RNNs) with a feedback structure, such as Long Short Term Memory. However, their learning phase based on Stochastic Gradient Descent (SGD) is computationally expensive for such edge devices. This issue is addressed by executing their learning on high-performance server machines, but it introduces a communication overhead and additional power consumption. On the other hand, Recursive Least-Squares Echo State Network (RLS-ESN) is a simple RNN that can be trained at low cost using the least-squares method rather than SGD. In this paper, we propose its area-efficient hardware implementation for edge devices and adapt it to human activity anomaly detection as an example of interdependent time-series sensor data. The model is implemented in Verilog HDL, synthesized with a 45 nm process technology, and evaluated in terms of the anomaly capability, hardware amount, and performance. The evaluation results demonstrate that the RLS-ESN core with a feedback structure is more robust to hyper parameters than an existing Online Sequential Extreme Learning Machine (OS-ELM) core. It consumes only 1.25 times larger hardware amount and 1.11 times longer latency than the existing OS-ELM core.

  • Accelerating ODE-Based Neural Networks on Low-Cost FPGAs

    Watanabe H., Matsutani H.

    2021 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2021 - In conjunction with IEEE IPDPS 2021 (2021 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2021 - In conjunction with IEEE IPDPS 2021)     88 - 95 2021.06

    ISSN  9781665435772

     View Summary

    ODENet is a deep neural network architecture in which a stacking structure of ResNet is implemented with an ordinary differential equation (ODE) solver. It can reduce the number of parameters and strike a balance between accuracy and performance by selecting a proper solver. It is also possible to improve the accuracy while keeping the same number of parameters on resource-limited edge devices. In this paper, using Euler method as an ODE solver, a part of ODENet is implemented as a dedicated logic on a low-cost FPGA (Field-Programmable Gate Array) board, such as PYNQ-Z2 board. As ODENet variants, reduced ODENets (rODENets) each of which heavily uses a part of ODENet layers and reduces/eliminates some layers differently are proposed and analyzed for low-cost FPGA implementation. They are evaluated in terms of parameter size, accuracy, execution time, and resource utilization on the FPGA. The results show that an overall execution time of an rODENet variant is improved by up to 2.66 times compared to a pure software execution while keeping a comparable accuracy to the original ODENet.

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Papers, etc., Registered in KOARA 【 Display / hide

Reviews, Commentaries, etc. 【 Display / hide

  • Recent Trends in Computing Infrastructure for Utilizing Big Data

    Hiroki Matsutani

    The Journal of IEICE 100 ( 8 ) 866 - 870 2017.08

    Article, review, commentary, editorial, etc. (scientific journal), Single Work

Presentations 【 Display / hide

  • An On-Device Learning Approach for Unsupervised Anomaly Detection

    Hiroki Matsutani

    International Forum on MPSoC for Software-defined Hardware (MPSoC'19), 

    2019.07

    Oral presentation (invited, special)

  • An On-Device Unsupervised Anomaly Detection Core and Its Applications

    Hiroki Matsutani

    LSI and System Workshop 2019, 

    2019.05

    Oral presentation (invited, special)

  • An Online Sequential Learning and Unsupervised Anomaly Detection and Its Applications

    Hiroki Matsutani

    IPSJ SIG-ARC meeting (Dec 2018), 

    2018.12

    Oral presentation (invited, special)

  • An Environmentally Adaptive Anomaly Detection Method for Edge Devices

    Hiroki Matsutani

    International Symposium on Computing and Networking (CANDAR'18) Workshop, 

    2018.11

    Oral presentation (invited, special)

  • An Environmentally Adaptive Anomaly Detection Using Edge Learning and Its Applications

    Hiroki Matsutani

    Design Solution Forum 2018, 

    2018.09

    Oral presentation (invited, special)

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Research Projects of Competitive Funds, etc. 【 Display / hide

  • An Edge Learning Infrastructure Supporting Realtime and All-Data Capabilities

    2017.10
    -
    2020.03

    Japan Science and Technology Agency, -, Hiroki Matsutani, Commissioned research, Principal investigator

  • A Reconfigurable Database Platform for Integrating Various Structured Storages

    2013.10
    -
    2017.03

    Japan Science and Technology Agency, Precursory Research for Embryonic Science and Technology, Hiroki Matsutani, Commissioned research, Principal investigator

  • Optimization on Wireless 3D Network-on-Chips

    2011.10
    -
    2013.03

    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research, Hiroki Matsutani, Research grant, Principal investigator

Awards 【 Display / hide

  • IPSJ Microsoft Informatics Research Award

    Hiroki Matsutani, 2018.03

    Type of Award: Award from Japanese society, conference, symposium, etc.

  • ACM Recognition of Service Award

    Hiroki Matsutani, 2018.01

    Type of Award: International academic award (Japan or overseas)

  • IEICE ISS Volunteer Review Service Award

    Hiroki Matsutani, 2017.06

    Type of Award: Award from Japanese society, conference, symposium, etc.

  • Best Paper Award, International Symposium on Computing and Networking (CANDAR'16)

    Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, 2016.11, LOREN: A Scalable Routing Method for Layout-conscious Random Topologies

    Type of Award: International academic award (Japan or overseas)

  • IPSJ Specially Selected Paper

    Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani, 2016.08, A Nonparametric Online Outlier Detector for FPGA NICs

    Type of Award: Award from Japanese society, conference, symposium, etc.

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Courses Taught 【 Display / hide

  • VLSI DESIGN EXERCISES

    2022

  • RECITATION IN INFORMATION AND COMPUTER SCIENCE

    2022

  • LABORATORIES IN INFORMATION AND COMPUTER SCIENCE 2

    2022

  • INDEPENDENT STUDY ON SCIENCE FOR OPEN AND ENVIRONMENTAL SYSTEMS

    2022

  • GRADUATE RESEARCH ON SCIENCE FOR OPEN AND ENVIRONMENTAL SYSTEMS 2

    2022

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Courses Previously Taught 【 Display / hide

  • Basic of Computer

    Keio University

    2018.04
    -
    2019.03

    Spring Semester, Lecture, Within own faculty, 1h

  • Advanced Course on Distributed Systems

    Keio University

    2018.04
    -
    2019.03

    Autumn Semester, Lecture, Within own faculty, 1h

  • VLSI Design Exercises

    Keio University

    2018.04
    -
    2019.03

    Spring Semester, Seminar, Within own faculty, 1h

  • Laboratories in Information and Computer Science 2

    Keio University

    2018.04
    -
    2019.03

    Autumn Semester, Laboratory work/practical work/exercise, Lecturer outside of Keio, 4h

  • Computer Algorithm II

    Keio University

    2018.04
    -
    2019.03

    Spring Semester, Lecture, Within own faculty, 1h

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Educational Activities and Special Notes 【 Display / hide

  • Digital VLSI Design using Open Cell Library, IEICE Society Conference 2014, Tutorial

    2014.09

    , Lecture at Education Method and Practice

 

Memberships in Academic Societies 【 Display / hide

  • IEEE

     
  • Institute of Electronics, Information and Communication Engineers

     
  • Information Processing Society of Japan

     

Committee Experiences 【 Display / hide

  • 2019.08
    -
    Present

    Technical program committee, International Conference on Parallel Processing (ICPP)

  • 2019.07

    Organizing committee (Local organization chair), International Forum on MPSoC for Software-defined Hardware (MPSoC)

  • 2018.10

    ACM Student Research Competition selection committee, International Symposium on Microarchitecture (MICRO)

  • 2018.04
    -
    Present

    Organizing committee (Secretary), IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips)

  • 2018.02

    Guest editor, IEICE Transactions on Information and Systems, Special Section on Reconfigurable Systems

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