Papers - Nishi, Hiroaki

ハイパフォーマンスルータアーキテクチャに関する研究

NISHI HIROAKI

慶應義塾大学大学院理工学研究科 博士学位論文  2000.12

Research paper (other academic), Single Work

64-Gb/s highly reliable network switch (RHiNET-2/SW) using parallel optical interconnection

Shinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Junji Yamamoto, Katsuyoshi Harasawa, Nobuhiro Matsudaira, Shigeto Akutsu, Hideharu Amano

Journal of Lightwave Technology 18 ( 12 ) 1620 - 1627 2000.12

Accepted,  ISSN  0733-8724

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RHiNET-2/SW is a network switch that enables high-performance optical network-based parallel computing system in a distributed environment. The switch used in such a computing system must provide high-speed, low-latency packet switching with high reliability. Our switch allows high-speed 8-Gb/s/port optical data transmission over a distance of up to 100 m, and the aggregate throughput is 64 Gb/s. In RHiNET-2/SW, eight pairs of 800 -Mb/s × 12-channel optical interconnection modules and a one-chip CMOS ASIC switch LSI (a 784-pin BGA package) are mounted on a single compact board. To enable high-performance parallel computing, this switch must provide high-speed, highly reliable node-to-node data transmission. To evaluate the reliability of the switch, we measured the bit error rate (BER) and skew between the data channels. The BER of the signal transmission through one I/O port was better than 10-11 at a data rate of 800 Mb/s × 10 b with a large timing-budget margin (870 ps) and skew of less than 140 ps. This shows that RHiNET-2/SW can provide high-throughput, highly reliable optical data transmission between the nodes of a network-based parallel computing system.

• Access to Document (DOI)

64-Gbit/s highly reliable network switch (RHiNET-2/SW) using parallel optical interconnection

Shinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Junji Yamamoto, Katsuyoshi Harasawa, Nobuhiro Matsudaira, Shigeto Akutsu, and Hideharu Amano

IEEE journal of lightwave technology (Special issue on Optical Networks) 18 ( 12 ) 1620-1627 2000.11

Research paper (conference, symposium, etc.), Joint Work, Accepted

A high-speed, highly-reliable network switch for parallel computing system using optical interconnection

Shinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Koji Tasho, Katsuyoshi Harasawa, Shigeto Akutsu, Shuji Fukuda, Yasutaka Shikichi

The IEICE Transaction on Electronics (Special Issue on Optical Interconnects/ Optical Signal Processing) E84 ( 9 ) 756-765 - 294 2000.09

Research paper (conference, symposium, etc.), Joint Work, Accepted,  ISSN  0916-8524

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RHiNET-2/SW is a network switch for the RHiNET-2 parallel computing system. RHiNET-2/SW enables high-speed and long-distance data transmission between PC nodes for parallel computing. In RHiNET-2/SW, a one-chip CMOS switch-LSI and eight pairs of 800-Mbit/s × 12-channel parallel optical interconnection modules are mounted into a single compact board. This switch allows high-speed 8-Gbit/s/port parallel optical data transmission over a distance of up to 100 m, and the aggregate throughput is 64 Gbit/s/board. The CMOS-ASIC switching LSI enables high-throughput (64 Gbit/s) packet switching with a single chip. The parallel optical interconnection modules enable high-speed and low-latency data transmission over a long distance. The structure and layout of the printed circuit board is optimized for high-speed, high-density device implementation to overcome electrical problems such as signal propagation-loss and crosstalk. All of the electrical interfaces are composed of high-speed CMOS-LVDS logic (800 Mbit/s/pin). We evaluated the realibility of the optical I/O port through long-term data transmission. No errors were detected during 50 hours of continuous data transmission at a data of 800 Mbit/s × 10 bits (BER: < 2.44×10-14). This test result shows that RHiNET-2/SW can provide high-throughput, long-transmission-length, and highly reliable data transmission in a practical parallel computing system.

A Network Switch for Supporting High Performance Parallel Processing by Computers Distributed in Local Area

NISHI Hiroaki, TASHO Koji, KUDOH Tomohiro, AMANO Hideharu

The Transactions of the Institute of Electronics,Information and Communication Engineers. (The Institute of Electronics, Information and Communication Engineers)  J-83-DI ( 2 ) 245-254 - 254 2000.04

Research paper (conference, symposium, etc.), Single Work, Accepted,  ISSN  0915-1915

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我々は、PCやWSを相互に接続して効率の良い並列処理を行うための通信アーキテクチャRHiNETの開発を行っている.RHiNETでは, 1箇所に集められた計算機だけでなく, ビル内やフロア内に設置され日常の業務に使用されている計算機を並列処理に利用する.RHiNETで用いるネットワークには, 高性能計算のための高い実効バンド幅と小さなレイテンシ, 及びビル内やフロア内の計算機を接続するためのリンク長と自由なトポロジーが求められる.従来のLANでは、スイッチに大容量のメモリをもつことにより両方の条件を満たす.本論文ではRHiNETのネットワークで用いるスイッチRHiNET / SW1のアーキテクチャと実装について述べる.RHiNET / SW1では, スイッチASIC外部にSRAMによる大容量パケットバッファを備え, 仮想チャネルキャッシュと呼ぶ手法を用いている.また, シミュレータによる性能評価も示す.

RHiNET-2/SW: a large- throughput, compact network- switch using 8.8-Gbit/s optical interconnection

Shinji Nishimura, Katsuyoshi Harasawa, Nobuhiro Matsudaira, Shigeto Akutsu, Tomohiro Kudoh, Hiroaki Nishi, and Hideharu Amano

New Generation Computing 18 ( 2 ) 188-197 2000.01

Research paper (conference, symposium, etc.), Joint Work, Accepted

Low latency high bandwidth message transfer mechanisms for a network interface plugged into a memory slot

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano

Cluster Computing 5 ( 5 ) 7-17 - 17 2000

Research paper (scientific journal), Single Work

• Access to Document (DOI)

A local area system network RHiNET-1: A network for high performance parallel computing

H. Nishi, K. Tasho, J. Yamamoto, T. Kudoh, H. Amano

Proceedings of the IEEE International Symposium on High Performance Distributed Computing (IEEE Computer Society)  2000-January   296 - 297 2000

ISSN  1082-8907

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© 2000 IEEE. The Real World Computing Partnership (RWCP) has developed a local area system network (LASN) called RHiNET-1 (RWCP High-performance NETwork, version 1) using 1.33-Gbps optical interconnections for high-performance computing using personal computers distributed in an office or laboratory environment. The network interface, RHiNET-1/NI, uses a complex programmable logic device (CPLD) based protocol controller to provide an easy evaluation platform for various protocols. It fits in a 32-bit/33-MHz PCI bus. The switch, RHiNET-1/SW, consists of a single-chip CMOS switch and external SRAM. It provides low-latency, reliable communication with a flexible topology design. We are currently evaluating protocols on RHiNET-1. RHiNET-1 will enable a new form of high-performance computing environment. We are also developing the second implementation, RHiNET-2. RHiNET-2/NI will support a 64-bit/66-MHz PCI bus. RHiNET-2/SW is an 8-Gbps/port 8x8 single-chip ASIC switch. The aggregate bandwidth of RHiNET-2/SW is 64 Gbps.

• Access to Document (DOI)

High-throughput network switch for the RHiNET-2 optically interconnected parallel computing system

Shinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Katsuyoshi Harasawa, Nobuhiro Matsudaira, Shigeto Akutsu, Koji Tasyo, Hideharu Amano

Proceedings of SPIE - The International Society for Optical Engineering 4089   562 - 569 2000

ISSN  0277-786X

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We have produced a prototype network-switch board (the RHiNET-2/SW) for optical interconnection. Eight pairs of 800-Mbit/s×12-channel optical interconnection modules and a one-chip CMOS ASIC switch LSI (a 784-pin BGA package) are mounted on to a single board. This board allows 8-Gbit/s/port parallel optical data transmission over a distance of up to 100 m, and the aggregate throughput is 64 Gbit/s/board. All of the electrical interfaces are composed of CMOS-LVDS logic. We have evaluated the skew of the signal and the reliability of each optical port by measuring the BER. No errors were detected during the 1011-bit packet data transmission at a data rate of 880 Mbit/s×10 bits (8.8 Gbit/s/port). (This corresponds to a BER of less than 10-11). The skew between data channels in one I/O port was less than 141 ps. The fiber length was 50 m. This test result shows that we achieved a high-throughput and long-transmission-length RHiNET-2/SW system using optical interconnection, and that the reliability of the I/O ports in the RHiNET-2/SW is sufficient for the RHiNET-2 parallel computing system.

RHiNET: A network for high performance parallel computing using locally distributed computers

T Kudoh, S Nishimura, J Yamamoto, H Nishi, O Tatebe, H Amano

INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS (IEEE COMPUTER SOC)     69 - 73 2000

Accepted,  ISSN  1063-6404

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A local area distributed computing system called RHiNET (RWCP High Performance Network), in which thousands of commodity personal computers and workstations can be connected by high speed optical interconnection is being developed. RHiNET consists of network interfaces, network switches and optical interconnections. RHiNET will provide a single system image to users and support high performance parallel computing. This paper presents an overview of the system.

RHiNET-2/SW: A high-throughput, compact network-switch using 8.8-Gbit/s optical interconnection

Shinji Nishimura, Katsuyoshi Harasawa, Nobuhiro Matsudaira, Shigeto Akutsu, Tomohiro Kudoh, Hiroaki Nishi, Hideharu Amano

New Generation Computing (SPRINGER VERLAG)  18 ( 2 ) 187 - 197 2000

Accepted,  ISSN  0288-3635

　View Summary

We have developed a high-throughput, compact network switch (the RHiNET-2/SW) for a distributed parallel computing system. Eight pairs of 800-Mbit/s×12-channel optical interconnection modules and a CMOS ASIC switch are integrated on a compact circuit board. To realize high-throughput (64 Gbit/s) and low-latency network, the SW-LSI has a customized high-speed LVDS I/O interface, and a high-speed internal SRAM memory in a 784-pin BGA one-chip package. We have also developed device implementation technologies to overcome the electrical problems (loss and crosstalk) caused by such high integration. The RHiNET-2/SW system enables high-performance parallel processing in a distributed computing environment.

• Access to Document (DOI)

MEMOnet: Network interface plugged into a memory slot

N. Tanabe, J. Yamamoto, H. Nishi, T. Kudoh, Y. Hamada, H. Nakajo, H. Amano

Proceedings - IEEE International Conference on Cluster Computing, ICCC (IEEE Computer Society)  2000-January   17 - 26 2000

ISSN  1552-5244

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© 2000 IEEE. The communication architecture of the DIMMnet-1 network interface, based on MEMOnet, is described. MEMOnet is an architecture consisting of a network interface plugged into a memory slot. The DIMMnet-1 prototype will have two banks of PC133 based SO-DIMM slots and an 8 Gbps full duplex optical link or two 448 MB/s full duplex LVDS channel links. The software overhead incurred to generate a message is only I CPU cycle and the estimated hardware delay is less than 100 ns using the atomic on-the-fly sending with header TLB. The estimated achievable communication bandwidth with block on-the-fly sending with protection stampable window memory is 440 MB/s which was observed in our experiments writing to the DIMM area with a write combining attribute. This is 3.3 times higher than the maximum bandwidth of PCI. This high performance distributed computing environment is available using economical personal computers with DIMM slots.

• Access to Document (DOI)

The RDT Router Chip: A versatile router for supporting a distributed shared memory

Hiroaki Nishi, Ken-ichiro Anjo, Tomoiro Kudoh, Hideharu Amano

IEICE TRANSACTIONS on Information and Systems E80-D ( 9 ) 854-862 1997.09

Research paper (scientific journal), Joint Work

相互結合網RDT上での階層マルチキャストによるメモリコヒーレンシ維持手法

西村 克信，工藤 知宏，西 宏章，楊 愚魯，天野 英晴

情報処理学会論文誌「並列処理」特集 37   1367-1377 1996.08

Research paper (scientific journal), Joint Work