Details of a Researcher - Nishi, Hiroaki

Papers - Nishi, Hiroaki

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KNIVES: Network based demand and supply control system - Enhancement for network and environmental affinity -

Toshihiko Handa, Charlotte Roesener, Junichi Ichimura, Hiroaki Nishi

IEEE International Conference on Industrial Informatics (INDIN) (IEEE) 2 1171 - 1176 2007

ISSN 1935-4576

KNIVES (Keio University Network oriented Intelligent and Versatile Energy saving System) is an IT based system, designed for Japanese power grids, that supports efficient control and balanced power supply. As KNIVES focuses on the integration of a vast numbers of end-users, it provides the necessary scalability, reliability, and dynamic adaptability. The latest generation of KNIVES system (V2) provides a new hardware concept for a local control that reflects environmental affinity. KNIVES terminals use Internet communication and supports ZigBee based environment sensors. The implementations of this system and practical field tests are described in this paper. ©2007 IEEE.

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Position control using an FPGA based on multirate acceleration control

Hiroyuki Tanaka, Kouhei Ohnishi, Hiroaki Nishi

Proceedings of the 2007 4th IEEE International Conference on Mechatronics, ICM 2007 (IEEE) 323 - 328 2007

Accepted

Acceleration control using a disturbance observer is a strategy of robust motion control. In the acceleration control, fast sampling rate is a key issue to improve the performance of robustness. By using FPGAs, faster sampling rates can be achieved than those using PCs. The sampling rates of the systems using FPGAs can be faster than the frequency of PWM wave. In that case, the performance of the acceleration control is not improved as expected. The frequency of the PWM wave becomes a performance limitation of the system. In this paper, a position control system based on acceleration control using multirate sampling method is implemented into an FPGA to overcome the limitations. In these multirate systems, the sampling rates of the system output and control calculations are faster than that of the system input. Experimental results show that the robustness of the system can be improved, even though the sampling rates of the system output and the control calculations are faster than the PWM frequency by using the multirate sampling method. ©2007 IEEE.

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ジッタバッファを用いたネットワークバイラテラル制御システム

加藤敦, 西宏章, 大西公平

電気学会論文誌D 産業応用部門誌 (The Institute of Electrical Engineers of Japan) 126 ( 12 ) 1737-1738 - 1738 2006.12

Research paper (scientific journal), Single Work, Accepted, ISSN 0913-6339

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Cache-based Network Processor Architecture: Evaluation with Real Network Traffic

Michitaka Okuno, Shinji Nishimura, Shinichi Ishida Hiroaki Nishi

Special Section on Novel Device Architectures and System-Integration Technologies, IEICE Transactions on Electronics (IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG) E89-C ( 11 ) 1620-1628 - 1628 2006.11

Research paper (scientific journal), Single Work, Accepted, ISSN 0916-8524

A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the prototype is evaluated with real network traffic traces. This architecture consists of several small processing units (PUs) and a bit-stream manipulation hardware called a burst-stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC) and a cache-miss handler (CMH). The PLC memorizes a packet-processing method with all table-lookup results, and applies it to subsequent packets that have the same information in their header. To avoid packet-processing blocking, the CMH handles cache-miss packets while registration processing is performed at the PLC. The combination of the PLC and CMH enables most packets to skip the execution at the PUs, which dissipate huge power in conventional NPs. We evaluated an FPGA-based prototype with real core network traffic traces of a WIDE backbone router. From the experimental results, we observed a special case where the packet of minimum size appeared in large quantities, and the cache-based NP was able to achieve 100 throughput with only the 10-throughput PUs due to the existence of very high temporal locality of network traffic. From the whole results, the cache-based NP would be able to achieve 100-Gbps throughput by using 10- to 40-Gbps throughput PUs. The power consumption of the cache-based NP, which consists of 40-Gbps throughput PUs, is estimated to be only 44.7 that of a conventional NP. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.

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A Controller Design Method of Decentralized Control System

Toshiaki Tsuji, Hiroaki Nishi and Kouhei Ohnishi

IEEJ Transactions on Industry Applications 126-D ( 5 ) 630-638 2006.05

Research paper (scientific journal), Single Work, Accepted, ISSN 0913-6339

Decentralized control is a promising method with many advantages while an effective design method for it is desired. Design in conventional methods is complicated because the correspondence between a system role and its controllers is unclear. To solve this problem, we have proposed the idea of "functionality" for a bilateral control system. The idea is to divide the system role into minimum components. The design method based on this idea is clear since controllers correspond to respective functions. Furthermore, the design method is simple since each function is a minimum component. This study expands the idea of the functionality to design of decentralized control systems. Subsystems are constructed based on functions. Functions for normal operation and for exception handling are treated in a unified manner. The system can automatically sustain important functions by a priority order of functions. This method realizes simple and explicit controller design for a decentralized control system with exception handling. Simulation and experimental results show the flexibility, fault tolerance and expandability of the decentralized system.

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A Controller Design Method of Bilateral Control System

Toshiaki Tsuji, Kenji Natori, Hiroaki Nishi, Kouhei Ohnishi

European Power Electronics and Drives Journal (EPE Journal) (TAYLOR & FRANCIS LTD) 14 ( 2 ) 22-28 - 27 2006.05

Research paper (scientific journal), Single Work, Accepted, ISSN 0939-8368

Haptic sense is indispensable for skillful operation in a telerobotic system. Bilateral control attracts considerable interest because it transfers the haptic sense to a remote place. Although it is simply composed of two manipulators, its design is complicated. This study proposes an idea that provides a new framework on design of a bilateral control system. The idea is to design the bilateral control system based on a "function", a minimum component of a system role. It enables simple and explicit design for various tasks. The features of the proposed method provide a way to design an adjustable system. Experimental results show the validity of the proposed method.

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100-Gb/s Physical-layer Architecture for Next-Generation Ethernet

Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Kouji Fukuda, Kouji Nakahara, and Hiroaki Nishi

IEICE Transactions on Communications (IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG) E89-B ( 3 ) 696-703 - 702 2006.03

Research paper (scientific journal), Single Work, Accepted, ISSN 0916-8516

A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding networks. Its links comprise 12 × 10-Gb/s synchronized parallel optical lanes. Ethernet data frames are transmitted by coarse wavelength division multiplexing link and bundled optical fibers. Ten of the lanes convey 640-bit data synchronously (64 bits × 10 lanes). One conveys forward error correction code ((132 b, 140 b) Hamming code), providing highly reliable (BER < 10-12) data transmission, and the other conveys parity data, enabling fault-lane recovery. A newly developed 64B/66B code-sequence-based deskewing mechanism is used that provides low-latency compensation for the lane-to-lane skew, which is less than 88 ns. Testing of this physical-layer architecture in a field programmable gate array circuit demonstrated that it can provide 100-Gb/s data communication with a 590 k gate circuit, which is small enough for implementation in a single LSI circuit. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.

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マルチレートサンプリング手法を用いた加速度制御系の実現

水落麻里子, 辻俊明, 大西公平, 西宏章

電気学会論文誌産業応用部門誌 126 ( 3 ) 261-268 2006.03

Research paper (scientific journal), Single Work, Accepted

Cache-based Packet-processing Techniques for Broadband Network Exploiting Temporal Locality of Network Traffic

OKUNO MICHITAKA, NISHIMURA SHINJI, ISHIDA SHIN-ICHI, NISHI HIROAKI

IPSJ journal (Information Processing Society of Japan (IPSJ)) 47 ( 2 ) 346-353 - 354 2006.02

Research paper (scientific journal), Joint Work, Accepted, ISSN 1882-7764

The cache-based packet-processing enginge (PPE) that consists of Process-Learning Cache (PLC) and Cache-Miss Handler (CMH) is proposed to achieve 100-Gbps (Gigabit per second) wire-rate throughput which would be needed for backbone routers in 2007 or later to support broadband network. In this paper, several technical requirements and those solutions for cache-based PPE are shown. Also details of a prototype of the cache-based PPE are shown. By using real network traffic traces, we show the cache-based PPE can achieve the wire-rate throughput. As another aspect, PPEs are required low power consumption. In our estimation, the cache-based PPE can be constructed about 46% LSI-die size and power consumption of a conventional PPE.

Discussion of aspects in energy management with demand response system KNIVES

S. Ishida, C. Roesener, H. Nishi, J. Ichimura

IEEE International Conference on Emerging Technologies and Factory Automation, ETFA (IEEE) 465 - 468 2006

This paper describes with the design of a communication network necessary for Demand Response systems adapted to the requirements of the Japanese power grid. Based on KNIVES controllers and network devices an exemplary redundant hierarchical tree structure is proposed to meet high demands on reliability, scalability and dynamic adaptability in order to be capable to secure the wholesale competition. Therefore essential information for energy management has to be secured, managed, processed and delivered. Using Internet for communication, the network has to guarantee reliability facing a high variety of network availability. This approach focuses on redundant data management combined with non local control loops of the power supply system, which shall guarantee a functional safe and high-performance microglia. © 2006 IEEE.

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Energy assessment of cogeneration and air conditioning system on Keio University Shonan Fujisawa Campus

Atsushi Mise, Hitoaki Nishi, Haruki Sato

2006 IEEE International Conference on Industrial Informatics, INDIN'06 387 - 392 2006

Conservation of energy has become a major concern all over the world. Especially in the domestic area, public buildings, and office buildings, energy supply systems have to be optimized swiftly balancing with the time-dependent energy demand. This paper discusses the exemplary energy assessment of the cogeneration and air-conditioning system on Keio University Shonan Fujisawa Campus with approximately 5,000 students and 200 faculty members. The purpose of the cogeneration system consisting of prime mover and exhaust heat recovery equipment is a conlribution to energy conservation. Exhaust heal of lhe prime mover can be reutilized in form of heated or chilled water by the exhaust heat recovery equipment. Optimized reutilization of exhaust heat shall bring the main benefit for energy conservation. Therefore, the effectiveness of the cogeneration system has been evaluated based on collected annual data of energy consumption on the campus. Furthermore, curtailment of air-conditioning systems during peak load caused by the congestion of the grid power has been examined. In order to optimize the energy management under these conditions, the forecast of power consumption has been discussed, and the relation of power consumption to air temperature has been examined. © 2006 IEEE.

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Internet-based hybrid demand control system for Japanese power grid

C. Roesener, S. Ishida, J. Ichimura, H. Nishi

IEEE International Workshop on Factory Communication Systems - Proceedings, WFCS 395 - 400 2006

Worldwide the demand on a higher level of automatic control of power systems rises to comply with system objectives of reliability, efficiency, cost minimization as well as emission requirements. With the transition of the power systems towards a more volatile on-site generation based on renewable resources, a higher degree of flexibility in energy consumption for reduced system congestion is evident. This paper presents a real-time information system for active control of the demand side in Japanese power grids. The proposed system allows local data processing of environmental and consumption data to schedule and curtail loads of shops, small and medium size enterprises. The concept comprises specialized control hardware for end-use supervision, local and internet based server architecture and control methods for global energy management. © 2006 IEEE.

Improvement of performance in bilateral teleoperation by using FPGA

Ena Ishii, Hiroaki Nishi, Kouhei Ohnishi

International Workshop on Advanced Motion Control, AMC (IEEE) 2006 317 - 322 2006

Accepted

Bilateral teleoperation has been needed in many scenes such as space activities or undersea, work on a atomic power plant and minimally invasive surgery, etc. In bilateral teleoperation, transfer of keen tactile sense as if the operator directly touch the environment without using the robot is required. Wide frequency bandwidth of force sensing is required to achieve transfer of a keen tactile sensation. Bilateral controller based on acceleration control with disturbance observer is available to achieve transfer of a keen tactile sensation. The frequency bandwidth of force sensing is determined by cut-off frequency of low-pass filter used in disturbance observer. The cut-off frequency is in inverse proportion to a sampling period. Therefore, shortening of the sampling period improves performance of bilateral teleoperation. In this paper, bilateral teleoperation system by using FPGA(Field Programmable Gate Array) is introduced. FPGA is a LSI that user can design its internal logic. When motion controller is implemented on FPGA, it operates faster than that implemented in a PC(Personal computer) with RTOS(Real Time Operating System). The sampling period is shortened from 100/its to 10μs by using FPGA. © 2006 IEEE.

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Implementation of Internet based demand controlling system

S. Ishida, C. Roesener, J. Ichimura, H. Nishi

2006 IEEE International Conference on Industrial Informatics, INDIN'06 381 - 386 2006

Due to liberalization processes initiated on Japan's power market since 2000, a significant higher congestion on the power grid is expected entailing a higher vulnerability to shortages. With increasing aspirations on power supply security, an interaction with the demand side has become inevitable to reduce the congestion without the need for new generation or transmission capacities. Attaining efficiency close to the optimum in curtailing and rescheduling loads, the fast automatic processing of essential information affecting the performance of the power grid is crucial. This approach shows a solution for hybrid demand control integrating a vast number of small and medium sized enterprises for centralized load management based on locally collected environmental data. The hardware and software of this system has been prototyped and evaluated. Evaluation tests show the capability of this system to deliver the necessary infrastructure necessary for demand control. © 2006 IEEE.

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Evaluation of cache base network processor by using real backbone network trace

Shinichi Ishida, Michitaka Okuno, Hiroaki Nishi

2006 Workshop on High Performance Switching and Routing, HPSR 2006 (IEEE) 49 - 54 2006

Accepted

In this paper a novel cache-based packet-processing-engine (PPE) architecture that achieves high packet-processing throughput with low-power consumption is proposed and evaluated. As network packets of the same header information appear repeatedly in a short time, a special cache, the so called header-learning cache(HLC), memorizes the packet-processing method and enables most packets to skip the execution at the processing units array. The implementation of the cache-based PPE architecture, P-Gear, was designed. Real backbone network trace was used to evaluate the performance of it. This P-Gear can achieve over 80% cache hit rate using 4K/32K entry for access/core networks. Compared to conventional PPE, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.6% of the power consumption required by the conventional PPE. © 2006 IEEE.

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A 100-Gb-Ethernet subsystem for next-generation metro-area network

Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Ryouji Yamaoka, Hiroaki Nishi

IEEE International Conference on Communications (IEEE) 2 1036 - 1042 2005

ISSN 0536-1486

An ultra high-speed Ethernet subsystem, which realizes 100-Gb/s throughput and transmission up to 40 km, is examined for next-generation metro-area networks. A parallel link of 12 10-Gb/s synchronized parallel optical lanes is proposed. The 10 optical lanes are used to transmit 10-bit parallel data. The one of redundant lanes transmits a forward error correction code ((132b, 140b) Hamming code) to achieve highly-reliable (BER < 10-12) data transmission, and the other lane transmits a parity data used for the fault-lane recovery. Here, a 64B/66B code-sequence-based de-skewing mechanism is proposed, and its effectiveness to realize low-latency compensation of the inter-lane skew (< 80 ns) is shown. We have implemented the 100-Gb-Ethernet interface architectures into FPGA circuits, and confirmed the performance of 100 Gb/s data communication with compact 385-kgates circuit size, which is practically small for implementation in a single LSI circuit. © 2005 IEEE.

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Bilateral teleoperation based on modal system design

Ena Ishii, Seiichiro Katsura, Hiroaki Nishi, Kouhei Ohnishi

IEEE International Symposium on Industrial Electronics IV 1527 - 1532 2005

Accepted

Technology for teleoperation has been needed in many scenes. Especially in robotic surgery, It is required that to transmit the tactile sensation to the operator. To attain that need, teleoperation method called bilateral has developed. Bilateral means transmit information each other. Environmental information is transmitted both from master to slave and from slave to master in bilateral teleoperation. In bilateral teleoperation, environmental information of master and slave should be exchanged in common coordinates. It is difficult to define a common coordinates in different structured bilateral teleoperation. Mode based control for bilateral teleoperation is proposed in this paper. Coordinates based on geometric mode is used to common coordinates to exchange the environmental information between master robot and slave robot. Geometric environmental mode is quarried by quarry matrix and hypothetical axes bilateral controller based on acceleration control is applied to hypothetical mode motors. Hypothetical mode master motor and mode slave motor are transformed to mode common motor and mode differential motor. Force servo controller is applied to mode common motor and position regulator is applied to mode differential motor. Viability of proposed method is shown in experimental result. ©2005 IEEE.

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A velocity measurement method for acceleration control

Toshiaki Tsuji, Mariko Mizuochi, Hiroaki Nishi, Kouhei Ohnishi

IECON Proceedings (Industrial Electronics Conference) 2005 1943 - 1948 2005

Accepted

This paper proposes a novel method of velocity measurement for motor drives with optical encoders. Acceleration control is indispensable for advanced motion control while it requires accurate velocity information. Although many methods on velocity measurement have been proposed, accurate measurement was not achieved in a high-speed range. We therefore propose " synchronousmeasurement method (S method)" that measures the velocity synchronized with alteration of pulse numbers. Accurate velocity measurement is achieved in all speed ranges with this method. Furthermore, other estimation methods are applicable in addition since the method does not require any model of a control object. Simulation and experimental results verify the validity of the proposed method. © 2005 IEEE.

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A packet forwarding layer for DIMMnet and its hardware implementation

Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo

Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05 (CSREA Press) 2 461 - 467 2005

DIMMnet-1 is a high-performance network interface for a PC cluster system. It uses memory bus for IO bus to relax a bottleneck of networks. Moreover, a PC memory bus is spread bandwidth earliest in a PC, the DIMMnet-1 can reorganize a NIC according to spreading bandwidth of a communication link. However, the NIC that use a parallel transmission lacks a scalability of a bandwidth of a communication link. To resolve this problem, we developed new NICs : DIMMnet-1/bDais and DIMMnet-2. We employ a high-speed serial transmission on these NICs. Therefore we have to expand the DIMMnet network protocol. Now we have been developing new DIMMnet network protocol by two parts. The One is the CoreLogic which includes communication primitives. In this paper, we describe the rest of that which is the InfiniSWIF that includes functions of packet forwarding. And we propose the Concurrent Datagram communication service which is implemented in the InfiniSWIF and gives reliability and scalability for the DIMMnet network protocol.

SoC architecture synthesis methodology based on high-level IPs

Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Yoichi Onishi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E87-A ( 12 ) 3057 - 3067 2004.12

ISSN 0916-8508

We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.

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