研究者詳細 - 西　宏章

論文 - 西　宏章

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Autonomous Decentralized Control for Formation of Multiple Mobile-Robots Considering Ability of Robot

Hiroamasa Takahashi, Hiroaki Nishi, Kouhei Ohnishi

IEEE Transactions on Industrial Electronics （IEEE） Vol. 51 （ 6 ） 1272- 1279 - 1279 2004年05月

研究論文（学術雑誌）, 共著, 査読有り, ISSN 0278-0046

The purpose of this study is to control multiple mobile robots in formation considering the ability of a robot using the "Leader-Following" strategy. There are three features of this study. First, a performance index that shows mobile robot ability is quantified. Specifically, maximum acceleration and maximum velocity of a robot are defined by maximum admissible rotation and maximum continuous torque of a motor. The performance index is quantified from arrival time on the destination using these parameters. Second, a new controller is proposed based on the performance index, so that robots can be controlled according to robot ability. Third, a compliance controller using a virtual repulsion is suggested in this paper, so that each robot can avoid collision. Finally, simulation and experiments are done in a real-time system using RT-Messenger. RT-Messenger allows robots to transmit information regarding their positions to each other in real time. These results shows the validity of the proposed method. © 2004 IEEE.

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Design methodology for SoC architectures based on reusable virtual cores

Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC （IEEE Computer Society） 256 - 262 2004年

The design reuse methodology, which has been developed at the VCDS Project, is a SoC design methodology to reduce the SoC design time using high level design intellectual properties named as Virtual Cores (VCores). In this paper, we propose the VCore based design methodology to synthesize the SoC architecture from the system level specification. This synthesis methodology generates an initial architecture that consists of a CPU, buses, I/Os peripherals, and RTOS (Real Time Operating System), and makes tradeoffs between hardware and software on assigned software VCores and hardware VCores models to the architecture. The results of an architecture level design experiment using the proposed methodology shows that the partial automation of the communication refinement process, allied with design reuse, accelerates the architecture synthesis, thus reducing the design time required to design an architecture.

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Signal Transmission and Coding Architecture for Next Generation Ethernet

西宏章

IEICE Transaction on Information and Systems E-86-D （ 11 ） 2003年11月

研究論文（学術雑誌）, 共著

Signal Transmission and Coding Architecture for Next Generation Ethernet

Hidehiro Toyoda, Hiroaki Nishi, Shinji Nishimura, Hisaaki Kanai, Katsuyoshi Harasawa

IEICE Journal Special Issue on New Technologies in the Internet and their Architecture E-86-D （ 11 ） 2317-2324 2003年11月

研究論文（研究会，シンポジウム資料等）, 共著, 査読有り

Low-Power Network-Packet-Processing Architecture Using Process Learning Cache for High-end Backbone Router

Michitaka Okuno, Shin-ichi Ishida, Hiroaki Nishi

IEICE Transaction on Electronics(Special Section on Low-Power LSI, Low-Power IP and Low Power Devices) （Institute of Electronics, Information and Communication, Engineers, IEICE） E88-C （ 4 ） 536-543 - 543 2003年10月

研究論文（研究会，シンポジウム資料等）, 共著, 査読有り, ISSN 0916-8524

A novel cache-based packet-processing-engine (PPE) architecture that achieves low-power consumption and high packet-processing throughput by exploiting the nature of network traffic is proposed. This architecture consists of a processing-unit array and a bit-stream manipulation path called a burst stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC). Network packets, which have the same information in their header, appear repeatedly over a short time. By exploiting that nature, the PLC memorizes the packet-processing method with all results (i.e., table lookups), and applies it to other packets. The PLC enables most packets to skip the execution at the processing-unit array, which consumes high power. As a practical implementation of the cache-based PPE architecture, P-Gear was designed. In particular, P-Gear was compared with a conventional PPE in terms of silicon die size and power consumption. According to this comparison, in the case of current 0.13-μm CMOS process technology, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.8% of the power consumption required by the conventional PPE. Configurations of both architectures for the 1- to 100-Gbps throughput range were also analyzed. In the throughput range of 10-Gbps or more, P-Gear can achieve the target throughput in a smaller die size than the conventional PPE. And for the whole throughput range, P-Gear can achieve a target throughput at lower power than the conventional PPE. Copyright © 2005 The Institute of Electronics, Information and Communication Engineers.

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The Architecture and Evaluation of 3rd-generation RHiNET Switch for High-performance Parallel Computing

Hiroaki Nishi, Shinji Nishimura, Katsuyoshi Harasawa, Tomohiro Kudoh, Hideharu Amano

Special Issue on Development of Advanced Computer Systems E-86-D （ 10 ） 1987-1995 2003年10月

研究論文（研究会，シンポジウム資料等）, 共著, 査読有り

Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing

Hiroaki Nishi, Shinji Nishimura, Katsuyoshi Harasawa, Tomohiro Kudoh, Hideharu Amano

IEICE Transactions on Information and Systems E86-D （ 10 ） 1987 - 1995 2003年10月

ISSN 0916-8532

RHiNET-3/SW is the third-generation switch used in the RHiNET-3 system. It provides both low-latency processing and flexible connection due to its use of a credit-based flow-control mechanism, topology-free routing, and deadlock-free routing. The aggregate throughput of RHiNET-3/SW is 80 Gbps, and the latency is 140 ns. RHiNET-3/SW also provides a hop-by-hop retransmission mechanism. Simulation demonstrated that the effective throughput at a node in a 64-node torus RHiNET-3 system is equivalent to the effective throughput of a 64-bit 33-MHz PCI bus and that the performance of RHiNET-3/SW almost equals or exceeds the best performance of RHiNET-2/SW, the second-generation switch. Although credit-based flow control requires 26% more gates than rate-based flow control to manage the virtual channels (VCs), it requires less VC memory than rate-based flow control. Moreover, its use in a network system reduces latency and increases the maximum throughput compared to rate-based flow control.

LAN領域での高性能並列処理に適したネットワークスイッチ用ASIC

西宏章，西村信治，工藤知宏，天野英晴

電子情報通信学会論文誌システムＬＳＩのための先進アーキテクチャ特集号C （一般社団法人電子情報通信学会） J86-C （ 8 ） 836-844 - 844 2003年08月

研究論文（研究会，シンポジウム資料等）, 共著, 査読有り, ISSN 1345-2827

本論文では,LAN領域で低遅延かつ高信頼な計算環境を実現するRHiNETシステムについて,このシステムで用いるネットワークスイッチRHiNET-3/SWに搭載するスイッチASIC,及びスキュー調整ASICについて述べる.スイッチASICは小さい処理遅延,高い柔軟性,高い信頼性を兼ね備える.また,スキュー調整ASICは,1kmの伝送路で発生するスキューを効率良く調整するため新しい環状スキュー調整符号を用いる.

Virtual core based synthesis of SoC architectures

Hiroaki Nishi, Michiaki Muraoka, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada

IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings 1 35 - 40 2003年

ISSN 1523-553X

© 2003 IEEE. The reuse of high-level design intellectual properties is indispensable to reduce SoC design time. It has been difficult for SoC designers to design and compare two or more SoC architectures in a given product design time. In this paper, we present a synthesis methodology of SoC architectures using Virtual Cores (VCores) to perform architectural explorations in a short period. The proposed synthesis methodology generates an initial architecture, which consists of a CPU, buses, I/Os. etc., and makes tradeoffs between hardware and software on mapped software VCores and hardware VCores models. The authors show the usefulness of me proposed method from the results of an architecture level design experiment.

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VCore-based design methodology.

Michiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida

Proceedings of the 2003 Asia and South Pacific Design Automation Conference(ASP-DAC) （ACM） 441 - 445 2003年

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Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System

Tomohiro Otsuka, Konosuke Watanabe, Jun ichiro Tsuchiya, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Hideharu Amano

IASTED International Multi-Conference on Applied Informatics （IASTED/ACTA Press） 21 738 - 743 2003年

Synthesis for SoC architecture using VCores

H. Nishi, M. Muraoka, R. K. Morizawa, H. Yokota, H. Hamada

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC （ACM） 2003-January 446 - 452 2003年

© 2003 IEEE. In this paper, we propose a novel architecture synthesis method for SoCs using VCores (virtual cores). VCores are reusable and configurable high-level descriptions. An initial SoC architecture, which consists of a CPU, buses, and peripherals, is generated, based on an architecture template. The hardware and software tradeoff is possible on the architecture model after assignment of software VCores or hardware VCores. The assignment is based on the results of the architecture's performance estimation. We present a prototype of the synthesis for SoC architecture using VCores and an architecture level design experiment using this prototype.

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Performance evaluation of RHiNET 2/NI: A network interface for distributed parallel computing systems

Konosuke Watanabe, Tomohiro Otsuka, Jun Ichiro Tsuchiya, Hideharu Amano, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh

Proceedings - CCGrid 2003: 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid （IEEE Computer Society） 318 - 325 2003年

査読有り

RHiNET-2/NI is a network interface for a parallel and distributed computing system with network connected PCs. The core of the network interface is an ASIC network controller chip Martini, which provides low-latency and large-bandwidth communication. Evaluation results show that it achieves almost full bandwidth of the 66MHz/64bit PCI bus, which is much larger than that of Myrinet-2000. The performance of a small prototype parallel system achieves almost linear speed up. © 2003 IEEE.

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高性能計算をサポートするネットワークインタフェース用コントローラチップ Martini

山本淳二，渡邊幸之介，土屋潤一郎，原田浩，今城英樹，寺川博昭，西宏章，田邊昇，上嶋利明，工藤知宏，天野英晴

情報処理学会論文誌（一般社団法人情報処理学会） 43 （ SIG6 ） 122-133 - 133 2002年09月

研究論文（研究会，シンポジウム資料等）, 共著, 査読有り, ISSN 0387-5806

ユーザレベル・ゼロコピー通信を用いることで低レイテンシ・広バンド幅な通信を提供するネットワークRHiNETのネットワークインタフェースコントローラMartiniについて述べる.Martiniでは基本のRDMA機能をすべてハードワイヤード処理することで,低レイテンシ・広バンド幅のRHiNETネットワークを最大限利用する.その一方で内部にプロセッサを持つことで複雑な処理についても柔軟に対処できる構成となっている.

A network switch for supporting high-performance parallel processing by computers distributed in local areas

Hiroaki Nishi, Koji Tasho, Tomohiro Kudoh, Hideharu Amano

Systems and Computers in Japan 32 （ 14 ） 24 - 33 2001年12月

査読有り, ISSN 0882-1666

The authors have developed a communications architecture called RHiNET that is capable of high-performance parallel processing by interconnecting PCs and WSs. RHiNET uses not only computers concentrated in one place but also computers used for daily business within buildings and within floors for parallel processing. Networks used by RHiNET should have high effective bandwidths and small latencies for high-efficiency computing, as well as link lengths for connecting the computers within buildings and floors and a free topology. The former requirements are not satisfied sufficiently by the conventional LANs, while the latter is not satisfied by SANs which are used in cluster systems. RHiNET satisfies both conditions by using a switch having a large memory capacity. In this paper, the architecture and implementation of the RHiNET/SW1 switch used by RHiNET networks are discussed. A scheme called virtual cache is used in RHiNET/SW1 such that a large-capacity packet buffer is installed by SRAM outside the switch ASIC. In addition, the performance of the switch is evaluated by a simulator. © 2001 Scripta Technica, Syst. Comp. Jpn.

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RHiNET-2/SW: 並列光インタコネクションを搭載した並列計算機システム用高速ネットワークスイッチ

Shinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Junji Yamamoto, Katsuyoshi Harasawa, Shuji Fukuda, Yasutaka Shikichi, and Shigeto Akutsu

電子情報通信学会論文誌. C, エレクトロニクス（一般社団法人電子情報通信学会） 85 （ 6 ） 756-765 - 10 2001年09月

研究論文（研究会，シンポジウム資料等）, 共著, 査読有り, ISSN 8756-663X

分散配置したPC間を光インタコネクションで接続し, 大容量並列処理を可能とする計算機システムRHiNET-2に搭載する高速ネットワークスイッチRHiNET-2/SWを開発した.RHiNET-2/SWは, スイッチLSIと並列同期光インタコネクションモジュール(800Mbit/s×12ch)送受8対をボード上に高密度実装し, 単体で64Gbit/sの大容量スイッチング処理を実現する(8Gbit/s×8ポート).今回, ビットエラーレート測定により, 10^<-11>以下(近似計算によると10^<-20>台)の信頼性を確認すると共に, 本スイッチ5台とPCノード16台を接続して計算システムを構成し, 計算機システムとしての安定動作に成功した.本結果により, 並列計算機システムにおいて大容量かつ柔軟なネットワークを実現する光インタコネクションの実用性を実証した.

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RHiNET-2/SW: 並列光インタコネクションを搭載した並列計算機システム用高速ネットワークスイッチ，

西村信治，工藤知宏，西宏章，山本淳二，原澤克嘉，福田周司，敷地泰卓，圷重人

電子情報通信学会論文誌 J84-C （ 9 ） 756-765 2001年09月

研究論文（研究会，シンポジウム資料等）, 共著, 査読有り

Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers

Yulu Yang, Akira Funahashi, Akiya Jouraku, Hiroaki Nishi, Hideharu Amano, and Toshinori Sueyoshi

IEEE TRANSACTIONS on Parallel And Distributed Systems （IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC） 12 （ 7 ） 701-715 - 715 2001年07月

研究論文（研究会，シンポジウム資料等）, 共著, 査読有り, ISSN 1045-9219

Recursive Diagonal Torus (RDT), a class of interconnection network is proposed for massively parallel computers with up to 2 16 nodes. By making the best use of a recursively structured diagonal mesh (torus) connection, the RDT has a smaller diameter (e.g., it is 11 for 2 16 nodes) with a smaller number of links per node (i.e., 8 links per node) than those of the hypercube, A simple routing algorithm, called vector routing, which is near-optimal and easy to implement is also proposed. Although the congestion on upper rank tori sometimes degrades the performance under the random traffic, the RDT provides much better performance than that of a 2D/3D torus in most cases and, under hot spot traffic, the RDT provides much better performance than that of a 2D/3D/4D torus. The RDT router chip which provides a message multicast for maintaining cache consistency is available. Using the 0.5μm BiCMOS SOG technology, versatile functions, including hierarchical multicasting, combining acknowledge packets, shooting down/restart mechanism, and time-out/setup mechanisms, work at a 60MHz clock rate.

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Optical interconnection as an IP macro of a CMOS library

T. Yoshikawa, I. Hatakeyama, K. Miyoshi, K. Kurata, J. Sasaki, N. Kami, T. Sugimoto, M. Fukaishi, K. Nakamura, K. Tanaka, H. Nishi, T. Kudoh

Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects （IEEE Computer Society） 2001-January 31 - 35 2001年

ISSN 1550-4794

© 2001 IEEE. With the aim of producing a switch LSI with several-hundred-Gb/s-class throughput, we first developed LAN-LSIs with 10-Gb/s-class optical input/output (I/O) buffer. The optical I/O buffer was supplied as a set consisting of an optical-electrical package, soft or hard macros of the optical interface, and library files for a targeted CMOS technology. Using such library files, system LSI designers can implement an optical interface in their chips in a conventional design manner.

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RHiNET-3/SW: An 80-Gbit/s high-speed network switch for distributed parallel computing

S. Nishimura, T. Kudoh, H. Nishi, J. Yamamoto, R. Ueno, K. Harasawa, S. Fukuda, Y. Shikichi, S. Akutsu, K. Tasho, H. Amano

Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects （IEEE Computer Society） 2001-January 119 - 123 2001年

ISSN 1550-4794

© 2001 IEEE. We have developed a prototype network switch, RHiNET-3/SW, for a RHiNET high-performance distributed parallel computing environment. It has eight I/O ports and each port provides high-speed, bi-directional 10-Gbit/s-per-port parallel optical data transmission in a distance of over 300 m. The aggregate throughput is 80 Gbit/s per board. A switch consists of a one-chip CMOS ASIC 8x8 switch LSI (SW-LSI; a 784-pin BGA package), four deskew LSIs, and eight pairs of 1.25-Gbit/s x 12-channel optical interconnection modules on a single board. The switch uses a hop-by-hop retransmission mechanism and credit-based flow control to provide reliable and long-transmission-distance data communication. The deskew LSI has a skew compensation function for 10-bit parallel data channels and an 8B10B encoder/decoder. Its optical transmitter modules use an 850-nm VCSEL and a 12-channel MMF (multi-mode fiber) ribbon. RHiNET-3/SW enables high-throughput. Long-distance and flexible-flow-control network communication by means of distributed parallel computing using commercial PCs.

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