Nakano, Nobuhiko

写真a

Affiliation

Faculty of Science and Technology, Department of Electronics and Electrical Engineering （Yagami）

Position

Professor
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Career 【 Display / hide 】

  • 1995.04
    -
    1996.03

    日本学術振興会 ,特別研究員

  • 1995.04
    -
    1996.03

    慶應義塾大学理工学部 ,訪問研究員

  • 1996
    -
    1999

    1年生クラス担任

  • 1996.04
    -
    1999.03

    慶應義塾大学理工学部電子工学科 ,助手

  • 1999.04
    -
    2003.03

    慶應義塾大学理工学部電子工学科 ,専任講師

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Academic Background 【 Display / hide 】

  • 1990.03

    Keio University, Faculty of Science and Engineering, 電気工学科

    University, Graduated

  • 1992.03

    Keio University, Graduate School, Division of Science and Engineeri, 電気工学専攻

    Graduate School, Completed, Master's course

  • 1995.03

    Keio University, Graduate School, Division of Science and Engineeri, 電気工学専攻

    Graduate School, Completed, Doctoral course

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Academic Degrees 【 Display / hide 】

  • 工学, Keio University, 1995.03

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Research Areas 【 Display / hide 】

  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment (Electronic Device/Electronic Equipment)

  • Life Science / Neuroscience-general (General Neuroscience)

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Research Keywords 【 Display / hide 】

  • アナログ回路設計

  • noise modeling

  • bio-sensing

  • numerical simulation

  • LSI

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Papers 【 Display / hide 】

  • High-Temperature Operational Piezoresistive Pressure Sensor on Standard CMOS Process

    Sugiura T., Miura H., Nakano N.

    IEEE Transactions on Circuits and Systems II: Express Briefs （IEEE Transactions on Circuits and Systems II: Express Briefs)  70 （ 2 ） 726 - 730 2023.02

    ISSN  15497747

    　View Summary

    Piezoresistive pressure sensor designed in the standard CMOS process is proposed. The device features the electrical separation by the pn-junction provided by the standard CMOS process, which it does not need any MEMS processes or the post-processes. The proposed device is composed of vertical multi-pn junctions, and two methods of 3-layer and 4-layer are considered with their advantages and drawbacks. It features high-temperature robustness with silicon material, and integrability to silicon devices. It is designed without any additional processes and therefore enables to compatible to the CMOS devices with low-cost and suitable for mass production that are favorable for IoT (Internet of Things) applications.

  • On-Chip Carrier-Selective Contact Photovoltaic Cell

    Sugiura T., Miura H., Nakano N.

    IEEE Transactions on Electron Devices （IEEE Transactions on Electron Devices)   2023

    ISSN  00189383

    　View Summary

    This article proposes an on-chip photovoltaic cell equipped with a tunnel oxide passivated contact (TOPCon) exhibiting selective carrier contact. The proposed structure utilizes the gate region as the TOPCon structure and performs best when the gate oxide is high-<inline-formula> <tex-math notation="LaTeX">$\kappa$</tex-math> </inline-formula> hafnium oxide (HfO<inline-formula> <tex-math notation="LaTeX">$_\text{2}$</tex-math> </inline-formula>). Oxide thicknesses lower than 1.5 nm enable the utilization of the device as a solar cell; therefore, it can be fabricated using high-end oriented CMOS processes. Furthermore, TOPCon technology at the bulk contact is observed to be more important than that at the emitter contact; however, a combination of the two yields an improved <inline-formula> <tex-math notation="LaTeX">$\textit{V}_{\text{OC}}$</tex-math> </inline-formula> value. On applying the full TOPCon technology, <inline-formula> <tex-math notation="LaTeX">$\textit{V}_{\text{OC}}$</tex-math> </inline-formula> is improved by approximately 20 mV from 601 to 619 mV, and <inline-formula> <tex-math notation="LaTeX">$\eta$</tex-math> </inline-formula> is improved by approximately 0.5<inline-formula> <tex-math notation="LaTeX">$\%$</tex-math> </inline-formula> from 15.20<inline-formula> <tex-math notation="LaTeX">$\%$</tex-math> </inline-formula> to 15.73<inline-formula> <tex-math notation="LaTeX">$\%$</tex-math> </inline-formula> compared to the conventional surface diffusion (SD)-based structure.

  • Germanium-and Silicon-Nanotransistor Designs by Electrical and Thermal Self-Consistent Analysis

    Sugiura T., Yamakiri S., Nakano N.

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems （IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)   2023

    ISSN  02780070

    　View Summary

    This study evaluated nanometer gate length germanium (Ge) transistors, including the electrical and thermal components, and compared them with silicon (Si) transistors. Nanometer-scale Ge and Si junction-less field-effect transistors (JLFETs) were treated for both NFET and PFET devices under a transient response. Consequently, the electrical and thermal self-consistent simulations revealed that hole carrier transport is more challenging at the channel region for PFET, inhibiting process shrinking. Moreover, the results show that self-heating can reach a dangerous stature, particularly when the channel region is thick. This is because the operation of the nanometer-scale Ge and Si JLFETs depends on the quantum effect, which increases the band-gap energy. The suitable channel design for Ge and Si transistors is almost similar; a heavier doping concentration is favorable for Si transistors. The study concludes that optimizing the channel region to fit the band-gap energy is the most crucial aspect for designing transistors.

  • Back-Contact Interdigitated Carrier-Selective Cell: Numerical Demonstration of 30 mW/cm<sup>2</sup>; Output Power Density in Standard Albedo Condition

    Sugiura T., Nakano N.

    IEEE Transactions on Electron Devices （IEEE Transactions on Electron Devices)  69 （ 12 ） 7190 - 7193 2022.12

    ISSN  00189383

    　View Summary

    This brief proposes a new crystalline-Si (c-Si) solar cell structure, based on bifacial back-contact and carrier-selective contact solar cell technology. The proposed device, known as back-contact interdigitated carrier selective (BICS), offers the advantage of using existing c-Si solar cell structures. The bifaciality provided by the passivated emitter and rear cell (PERC), back-contact provided by interdigitated back contact (IBC), and carrier-selective contact provided by tunnel oxide passivated contact (TOPCon) are featured simultaneously. The local and full TOPCons are, respectively, applied to the emitter and back surface field (BSF) region. The proposed device has an output density of over 30 mW/cm2 under standard conditions-room temperature with a 20% albedo condition. A comparison with our previously proposed bifacial solar cell, heterojunction back contact (HBC)+, reveals the advantages of the proposed device. The proposed device is operable under a relatively low temperature under 45 °C, whereas HBC+ is suitable for higher temperatures. Therefore, the choice between the proposed device and HBC+ should be based on the climate of the installation location.

  • Hard- and soft-breakdown modeling in &lt;001&gt; oriented β -Ga<inf>2</inf>O<inf>3</inf>Schottky barrier diode

    Sugiura T., Nakano N.

    Journal of Applied Physics （Journal of Applied Physics)  132 （ 17 ）  2022.11

    ISSN  00218979

    　View Summary

    Gallium oxide (Ga 2 O 3) attracts considerable technological interest because of its high Baliga's figure-of-merit and high breakdown voltages. As the models for the breakdown behavior of n-doped Ga 2 O 3 that consider soft (barrier lowering) and hard (avalanche effect) breakdowns are still lacking, in this study, we model the breakdown operations in <001> oriented Schottky barrier diodes considering both the soft- and hard-breakdown phenomena. The completion of the impact ionization model of β- Ga 2 O 3 in <001> orientation is proposed by determining the hole impact ionization coefficient, thereby reproducing hard breakdown operations. Moreover, a barrier lowering model is determined for reproducing soft breakdown operations. The outcomes of the proposed modeling investigation are expected to be crucial for predicting the reverse-biased operations of β- Ga 2 O 3 in <001> orientation to facilitate further technological development and applications of Ga 2 O 3.

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Papers, etc., Registered in KOARA 【 Display / hide 】

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Presentations 【 Display / hide 】

  • An On-Chip Ultra-Low-Power Hz-Range Ring Oscillator Based on Dynamic Leakage Suppression Logic

    Jorge Cañada, Yui Yoshida, Hiroki Miura, Nobuhiko Nakano

    International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2020), 

    2020.07

  • Low-power High-Voltage Driver Based on Standard CMOS Technology for On-Chip Memory Recording

    Jorge Cañada, Yui Yoshida, Takashi Tonomura, Hiroki Miura, Nobihiko Nakano

    電子回路研究会 (日本大学理工学部駿河台校舎タワー・スコラ) , 

    2019.12
    , 

    Oral presentation (general), 電気学会

  • リングオシレータ用昇圧器付きクロスカップルチャージポンプ

    三浦 大毅, 吉田 祐威, 外村 崇史, Jorge Canada, 中野 誠彦

    電子回路研究会, 

    2019.12
    , 

    Oral presentation (general)

  • A delta-sigma modulator with frequency division multiplexing for multi-channel EEG acquisition front-end

    Mikawa M., Kawazoe S., Fukuoka R., Nakano N. 

    2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, 

    2019.11
    , 

    Poster presentation

  • Frequency Adjustable On-Chip Notch Filter to Eliminate Hum Noise for EEG Acquisition

    Ryuto Fukuoka, Syohei Kawazoe,Mikiyoshi Mikawa, and Nobuhiko Nakano

    2019 International Conference on Analog VLSI Circuits (Yilan, Taiwan) , 

    2019.10
    , 

    Oral presentation (general)

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Research Projects of Competitive Funds, etc. 【 Display / hide 】

  • 人工シナプス用多チャンネル膜電位固定LSIの実現

    2014
    -
    2017.03

    日本学術振興会, Grant-in-Aid for Scientific Research, Research grant, Principal investigator

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Awards 【 Display / hide 】

  • Certificate of Appreciation

    2020.06, IEICE Electronics Express Editorial Committee

    Type of Award： Other

  • Taiwan and Japan Conference on Circuits and Systems 2019 Best student paper award

    Jorge Canada, Nobuhiko Nakano, 2019.08, IEEE CASS, An On-Chip Sub-pW Hz-Range Ring Oscillator

    Type of Award： Award from international society, conference, symposium, etc.

  • LSIとシステムのワークショップ優秀ポスター賞

    2017.05, 電子情報通信学会, 標準CMOSプロセスによるオンチップ太陽電池の高性能化

  • エレクトロニクスソサエティ功労賞

    2017.03, 電子情報通信学会

    Type of Award： Award from publisher, newspaper, foundation, etc.

  • 電気学会 論文発表賞

    中野 誠彦, 1992, 電気学会

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Courses Taught 【 Display / hide 】

  • SEMINOR IN ELECTRONICS AND INFOTMATION ENGINEERING(2)

    2023

  • RECITATION IN ELECTRONICS AND INFORMATION ENGINEERING

    2023

  • NUMERICAL MODELING AND COMPUTATIONAL SIMULATION

    2023

  • LSI CIRCUIT DESIGN 1

    2023

  • LABORATORIES IN ELECTRONICS AND INFORMATION ENGINEERING(2)

    2023

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Courses Previously Taught 【 Display / hide 】

  • 電気電子工学実験第二

    Keio University

    2014.04
    -
    2015.03
    , 

    Autumn Semester, Laboratory work/practical work/exercise, Lecturer outside of Keio

  • 計算機構成

    Keio University

    2014.04
    -
    2015.03
    , 

    Autumn Semester, Lecture, Within own ｆaculty

  • 理工学基礎実験

    Keio University

    2014.04
    -
    2015.03
    , 

    Spring Semester, Laboratory work/practical work/exercise, Lecturer outside of Keio

  • 数値モデリングと計算機シミュレーション

    Keio University

    2014.04
    -
    2015.03
    , 

    Spring Semester, Lecture, Within own ｆaculty

  • 電気電子計測

    Keio University

    2014.04
    -
    2015.03
    , 

    Spring Semester, Lecture, Within own ｆaculty

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Memberships in Academic Societies 【 Display / hide 】

  • 電気学会, 

    1992
    -
    Present

  • 応用物理学会, 

    1992.02
    -
    Present

  • シリコンテクノロジー分科会, 

    2017.04
    -
    Present

  • プラズマエレクトロニクス分科会, 

    1996.03
    -
    2016.05

  • 電子通信情報学会, 

    2009
    -
    Present

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Committee Experiences 【 Display / hide 】

  • 2020.06
    -
    Present

    CAS研究会専門委員, 電子情報通信学会

  • 2020.04
    -
    Present

    電子・情報・システム部門　役員会　委員, 電気学会

  • 2020.04
    -
    Present

    電子・情報・システム部門編修委員会委員, 電気学会

  • 2020.04
    -
    2022.03

    サステナブルコンピューティング特別研究会委員長, 電子情報通信学会

  • 2020.04
    -
    2021.03

    2020年電子・情報・システム部門大会委員会　委員, 電気学会

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