Yoshioka, Kentaro

写真a

Affiliation

Faculty of Science and Technology, Department of Electronics and Electrical Engineering (Yagami)

Position

Assistant Professor/Senior Assistant Professor

Related Websites

 

Papers 【 Display / hide

  • An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging with a 40-Channel 0.0036-mm<sup>2</sup>Voltage/Time Dual-Data-Converter-Based AFE

    Kondo S., Kubota H., Katagiri H., Ota Y., Hirono M., Ta T.T., Okuni H., Ohtsuka S., Ojima Y., Sugimoto T., Ishii H., Yoshioka K., Kimura K., Sai A., Matsumoto N.

    IEEE Journal of Solid-State Circuits (IEEE Journal of Solid-State Circuits)  55 ( 11 ) 2866 - 2877 2020.11

    ISSN  00189200

     View Summary

    This article presents a 40-channel high-resolution automotive LiDAR system-on-chip (SoC), which utilizes the world's first dual-data converter (DDC). The proposed DDC consolidates the functions of ADC and TDC into a single circuitry and achieves acquisition of both high-precision time and voltage data from the input, realizing a 5 times smaller analog front-end (AFE) area than prior arts. Such innovations lead us to a 40-channel AFE integration of the SoC without silicon cost increase, which characterizes our LiDAR system with 2 times higher pixel resolution. To enhance the ADC's signal-to-noise and distortion ratio (SNDR) without sacrificing the area efficiency, a calibration-free and variation-tolerant voltage-controlled oscillator (VCO)-based ADC with a multiphase pulse density modulator (MP-PDM)-based feedback is proposed. Our proof-of-concept LiDAR system achieves a measurement range of 225 m at 70-klx direct sunlight, with a resolution of 240 times 192 pixels at 10 frames per second (FPS). To quantitatively measure the effect of the resolution improvement of our LiDAR, we evaluate the LiDAR's detection accuracy of small targets 75 m away. Due to the 2 times higher vertical pixel resolution, our LiDAR can detect targets with 2 times smaller height. The 3-D point cloud of the LiDAR captured outdoor in the wild is presented.

  • A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR

    Ta T.T., Kubota H., Kokubun K., Sugimoto T., Hirono M., Sengoku M., Katagiri H., Okuni H., Kondo S., Ohtsuka S., Kwon H., Sasaki K., Ota Y., Suzuki K., Kimura K., Yoshioka K., Sai A., Matsumoto N.

    IEEE Symposium on VLSI Circuits, Digest of Technical Papers (IEEE Symposium on VLSI Circuits, Digest of Technical Papers)  2020-June 2020.06

    ISSN  9781728199429

     View Summary

    This paper introduces several key RX techniques to realize a 200m-range and low-cost high-pixel-resolution solid-state LiDAR for autonomous self-driving systems. In-Sensor Scanning 2D-SPAD array can remove the mechanical mirror and improve the pixel-resolution by implying short dead time active-quenching SPADs. For ToF calculating SoC, we adopt the world first dual-data converter (DDC) which consolidates the functions of ADC and TDC into a single circuitry, achieving the acquisition of both high-precision time/voltage data from a single input. Such innovations lead us to 200m-range 300×80-pixel solid-state LiDAR RX under 70klux solar radiation.

  • A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm<sup>2</sup> Voltage/Time Dual-Data-Converter-Based AFE

    Kondo S., Kubota H., Katagiri H., Ota Y., Hirono M., Ta T.T., Okuni H., Ohtsuka S., Ojima Y., Sugimoto T., Ishii H., Yoshioka K., Kimura K., Sai A., Matsumoto N.

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Digest of Technical Papers - IEEE International Solid-State Circuits Conference)  2020-February   94 - 96 2020.02

    ISSN  9781728132044

     View Summary

    A safe and reliable self-driving system is a key enabling technology for a society without traffic jams or accidents; LiDAR plays an essential role for such systems. To ensure higher levels of safety and comfort, early detection of small objects (e.g., debris/children) is crucial. To achieve this, state-of-the-art LiDARs [1-3] must attain even more finely scaled pixel resolution: for example, a 0.1-degree angle resolution (a 2x finer resolution than [3]) is required to detect a 20×20cm2 object 100m away. However, hybrid LiDAR systems [3] require a pair of TDC/ADC AFEs per pixel to obtain both precise short-range (SR) distance measurement (DM) and 200m long-range (LR) DM. Scaling the pixel resolution will significantly enlarge the SoC area and explode its cost.

  • Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits

    Yoshioka K., Sugimoto T., Waki N., Kim S., Kurose D., Ishii H., Furuta M., Sai A., Ishikuro H., Itakura T.

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE Transactions on Very Large Scale Integration (VLSI) Systems)  27 ( 11 ) 2575 - 2586 2019.11

    ISSN  10638210

     View Summary

    To realize high-resolution pipelined and pipelined-SAR analog-to-digital-converters (ADCs), an accurate residue amplifier is necessary. However, realizing such an amplifier in scaled CMOS is challenging due to the worsened transistor characteristics. Prior works focused on gain calibration techniques to mitigate the use of low-gain amplifiers, in return of system complexity and prolonged startups. In this paper, we introduce a digital amplifier (DA) technique to realize power-efficient and accurate amplification in scaled CMOS. DA cancels out all errors (i.e., gain error, nonlinearity, incomplete settling, power supply noise, and thermal noise) of the low-gain amplifier by feedback based on successive approximation. The DA accuracy can be arbitrary set by configuring the number of bits in the DA capacitor digital-to-analog-converter; the amplifier gain is decoupled from the transistor intrinsic gain which is suitable for scaled CMOS integration. We also show that the power efficiency can be enhanced over conventional opamp-based designs with relaxed settling error requirements of DA-based multiplying digital-to-analog-converters (MDACs). Moreover, the circuit design of DA-based MDACs is further discussed. Measurement results of the calibration-free 0.7-V 12-bit 160-MS/s pipelined-SAR ADC implemented in 28-nm CMOS are reported. Without calibration, the ADC achieves signal-to-noise-and-distortion-ratio = 61.1 dB, figure-of-merit = 12.8 fJ/conv., which is over 3× improvement compared with conventional calibration-free high-speed pipelined ADCs. In addition, we evaluate the DA's process scalability by comparing the measured results of the DA-based MDAC prototyped in 65-and 28-nm CMOS. We observe 2×-3× improvement in speed, power, and area mainly resulting from the DA's process scalability.

  • An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators

    Toyama Y., Yoshioka K., Ban K., Maya S., Sai A., Onizuka K.

    IEEE Journal of Solid-State Circuits (IEEE Journal of Solid-State Circuits)  54 ( 10 ) 2730 - 2742 2019.10

    ISSN  00189200

     View Summary

    A small-gate-count 8 bit bidirectional phase-domain MAC (PMAC) circuit is proposed to minimize both area and energy consumption of extremely energy-efficient deep neural network (DNN) accelerators, targeting the Internet-of-Things (IoT) edge devices operating with very strict power budgets (e.g., energy harvesting). PMAC consumes significantly less energy than standard fully digital MACs, due to its efficient analog accumulation nature based on gated-ring oscillator (GRO). The architectural analysis of energy-efficient accelerators is performed, and the energy budget analysis is disclosed. Furthermore, theoretical analysis of PMAC is conducted and comparisons with the conventional analog approaches are shown. By exploiting the DNN digital quantization noise, we further improve the PMAC energy efficiency by designing the internal gain. The bidirectional architecture proposed in this paper achieves an area comparable to those of digital MACs and up to a fivefold improvement in power efficiency. Moreover, the system design constraints are relaxed by eliminating the phase error originating in leakage currents. An asynchronous readout technique and a two-step digital-to-time converter (DTC) to enhance system throughput and compact implementation, respectively, are presented for the first time. We also present DNN hardware-software co-training procedures to show further scaling of the PMAC efficiency. Utilizing such techniques, the measured PMAC achieves peak efficiency of 12.4 TOPS/W in 28 nm CMOS.

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Research Projects of Competitive Funds, etc. 【 Display / hide

  • LiDAR based Sensing System Focused on Privacy Preserving and Occlusions

    2021.08
    -
    2023.03

    MEXT,JSPS, Grant-in-Aid for Scientific Research, 吉岡 健太郎, Grant-in-Aid for Research Activity Start-up , Principal Investigator

 

Courses Taught 【 Display / hide

  • TOPICS IN ELECTRONICS AND INFORMATION ENGINEERING

    2021

  • RECITATION IN ELECTRONICS AND INFORMATION ENGINEERING

    2021

  • LABORATORIES IN SCIENCE AND TECHNOLOGY

    2021

  • LABORATORIES IN ELECTRONICS AND INFORMATION ENGINEERING(1)

    2021

  • BACHELOR'S THESIS

    2021