研究業績(原著論文・解説)
公開件数:41件     一覧情報の全データをタブ区切りテキスト形式でダウンロード
No. 掲載種別 単著・共著区分 タイトル 著者 誌名 出版者 巻号頁 出版日 ISSN DOI URL 概要 関連情報
1 研究論文(学術雑誌)
共著
High-Performance with an In-GPU Graph Database Cache

Shin Morishima, H...続きを表示
IEEE IT Professional

19/ 6, 58-64
2017/12





2 研究論文(学術雑誌)
共著
Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches

Yuta Tokusashi, H...続きを表示
IEEE Micro

37/ 5, 44-51
2017/10





3 研究論文(国際会議プロシーディングス)
共著
A Case for Uni-Directional Network Topologies in Large-Scale Clusters

Michihiro Koibuchi, ...続きを表示
International Conference on Cluster Computing (Cluster'17)

178-187
2017/09





4 研究論文(国際会議プロシーディングス)
共著
Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

Ryota Yasudo, Michih...続きを表示
International Conference on Parallel Processing (ICPP'17)

322-331
2017/08





5 研究論文(学術雑誌)
共著
Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

Ryota Yasudo, Hir...続きを表示
IEEE Transactions on Computers (TC)

66/ 4, 702-716
2017/04





6 研究論文(国際会議プロシーディングス)
共著
An FPGA-Based In-NIC Cache Approach for Lazy Learning Outlier Filtering

Ami Hayashi, Hiro...続きを表示
International Conference on Parallel, Distributed, and Network-Based Processing (PDP'17)

15-22
2017/03





7 研究論文(国際会議プロシーディングス)
共著
High-Bandwidth Low-Latency Approximate Interconnection Networks

Daichi Fujiki, Kiyo ...続きを表示
IEEE International Symposium on High-Performance Computer Architecture (HPCA'17)

469-480
2017/02





8 研究論文(国際会議プロシーディングス)
共著
Randomly Optimized Grid Graph for Low-Latency Interconnection Networks

Koji Nakano, Daisuke...続きを表示
International Conference on Parallel Processing (ICPP'16)

340-349
2016/08





9 研究論文(国際会議プロシーディングス)
共著
A Multilevel NOSQL Cache Design Combining In-NIC and In-Kernel Caches

Yuta Tokusashi, H...続きを表示
IEEE International Symposium on High Performance Interconnects (Hot Interconnects 24)

60-67
2016/08





10 研究論文(国際会議プロシーディングス)
共著
Randomizing Packet Memory Networks for Low-latency Processor-memory Communication

Daichi Fujiki, Hi...続きを表示
International Conference on Parallel, Distributed, and Network-Based Processing (PDP'16)

168-175
2016/02





11 研究論文(学術雑誌)
共著
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

Takahiro Kagami, ...続きを表示
IEEE Transactions on Very Large Scale Integration Systems (TVLSI)

24/ 2, 493-506
2016/02





12 研究論文(学術雑誌)
共著
A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface

Ami Hayashi, Yuta To...続きを表示
ACM SIGARCH Computer Architecture News (CAN)

43/ 4, 22-27
2015/09





13 研究論文(国際会議プロシーディングス)
共著
On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck

Ryota Yasudo, Hir...続きを表示
ACM/IEEE International Symposium on Networks-on-Chip (NOCS'15)

16:1-16:8
2015/09





14 研究論文(学術雑誌)
共著
Swap-and-randomize: A Method for Building Low-latency HPC Interconnects

Ikki Fujiwara, Michi...続きを表示
IEEE Transactions on Parallel and Distributed Systems (TPDS)

26/ 7, 2051-2060
2015/07





15 研究論文(国際会議プロシーディングス)
共著
Augmenting Low-latency HPC Network with Free-space Optical Links

Ikki Fujiwara, Michi...続きを表示
IEEE International Symposium on High-Performance Computer Architecture (HPCA'15)

390-401
2015/02





16 研究論文(学術雑誌)
共著
Performance Evaluations of Graph Database using CUDA and OpenMP-Compatible Libraries

Shin Morishima, H...続きを表示
ACM SIGARCH Computer Architecture News (CAN)

42/ 4, 75-80
2014/09





17 研究論文(国際会議プロシーディングス)
共著
Skywalk: a Topology for HPC Networks with Low-delay Switches

Ikki Fujiwara, Michi...続きを表示
IEEE International Parallel and Distributed Processing Symposium (IPDPS'14)

263-272
2014/05





18 研究論文(国際会議プロシーディングス)
共著
Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips

Hiroki Matsutani<...続きを表示
Design, Automation, and Test in Europe Conference (DATE'14)

1-6
2014/03





19 研究論文(学術雑誌)
共著
3-D NoC with Inductive-Coupling Links for Building-Block SiPs

Yasuhiro Take, Hi...続きを表示
IEEE Transactions on Computers (TC)

63/ 3, 748-763
2014/03





20 研究論文(学術雑誌)
共著
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface

Noriyuki Miura, Yusu...続きを表示
IEEE Micro

33/ 6, 6-15
2013/12





21 研究論文(国際会議プロシーディングス)
共著
Headfirst Sliding Routing: A Time-Based Routing Scheme for Bus-NoC Hybrid 3-D Architecture

Takahiro Kagami, ...続きを表示
ACM/IEEE International Symposium on Networks-on-Chip (NOCS'13)

29-36
2013/04





22 研究論文(国際会議プロシーディングス)
共著
Layout-conscious Random Topologies for HPC Off-chip Interconnects

Michihiro Koibuchi, ...続きを表示
IEEE International Symposium on High-Performance Computer Architecture (HPCA'13)

484-495
2013/02





23 研究論文(国際会議プロシーディングス)
共著
A Case for Wireless 3D NoCs for CMPs

Hiroki Matsutani<...続きを表示
Asia and South Pacific Design Automation Conference (ASP-DAC'13)

23-28
2013/01





24 研究論文(学術雑誌)
共著
Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems

Kazutoshi Suito, Rik...続きを表示
IEEE Micro

32/ 6, 52-61
2012/12





25 研究論文(国際会議プロシーディングス)
共著
A Case for Random Shortcut Topologies for HPC Interconnects

Michihiro Koibuchi, ...続きを表示
ACM/IEEE International Symposium on Computer Architecture (ISCA'12)

177-188
2012/06





26 研究論文(国際会議プロシーディングス)
共著
A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs

Hiroki Matsutani<...続きを表示
Asia and South Pacific Design Automation Conference (ASP-DAC'12)

407-412
2012/01





27 研究論文(学術雑誌)
共著
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

Hiroki Matsutani<...続きを表示
IEEE Transactions on Computers (TC)

60/ 6, 783-799
2011/06





28 研究論文(国際会議プロシーディングス)
共著
A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs

Hiroki Matsutani<...続きを表示
ACM/IEEE International Symposium on Networks-on-Chip (NOCS'11)

49-56
2011/05





29 研究論文(学術雑誌)
共著
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs

Hiroki Matsutani<...続きを表示
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD)

30/ 4, 520-533
2011/04





30 研究論文(国際会議プロシーディングス)
共著
Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs

Hiroki Matsutani<...続きを表示
ACM/IEEE International Symposium on Networks-on-Chip (NOCS'10)

61-68
2010/05





31 研究論文(国際会議プロシーディングス)
共著
MuCCRA-Cube: a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link

Shotaro Saito, Yoshi...続きを表示
International Conference on Field Programmable Logic and Applications (FPL'09)

6-11
2009/09





32 研究論文(学術雑誌)
共著
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network

Hiroki Matsutani<...続きを表示
IEEE Transactions on Parallel and Distributed Systems (TPDS)

20/ 8, 1126-1141
2009/08





33 研究論文(国際会議プロシーディングス)
共著
An On/Off Link Activation Method for Low-Power Ethernet in PC Clusters

Michihiro Koibuchi, ...続きを表示
IEEE International Parallel and Distributed Processing Symposium (IPDPS'09)

1-11
2009/05





34 研究論文(国際会議プロシーディングス)
共著
Prediction Router: Yet Another Low Latency On-Chip Router Architecture

Hiroki Matsutani<...続きを表示
IEEE International Symposium on High-Performance Computer Architecture (HPCA'09)

367-378
2009/02





35 研究論文(国際会議プロシーディングス)
共著
A Link Removal Methodology for Network-on-Chip on Reconfigurable Systems

Daihan Wang, Hiro...続きを表示
International Conference on Field Programmable Logic and Applications (FPL'08)

269-274
2008/09





36 研究論文(国際会議プロシーディングス)
共著
A Lightweight Fault-tolerant Mechanism for Network-on-chip

Michihiro Koibuchi, ...続きを表示
ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08)

13-22
2008/05





37 研究論文(国際会議プロシーディングス)
共著
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks

Hiroki Matsutani<...続きを表示
ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08)

23-32
2008/05





38 研究論文(国際会議プロシーディングス)
共著
Run-Time Power Gating of On-Chip Routers Using Look-Ahead Routing

Hiroki Matsutani<...続きを表示
Asia and South Pacific Design Automation Conference (ASP-DAC'08)

55-60
2008/01





39 研究論文(国際会議プロシーディングス)
共著
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs

Hiroki Matsutani<...続きを表示
International Conference on Parallel Processing (ICPP'07)

1-10
2007/09





40 研究論文(国際会議プロシーディングス)
共著
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems

Daihan Wang, Hiro...続きを表示
International Conference on Field Programmable Logic and Applications (FPL'07)

383-388
2007/08





41 研究論文(国際会議プロシーディングス)
共著
Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network

Hiroki Matsutani<...続きを表示
IEEE International Parallel and Distributed Processing Symposium (IPDPS'07)

1-10
2007/05